1// cmd/9c/9.out.h from Vita Nuova. 2// 3// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4// Portions Copyright © 1995-1997 C H Forsyth ([email protected]) 5// Portions Copyright © 1997-1999 Vita Nuova Limited 6// Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7// Portions Copyright © 2004,2006 Bruce Ellis 8// Portions Copyright © 2005-2007 C H Forsyth ([email protected]) 9// Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10// Portions Copyright © 2009 The Go Authors. All rights reserved. 11// 12// Permission is hereby granted, free of charge, to any person obtaining a copy 13// of this software and associated documentation files (the "Software"), to deal 14// in the Software without restriction, including without limitation the rights 15// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16// copies of the Software, and to permit persons to whom the Software is 17// furnished to do so, subject to the following conditions: 18// 19// The above copyright notice and this permission notice shall be included in 20// all copies or substantial portions of the Software. 21// 22// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28// THE SOFTWARE. 29 30package ppc64 31 32import "cmd/internal/obj" 33 34//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p ppc64 35 36/* 37 * powerpc 64 38 */ 39const ( 40 NSNAME = 8 41 NSYM = 50 42 NREG = 32 /* number of general registers */ 43 NFREG = 32 /* number of floating point registers */ 44) 45 46const ( 47 /* RBasePPC64 = 4096 */ 48 /* R0=4096 ... R31=4127 */ 49 REG_R0 = obj.RBasePPC64 + iota 50 REG_R1 51 REG_R2 52 REG_R3 53 REG_R4 54 REG_R5 55 REG_R6 56 REG_R7 57 REG_R8 58 REG_R9 59 REG_R10 60 REG_R11 61 REG_R12 62 REG_R13 63 REG_R14 64 REG_R15 65 REG_R16 66 REG_R17 67 REG_R18 68 REG_R19 69 REG_R20 70 REG_R21 71 REG_R22 72 REG_R23 73 REG_R24 74 REG_R25 75 REG_R26 76 REG_R27 77 REG_R28 78 REG_R29 79 REG_R30 80 REG_R31 81 82 // CR bits. Use Book 1, chapter 2 naming for bits. Keep aligned to 32 83 REG_CR0LT 84 REG_CR0GT 85 REG_CR0EQ 86 REG_CR0SO 87 REG_CR1LT 88 REG_CR1GT 89 REG_CR1EQ 90 REG_CR1SO 91 REG_CR2LT 92 REG_CR2GT 93 REG_CR2EQ 94 REG_CR2SO 95 REG_CR3LT 96 REG_CR3GT 97 REG_CR3EQ 98 REG_CR3SO 99 REG_CR4LT 100 REG_CR4GT 101 REG_CR4EQ 102 REG_CR4SO 103 REG_CR5LT 104 REG_CR5GT 105 REG_CR5EQ 106 REG_CR5SO 107 REG_CR6LT 108 REG_CR6GT 109 REG_CR6EQ 110 REG_CR6SO 111 REG_CR7LT 112 REG_CR7GT 113 REG_CR7EQ 114 REG_CR7SO 115 116 /* Align FPR and VSR vectors such that when masked with 0x3F they produce 117 an equivalent VSX register. */ 118 /* F0=4160 ... F31=4191 */ 119 REG_F0 120 REG_F1 121 REG_F2 122 REG_F3 123 REG_F4 124 REG_F5 125 REG_F6 126 REG_F7 127 REG_F8 128 REG_F9 129 REG_F10 130 REG_F11 131 REG_F12 132 REG_F13 133 REG_F14 134 REG_F15 135 REG_F16 136 REG_F17 137 REG_F18 138 REG_F19 139 REG_F20 140 REG_F21 141 REG_F22 142 REG_F23 143 REG_F24 144 REG_F25 145 REG_F26 146 REG_F27 147 REG_F28 148 REG_F29 149 REG_F30 150 REG_F31 151 152 /* V0=4192 ... V31=4223 */ 153 REG_V0 154 REG_V1 155 REG_V2 156 REG_V3 157 REG_V4 158 REG_V5 159 REG_V6 160 REG_V7 161 REG_V8 162 REG_V9 163 REG_V10 164 REG_V11 165 REG_V12 166 REG_V13 167 REG_V14 168 REG_V15 169 REG_V16 170 REG_V17 171 REG_V18 172 REG_V19 173 REG_V20 174 REG_V21 175 REG_V22 176 REG_V23 177 REG_V24 178 REG_V25 179 REG_V26 180 REG_V27 181 REG_V28 182 REG_V29 183 REG_V30 184 REG_V31 185 186 /* VS0=4224 ... VS63=4287 */ 187 REG_VS0 188 REG_VS1 189 REG_VS2 190 REG_VS3 191 REG_VS4 192 REG_VS5 193 REG_VS6 194 REG_VS7 195 REG_VS8 196 REG_VS9 197 REG_VS10 198 REG_VS11 199 REG_VS12 200 REG_VS13 201 REG_VS14 202 REG_VS15 203 REG_VS16 204 REG_VS17 205 REG_VS18 206 REG_VS19 207 REG_VS20 208 REG_VS21 209 REG_VS22 210 REG_VS23 211 REG_VS24 212 REG_VS25 213 REG_VS26 214 REG_VS27 215 REG_VS28 216 REG_VS29 217 REG_VS30 218 REG_VS31 219 REG_VS32 220 REG_VS33 221 REG_VS34 222 REG_VS35 223 REG_VS36 224 REG_VS37 225 REG_VS38 226 REG_VS39 227 REG_VS40 228 REG_VS41 229 REG_VS42 230 REG_VS43 231 REG_VS44 232 REG_VS45 233 REG_VS46 234 REG_VS47 235 REG_VS48 236 REG_VS49 237 REG_VS50 238 REG_VS51 239 REG_VS52 240 REG_VS53 241 REG_VS54 242 REG_VS55 243 REG_VS56 244 REG_VS57 245 REG_VS58 246 REG_VS59 247 REG_VS60 248 REG_VS61 249 REG_VS62 250 REG_VS63 251 252 REG_CR0 253 REG_CR1 254 REG_CR2 255 REG_CR3 256 REG_CR4 257 REG_CR5 258 REG_CR6 259 REG_CR7 260 261 // MMA accumulator registers, these shadow VSR 0-31 262 // e.g MMAx shadows VSRx*4-VSRx*4+3 or 263 // MMA0 shadows VSR0-VSR3 264 REG_A0 265 REG_A1 266 REG_A2 267 REG_A3 268 REG_A4 269 REG_A5 270 REG_A6 271 REG_A7 272 273 REG_MSR 274 REG_FPSCR 275 REG_CR 276 277 REG_SPECIAL = REG_CR0 278 279 REG_CRBIT0 = REG_CR0LT // An alias for a Condition Register bit 0 280 281 REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers 282 283 REG_XER = REG_SPR0 + 1 284 REG_LR = REG_SPR0 + 8 285 REG_CTR = REG_SPR0 + 9 286 287 REGZERO = REG_R0 /* set to zero */ 288 REGSP = REG_R1 289 REGSB = REG_R2 290 REGRET = REG_R3 291 REGARG = -1 /* -1 disables passing the first argument in register */ 292 REGRT1 = REG_R20 /* reserved for runtime, duffzero and duffcopy */ 293 REGRT2 = REG_R21 /* reserved for runtime, duffcopy */ 294 REGMIN = REG_R7 /* register variables allocated from here to REGMAX */ 295 REGCTXT = REG_R11 /* context for closures */ 296 REGTLS = REG_R13 /* C ABI TLS base pointer */ 297 REGMAX = REG_R27 298 REGEXT = REG_R30 /* external registers allocated from here down */ 299 REGG = REG_R30 /* G */ 300 REGTMP = REG_R31 /* used by the linker */ 301 FREGRET = REG_F0 302 FREGMIN = REG_F17 /* first register variable */ 303 FREGMAX = REG_F26 /* last register variable for 9g only */ 304 FREGEXT = REG_F26 /* first external register */ 305) 306 307// OpenPOWER ABI for Linux Supplement Power Architecture 64-Bit ELF V2 ABI 308// https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture 309var PPC64DWARFRegisters = map[int16]int16{} 310 311func init() { 312 // f assigns dwarfregister[from:to] = (base):(to-from+base) 313 f := func(from, to, base int16) { 314 for r := int16(from); r <= to; r++ { 315 PPC64DWARFRegisters[r] = r - from + base 316 } 317 } 318 f(REG_R0, REG_R31, 0) 319 f(REG_F0, REG_F31, 32) 320 f(REG_V0, REG_V31, 77) 321 f(REG_CR0, REG_CR7, 68) 322 323 f(REG_VS0, REG_VS31, 32) // overlaps F0-F31 324 f(REG_VS32, REG_VS63, 77) // overlaps V0-V31 325 PPC64DWARFRegisters[REG_LR] = 65 326 PPC64DWARFRegisters[REG_CTR] = 66 327 PPC64DWARFRegisters[REG_XER] = 76 328} 329 330/* 331 * GENERAL: 332 * 333 * compiler allocates R3 up as temps 334 * compiler allocates register variables R7-R27 335 * compiler allocates external registers R30 down 336 * 337 * compiler allocates register variables F17-F26 338 * compiler allocates external registers F26 down 339 */ 340const ( 341 BIG = 32768 - 8 342) 343 344const ( 345 /* mark flags */ 346 LABEL = 1 << 0 347 LEAF = 1 << 1 348 FLOAT = 1 << 2 349 BRANCH = 1 << 3 350 LOAD = 1 << 4 351 FCMP = 1 << 5 352 SYNC = 1 << 6 353 LIST = 1 << 7 354 FOLL = 1 << 8 355 NOSCHED = 1 << 9 356 PFX_X64B = 1 << 10 // A prefixed instruction crossing a 64B boundary 357) 358 359// Values for use in branch instruction BC 360// BC B0,BI,label 361// BO is type of branch + likely bits described below 362// BI is CR value + branch type 363// ex: BEQ CR2,label is BC 12,10,label 364// 12 = BO_BCR 365// 10 = BI_CR2 + BI_EQ 366 367const ( 368 BI_CR0 = 0 369 BI_CR1 = 4 370 BI_CR2 = 8 371 BI_CR3 = 12 372 BI_CR4 = 16 373 BI_CR5 = 20 374 BI_CR6 = 24 375 BI_CR7 = 28 376 BI_LT = 0 377 BI_GT = 1 378 BI_EQ = 2 379 BI_FU = 3 380) 381 382// Common values for the BO field. 383 384const ( 385 BO_ALWAYS = 20 // branch unconditionally 386 BO_BCTR = 16 // decrement ctr, branch on ctr != 0 387 BO_NOTBCTR = 18 // decrement ctr, branch on ctr == 0 388 BO_BCR = 12 // branch on cr value 389 BO_BCRBCTR = 8 // decrement ctr, branch on ctr != 0 and cr value 390 BO_NOTBCR = 4 // branch on not cr value 391) 392 393// Bit settings from the CR 394 395const ( 396 C_COND_LT = iota // 0 result is negative 397 C_COND_GT // 1 result is positive 398 C_COND_EQ // 2 result is zero 399 C_COND_SO // 3 summary overflow or FP compare w/ NaN 400) 401 402const ( 403 C_NONE = iota 404 C_REGP /* An even numbered gpr which can be used a gpr pair argument */ 405 C_REG /* Any gpr register */ 406 C_FREGP /* An even numbered fpr which can be used a fpr pair argument */ 407 C_FREG /* Any fpr register */ 408 C_VREG /* Any vector register */ 409 C_VSREGP /* An even numbered vsx register which can be used as a vsx register pair argument */ 410 C_VSREG /* Any vector-scalar register */ 411 C_CREG /* The condition registor (CR) */ 412 C_CRBIT /* A single bit of the CR register (0-31) */ 413 C_SPR /* special processor register */ 414 C_AREG /* MMA accumulator register */ 415 C_ZCON /* The constant zero */ 416 C_U1CON /* 1 bit unsigned constant */ 417 C_U2CON /* 2 bit unsigned constant */ 418 C_U3CON /* 3 bit unsigned constant */ 419 C_U4CON /* 4 bit unsigned constant */ 420 C_U5CON /* 5 bit unsigned constant */ 421 C_U8CON /* 8 bit unsigned constant */ 422 C_U15CON /* 15 bit unsigned constant */ 423 C_S16CON /* 16 bit signed constant */ 424 C_U16CON /* 16 bit unsigned constant */ 425 C_16CON /* Any constant which fits into 16 bits. Can be signed or unsigned */ 426 C_U31CON /* 31 bit unsigned constant */ 427 C_S32CON /* 32 bit signed constant */ 428 C_U32CON /* 32 bit unsigned constant */ 429 C_32CON /* Any constant which fits into 32 bits. Can be signed or unsigned */ 430 C_S34CON /* 34 bit signed constant */ 431 C_64CON /* Any constant which fits into 64 bits. Can be signed or unsigned */ 432 C_SACON /* $n(REG) where n <= int16 */ 433 C_LACON /* $n(REG) where n <= int32 */ 434 C_DACON /* $n(REG) where n <= int64 */ 435 C_BRA /* A short offset argument to a branching instruction */ 436 C_BRAPIC /* Like C_BRA, but requires an extra NOP for potential TOC restore by the linker. */ 437 C_ZOREG /* An $0+reg memory op */ 438 C_SOREG /* An $n+reg memory arg where n is a 16 bit signed offset */ 439 C_LOREG /* An $n+reg memory arg where n is a 32 bit signed offset */ 440 C_XOREG /* An reg+reg memory arg */ 441 C_FPSCR /* The fpscr register */ 442 C_LR /* The link register */ 443 C_CTR /* The count register */ 444 C_ANY /* Any argument */ 445 C_GOK /* A non-matched argument */ 446 C_ADDR /* A symbolic memory location */ 447 C_TLS_LE /* A thread local, local-exec, type memory arg */ 448 C_TLS_IE /* A thread local, initial-exec, type memory arg */ 449 C_TEXTSIZE /* An argument with Type obj.TYPE_TEXTSIZE */ 450 451 C_NCLASS /* must be the last */ 452) 453 454const ( 455 AADD = obj.ABasePPC64 + obj.A_ARCHSPECIFIC + iota 456 AADDCC 457 AADDIS 458 AADDV 459 AADDVCC 460 AADDC 461 AADDCCC 462 AADDCV 463 AADDCVCC 464 AADDME 465 AADDMECC 466 AADDMEVCC 467 AADDMEV 468 AADDE 469 AADDECC 470 AADDEVCC 471 AADDEV 472 AADDZE 473 AADDZECC 474 AADDZEVCC 475 AADDZEV 476 AADDEX 477 AAND 478 AANDCC 479 AANDN 480 AANDNCC 481 AANDISCC 482 ABC 483 ABCL 484 ABEQ 485 ABGE // not LT = G/E/U 486 ABGT 487 ABLE // not GT = L/E/U 488 ABLT 489 ABNE // not EQ = L/G/U 490 ABVC // Branch if float not unordered (also branch on not summary overflow) 491 ABVS // Branch if float unordered (also branch on summary overflow) 492 ABDNZ // Decrement CTR, and branch if CTR != 0 493 ABDZ // Decrement CTR, and branch if CTR == 0 494 ACMP 495 ACMPU 496 ACMPEQB 497 ACNTLZW 498 ACNTLZWCC 499 ACRAND 500 ACRANDN 501 ACREQV 502 ACRNAND 503 ACRNOR 504 ACROR 505 ACRORN 506 ACRXOR 507 ADIVW 508 ADIVWCC 509 ADIVWVCC 510 ADIVWV 511 ADIVWU 512 ADIVWUCC 513 ADIVWUVCC 514 ADIVWUV 515 AMODUD 516 AMODUW 517 AMODSD 518 AMODSW 519 AEQV 520 AEQVCC 521 AEXTSB 522 AEXTSBCC 523 AEXTSH 524 AEXTSHCC 525 AFABS 526 AFABSCC 527 AFADD 528 AFADDCC 529 AFADDS 530 AFADDSCC 531 AFCMPO 532 AFCMPU 533 AFCTIW 534 AFCTIWCC 535 AFCTIWZ 536 AFCTIWZCC 537 AFDIV 538 AFDIVCC 539 AFDIVS 540 AFDIVSCC 541 AFMADD 542 AFMADDCC 543 AFMADDS 544 AFMADDSCC 545 AFMOVD 546 AFMOVDCC 547 AFMOVDU 548 AFMOVS 549 AFMOVSU 550 AFMOVSX 551 AFMOVSZ 552 AFMSUB 553 AFMSUBCC 554 AFMSUBS 555 AFMSUBSCC 556 AFMUL 557 AFMULCC 558 AFMULS 559 AFMULSCC 560 AFNABS 561 AFNABSCC 562 AFNEG 563 AFNEGCC 564 AFNMADD 565 AFNMADDCC 566 AFNMADDS 567 AFNMADDSCC 568 AFNMSUB 569 AFNMSUBCC 570 AFNMSUBS 571 AFNMSUBSCC 572 AFRSP 573 AFRSPCC 574 AFSUB 575 AFSUBCC 576 AFSUBS 577 AFSUBSCC 578 AISEL 579 AMOVMW 580 ALBAR 581 ALHAR 582 ALSW 583 ALWAR 584 ALWSYNC 585 AMOVDBR 586 AMOVWBR 587 AMOVB 588 AMOVBU 589 AMOVBZ 590 AMOVBZU 591 AMOVH 592 AMOVHBR 593 AMOVHU 594 AMOVHZ 595 AMOVHZU 596 AMOVW 597 AMOVWU 598 AMOVFL 599 AMOVCRFS 600 AMTFSB0 601 AMTFSB0CC 602 AMTFSB1 603 AMTFSB1CC 604 AMULHW 605 AMULHWCC 606 AMULHWU 607 AMULHWUCC 608 AMULLW 609 AMULLWCC 610 AMULLWVCC 611 AMULLWV 612 ANAND 613 ANANDCC 614 ANEG 615 ANEGCC 616 ANEGVCC 617 ANEGV 618 ANOR 619 ANORCC 620 AOR 621 AORCC 622 AORN 623 AORNCC 624 AORIS 625 AREM 626 AREMU 627 ARFI 628 ARLWMI 629 ARLWMICC 630 ARLWNM 631 ARLWNMCC 632 ACLRLSLWI 633 ASLW 634 ASLWCC 635 ASRW 636 ASRAW 637 ASRAWCC 638 ASRWCC 639 ASTBCCC 640 ASTHCCC 641 ASTSW 642 ASTWCCC 643 ASUB 644 ASUBCC 645 ASUBVCC 646 ASUBC 647 ASUBCCC 648 ASUBCV 649 ASUBCVCC 650 ASUBME 651 ASUBMECC 652 ASUBMEVCC 653 ASUBMEV 654 ASUBV 655 ASUBE 656 ASUBECC 657 ASUBEV 658 ASUBEVCC 659 ASUBZE 660 ASUBZECC 661 ASUBZEVCC 662 ASUBZEV 663 ASYNC 664 AXOR 665 AXORCC 666 AXORIS 667 668 ADCBF 669 ADCBI 670 ADCBST 671 ADCBT 672 ADCBTST 673 ADCBZ 674 AEIEIO 675 AICBI 676 AISYNC 677 APTESYNC 678 ATLBIE 679 ATLBIEL 680 ATLBSYNC 681 ATW 682 683 ASYSCALL 684 AWORD 685 686 ARFCI 687 688 AFCPSGN 689 AFCPSGNCC 690 /* optional on 32-bit */ 691 AFRES 692 AFRESCC 693 AFRIM 694 AFRIMCC 695 AFRIP 696 AFRIPCC 697 AFRIZ 698 AFRIZCC 699 AFRIN 700 AFRINCC 701 AFRSQRTE 702 AFRSQRTECC 703 AFSEL 704 AFSELCC 705 AFSQRT 706 AFSQRTCC 707 AFSQRTS 708 AFSQRTSCC 709 710 /* 64-bit */ 711 712 ACNTLZD 713 ACNTLZDCC 714 ACMPW /* CMP with L=0 */ 715 ACMPWU 716 ACMPB 717 AFTDIV 718 AFTSQRT 719 ADIVD 720 ADIVDCC 721 ADIVDE 722 ADIVDECC 723 ADIVDEU 724 ADIVDEUCC 725 ADIVDVCC 726 ADIVDV 727 ADIVDU 728 ADIVDUCC 729 ADIVDUVCC 730 ADIVDUV 731 AEXTSW 732 AEXTSWCC 733 /* AFCFIW; AFCFIWCC */ 734 AFCFID 735 AFCFIDCC 736 AFCFIDU 737 AFCFIDUCC 738 AFCFIDS 739 AFCFIDSCC 740 AFCTID 741 AFCTIDCC 742 AFCTIDZ 743 AFCTIDZCC 744 ALDAR 745 AMOVD 746 AMOVDU 747 AMOVWZ 748 AMOVWZU 749 AMULHD 750 AMULHDCC 751 AMULHDU 752 AMULHDUCC 753 AMULLD 754 AMULLDCC 755 AMULLDVCC 756 AMULLDV 757 ARFID 758 ARLDMI 759 ARLDMICC 760 ARLDIMI 761 ARLDIMICC 762 ARLDC 763 ARLDCCC 764 ARLDCR 765 ARLDCRCC 766 ARLDICR 767 ARLDICRCC 768 ARLDCL 769 ARLDCLCC 770 ARLDICL 771 ARLDICLCC 772 ARLDIC 773 ARLDICCC 774 ACLRLSLDI 775 AROTL 776 AROTLW 777 ASLBIA 778 ASLBIE 779 ASLBMFEE 780 ASLBMFEV 781 ASLBMTE 782 ASLD 783 ASLDCC 784 ASRD 785 ASRAD 786 ASRADCC 787 ASRDCC 788 AEXTSWSLI 789 AEXTSWSLICC 790 ASTDCCC 791 ATD 792 ASETB 793 794 /* 64-bit pseudo operation */ 795 ADWORD 796 AREMD 797 AREMDU 798 799 /* more 64-bit operations */ 800 AHRFID 801 APOPCNTD 802 APOPCNTW 803 APOPCNTB 804 ACNTTZW 805 ACNTTZWCC 806 ACNTTZD 807 ACNTTZDCC 808 ACOPY 809 APASTECC 810 ADARN 811 AMADDHD 812 AMADDHDU 813 AMADDLD 814 815 /* Vector */ 816 ALVEBX 817 ALVEHX 818 ALVEWX 819 ALVX 820 ALVXL 821 ALVSL 822 ALVSR 823 ASTVEBX 824 ASTVEHX 825 ASTVEWX 826 ASTVX 827 ASTVXL 828 AVAND 829 AVANDC 830 AVNAND 831 AVOR 832 AVORC 833 AVNOR 834 AVXOR 835 AVEQV 836 AVADDUM 837 AVADDUBM 838 AVADDUHM 839 AVADDUWM 840 AVADDUDM 841 AVADDUQM 842 AVADDCU 843 AVADDCUQ 844 AVADDCUW 845 AVADDUS 846 AVADDUBS 847 AVADDUHS 848 AVADDUWS 849 AVADDSS 850 AVADDSBS 851 AVADDSHS 852 AVADDSWS 853 AVADDE 854 AVADDEUQM 855 AVADDECUQ 856 AVSUBUM 857 AVSUBUBM 858 AVSUBUHM 859 AVSUBUWM 860 AVSUBUDM 861 AVSUBUQM 862 AVSUBCU 863 AVSUBCUQ 864 AVSUBCUW 865 AVSUBUS 866 AVSUBUBS 867 AVSUBUHS 868 AVSUBUWS 869 AVSUBSS 870 AVSUBSBS 871 AVSUBSHS 872 AVSUBSWS 873 AVSUBE 874 AVSUBEUQM 875 AVSUBECUQ 876 AVMULESB 877 AVMULOSB 878 AVMULEUB 879 AVMULOUB 880 AVMULESH 881 AVMULOSH 882 AVMULEUH 883 AVMULOUH 884 AVMULESW 885 AVMULOSW 886 AVMULEUW 887 AVMULOUW 888 AVMULUWM 889 AVPMSUM 890 AVPMSUMB 891 AVPMSUMH 892 AVPMSUMW 893 AVPMSUMD 894 AVMSUMUDM 895 AVR 896 AVRLB 897 AVRLH 898 AVRLW 899 AVRLD 900 AVS 901 AVSLB 902 AVSLH 903 AVSLW 904 AVSL 905 AVSLO 906 AVSRB 907 AVSRH 908 AVSRW 909 AVSR 910 AVSRO 911 AVSLD 912 AVSRD 913 AVSA 914 AVSRAB 915 AVSRAH 916 AVSRAW 917 AVSRAD 918 AVSOI 919 AVSLDOI 920 AVCLZ 921 AVCLZB 922 AVCLZH 923 AVCLZW 924 AVCLZD 925 AVPOPCNT 926 AVPOPCNTB 927 AVPOPCNTH 928 AVPOPCNTW 929 AVPOPCNTD 930 AVCMPEQ 931 AVCMPEQUB 932 AVCMPEQUBCC 933 AVCMPEQUH 934 AVCMPEQUHCC 935 AVCMPEQUW 936 AVCMPEQUWCC 937 AVCMPEQUD 938 AVCMPEQUDCC 939 AVCMPGT 940 AVCMPGTUB 941 AVCMPGTUBCC 942 AVCMPGTUH 943 AVCMPGTUHCC 944 AVCMPGTUW 945 AVCMPGTUWCC 946 AVCMPGTUD 947 AVCMPGTUDCC 948 AVCMPGTSB 949 AVCMPGTSBCC 950 AVCMPGTSH 951 AVCMPGTSHCC 952 AVCMPGTSW 953 AVCMPGTSWCC 954 AVCMPGTSD 955 AVCMPGTSDCC 956 AVCMPNEZB 957 AVCMPNEZBCC 958 AVCMPNEB 959 AVCMPNEBCC 960 AVCMPNEH 961 AVCMPNEHCC 962 AVCMPNEW 963 AVCMPNEWCC 964 AVPERM 965 AVPERMXOR 966 AVPERMR 967 AVBPERMQ 968 AVBPERMD 969 AVSEL 970 AVSPLTB 971 AVSPLTH 972 AVSPLTW 973 AVSPLTISB 974 AVSPLTISH 975 AVSPLTISW 976 AVCIPH 977 AVCIPHER 978 AVCIPHERLAST 979 AVNCIPH 980 AVNCIPHER 981 AVNCIPHERLAST 982 AVSBOX 983 AVSHASIGMA 984 AVSHASIGMAW 985 AVSHASIGMAD 986 AVMRGEW 987 AVMRGOW 988 AVCLZLSBB 989 AVCTZLSBB 990 991 /* VSX */ 992 ALXV 993 ALXVL 994 ALXVLL 995 ALXVD2X 996 ALXVW4X 997 ALXVH8X 998 ALXVB16X 999 ALXVX 1000 ALXVDSX 1001 ASTXV 1002 ASTXVL 1003 ASTXVLL 1004 ASTXVD2X 1005 ASTXVW4X 1006 ASTXVH8X 1007 ASTXVB16X 1008 ASTXVX 1009 ALXSDX 1010 ASTXSDX 1011 ALXSIWAX 1012 ALXSIWZX 1013 ASTXSIWX 1014 AMFVSRD 1015 AMFFPRD 1016 AMFVRD 1017 AMFVSRWZ 1018 AMFVSRLD 1019 AMTVSRD 1020 AMTFPRD 1021 AMTVRD 1022 AMTVSRWA 1023 AMTVSRWZ 1024 AMTVSRDD 1025 AMTVSRWS 1026 AXXLAND 1027 AXXLANDC 1028 AXXLEQV 1029 AXXLNAND 1030 AXXLOR 1031 AXXLORC 1032 AXXLNOR 1033 AXXLORQ 1034 AXXLXOR 1035 AXXSEL 1036 AXXMRGHW 1037 AXXMRGLW 1038 AXXSPLTW 1039 AXXSPLTIB 1040 AXXPERM 1041 AXXPERMDI 1042 AXXSLDWI 1043 AXXBRQ 1044 AXXBRD 1045 AXXBRW 1046 AXXBRH 1047 AXSCVDPSP 1048 AXSCVSPDP 1049 AXSCVDPSPN 1050 AXSCVSPDPN 1051 AXVCVDPSP 1052 AXVCVSPDP 1053 AXSCVDPSXDS 1054 AXSCVDPSXWS 1055 AXSCVDPUXDS 1056 AXSCVDPUXWS 1057 AXSCVSXDDP 1058 AXSCVUXDDP 1059 AXSCVSXDSP 1060 AXSCVUXDSP 1061 AXVCVDPSXDS 1062 AXVCVDPSXWS 1063 AXVCVDPUXDS 1064 AXVCVDPUXWS 1065 AXVCVSPSXDS 1066 AXVCVSPSXWS 1067 AXVCVSPUXDS 1068 AXVCVSPUXWS 1069 AXVCVSXDDP 1070 AXVCVSXWDP 1071 AXVCVUXDDP 1072 AXVCVUXWDP 1073 AXVCVSXDSP 1074 AXVCVSXWSP 1075 AXVCVUXDSP 1076 AXVCVUXWSP 1077 AXSMAXJDP 1078 AXSMINJDP 1079 ALASTAOUT // The last instruction in this list. Also the first opcode generated by ppc64map. 1080 1081 // aliases 1082 ABR = obj.AJMP 1083 ABL = obj.ACALL 1084 ALAST = ALASTGEN // The final enumerated instruction value + 1. This is used to size the oprange table. 1085) 1086