1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_adc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L4xx_HAL_ADC_EX_H 22 #define STM32L4xx_HAL_ADC_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l4xx_hal_def.h" 30 31 /** @addtogroup STM32L4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup ADCEx 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief ADC Injected Conversion Oversampling structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Ratio; /*!< Configures the oversampling ratio. 50 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 51 52 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 53 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 54 } ADC_InjOversamplingTypeDef; 55 56 /** 57 * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected 58 * @note Parameters of this structure are shared within 2 scopes: 59 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset 60 * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, 61 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling. 62 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 63 * ADC state can be either: 64 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') 65 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. 66 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. 67 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going 68 * on ADC groups regular and injected. 69 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 70 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 71 */ 72 typedef struct 73 { 74 uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. 75 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 76 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 77 78 uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. 79 This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. 80 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 81 the new channel setting (or parameter number of conversions adjusted) */ 82 83 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 84 Unit: ADC clock cycles. 85 Conversion time is the addition of sampling time and processing time 86 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 87 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. 88 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 89 It overwrites the last setting. 90 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 91 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 92 Refer to device datasheet for timings values. */ 93 94 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. 95 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 96 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 97 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. 98 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 99 It overwrites the last setting. 100 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 101 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 102 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 103 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 104 of another parameter update on the fly) */ 105 106 uint32_t InjectedOffsetNumber; /*!< Selects the offset number. 107 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. 108 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 109 110 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. 111 Offset value must be a positive number. 112 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 113 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 114 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 115 without continuous mode or external trigger that could launch a conversion). */ 116 117 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. 118 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 119 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 120 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 121 configure a channel on injected group can impact the configuration of other channels previously set. */ 122 123 FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence 124 (main sequence subdivided in successive parts). 125 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 126 Discontinuous mode can be enabled only if continuous mode is disabled. 127 This parameter can be set to ENABLE or DISABLE. 128 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 129 Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). 130 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 131 configure a channel on injected group can impact the configuration of other channels previously set. */ 132 133 FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one 134 This parameter can be set to ENABLE or DISABLE. 135 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) 136 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) 137 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. 138 To maintain JAUTO always enabled, DMA must be configured in circular mode. 139 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 140 configure a channel on injected group can impact the configuration of other channels previously set. */ 141 142 FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. 143 This parameter can be set to ENABLE or DISABLE. 144 If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a 145 new injected context is set when queue is full, error is triggered by interruption and through function 146 'HAL_ADCEx_InjectedQueueOverflowCallback'. 147 Caution: This feature request that the sequence is fully configured before injected conversion start. 148 Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. 149 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 150 configure a channel on injected group can impact the configuration of other channels previously set. 151 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ 152 153 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. 154 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 155 This parameter can be a value of @ref ADC_injected_external_trigger_source. 156 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 157 configure a channel on injected group can impact the configuration of other channels previously set. */ 158 159 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 160 This parameter can be a value of @ref ADC_injected_external_trigger_edge. 161 If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. 162 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 163 configure a channel on injected group can impact the configuration of other channels previously set. */ 164 165 FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. 166 This parameter can be set to ENABLE or DISABLE. 167 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 168 169 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. 170 Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. 171 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 172 } ADC_InjectionConfTypeDef; 173 174 #if defined(ADC_MULTIMODE_SUPPORT) 175 /** 176 * @brief Structure definition of ADC multimode 177 * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). 178 * Both Master and Slave ADCs must be disabled. 179 */ 180 typedef struct 181 { 182 uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. 183 This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ 184 185 uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC: 186 selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master) 187 This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */ 188 189 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 190 This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. 191 Delay range depends on selected resolution: 192 from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, 193 from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */ 194 } ADC_MultiModeTypeDef; 195 #endif /* ADC_MULTIMODE_SUPPORT */ 196 197 /** 198 * @} 199 */ 200 201 /* Exported constants --------------------------------------------------------*/ 202 203 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants 204 * @{ 205 */ 206 207 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source 208 * @{ 209 */ 210 /* ADC group regular trigger sources for all ADC instances */ 211 #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ 212 #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 213 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ 214 #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 215 #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 216 #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 217 #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 218 #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 219 #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 220 #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 221 #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 222 #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ 223 #define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 224 #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 225 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ 226 #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ 227 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 228 /** 229 * @} 230 */ 231 232 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) 233 * @{ 234 */ 235 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ 236 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ 237 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ 238 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ 239 /** 240 * @} 241 */ 242 243 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending 244 * @{ 245 */ 246 #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ 247 #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ 248 /** 249 * @} 250 */ 251 252 /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number 253 * @{ 254 */ 255 #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ 256 #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 257 #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 258 #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 259 #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 260 /** 261 * @} 262 */ 263 264 /** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 265 * @{ 266 */ 267 #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ 268 #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ 269 #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ 270 #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ 271 /** 272 * @} 273 */ 274 275 #if defined(ADC_MULTIMODE_SUPPORT) 276 /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode 277 * @{ 278 */ 279 #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */ 280 #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */ 281 #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */ 282 #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */ 283 #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 284 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 285 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 286 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ 287 288 /** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution 289 * @{ 290 */ 291 #define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ 292 #define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ 293 #define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ 294 /** 295 * @} 296 */ 297 298 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 299 * @{ 300 */ 301 #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ 302 #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ 303 #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ 304 #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ 305 #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ 306 #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ 307 #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ 308 #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ 309 #define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ 310 #define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ 311 #define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ 312 #define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ 313 /** 314 * @} 315 */ 316 317 /** 318 * @} 319 */ 320 #endif /* ADC_MULTIMODE_SUPPORT */ 321 322 /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups 323 * @{ 324 */ 325 #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ 326 #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ 327 #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ 328 /** 329 * @} 330 */ 331 332 /** @defgroup ADC_CFGR_fields ADCx CFGR fields 333 * @{ 334 */ 335 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 336 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 337 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 338 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 339 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 340 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 341 ADC_CFGR_RES | ADC_CFGR_DFSDMCFG | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) 342 #else 343 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 344 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 345 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 346 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 347 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 348 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) 349 #endif 350 /** 351 * @} 352 */ 353 354 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields 355 * @{ 356 */ 357 #if defined(ADC_SMPR1_SMPPLUS) 358 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 359 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 360 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 361 ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS) 362 #else 363 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 364 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 365 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 366 ADC_SMPR1_SMP0) 367 #endif 368 /** 369 * @} 370 */ 371 372 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 373 * @{ 374 */ 375 /* ADC_CFGR fields of parameters that can be updated when no conversion 376 (neither regular nor injected) is on-going */ 377 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 378 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY | ADC_CFGR_DFSDMCFG)) 379 #else 380 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY)) 381 #endif 382 /** 383 * @} 384 */ 385 386 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 387 /** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data 388 * @{ 389 */ 390 #define ADC_DFSDM_MODE_DISABLE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */ 391 #define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ 392 /** 393 * @} 394 */ 395 #endif 396 397 /** 398 * @} 399 */ 400 401 /* Exported macros -----------------------------------------------------------*/ 402 403 #if defined(ADC_MULTIMODE_SUPPORT) 404 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros 405 * @{ 406 */ 407 408 /** @brief Force ADC instance in multimode mode independent (multimode disable). 409 * @note This macro must be used only in case of transition from multimode 410 * to mode independent and in case of unknown previous state, 411 * to ensure ADC configuration is in mode independent. 412 * @note Standard way of multimode configuration change is done from 413 * HAL ADC handle of ADC master using function 414 * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". 415 * Usage of this macro is not the Standard way of multimode 416 * configuration and can lead to have HAL ADC handles status 417 * misaligned. Usage of this macro must be limited to cases 418 * mentionned above. 419 * @param __HANDLE__ ADC handle. 420 * @retval None 421 */ 422 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ 423 LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) 424 425 /** 426 * @} 427 */ 428 #endif /* ADC_MULTIMODE_SUPPORT */ 429 430 /* Private macros ------------------------------------------------------------*/ 431 432 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros 433 * @{ 434 */ 435 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 436 /* code of final user. */ 437 438 /** 439 * @brief Test if conversion trigger of injected group is software start 440 * or external trigger. 441 * @param __HANDLE__ ADC handle. 442 * @retval SET (software start) or RESET (external trigger). 443 */ 444 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 445 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) 446 447 /** 448 * @brief Check if conversion is on going on regular or injected groups. 449 * @param __HANDLE__ ADC handle. 450 * @retval SET (conversion is on going) or RESET (no conversion is on going). 451 */ 452 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ 453 (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \ 454 ) ? RESET : SET) 455 456 /** 457 * @brief Check if conversion is on going on injected group. 458 * @param __HANDLE__ ADC handle. 459 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) 460 */ 461 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ 462 (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance)) 463 464 /** 465 * @brief Check whether or not ADC is independent. 466 * @param __HANDLE__ ADC handle. 467 * @note When multimode feature is not available, the macro always returns SET. 468 * @retval SET (ADC is independent) or RESET (ADC is not). 469 */ 470 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 471 #define ADC_IS_INDEPENDENT(__HANDLE__) \ 472 ( ( ( ((__HANDLE__)->Instance) == ADC3) \ 473 )? \ 474 SET \ 475 : \ 476 RESET \ 477 ) 478 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 479 #define ADC_IS_INDEPENDENT(__HANDLE__) (SET) 480 #elif defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) 481 #define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) 482 #endif 483 484 /** 485 * @brief Set the selected injected Channel rank. 486 * @param __CHANNELNB__ Channel number. 487 * @param __RANKNB__ Rank number. 488 * @retval None 489 */ 490 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) 491 492 /** 493 * @brief Configure ADC injected context queue 494 * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. 495 * @retval None 496 */ 497 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) 498 499 /** 500 * @brief Configure ADC discontinuous conversion mode for injected group 501 * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. 502 * @retval None 503 */ 504 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) 505 506 /** 507 * @brief Configure ADC discontinuous conversion mode for regular group 508 * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. 509 * @retval None 510 */ 511 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) 512 513 /** 514 * @brief Configure the number of discontinuous conversions for regular group. 515 * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. 516 * @retval None 517 */ 518 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) 519 520 /** 521 * @brief Configure the ADC auto delay mode. 522 * @param __AUTOWAIT__ Auto delay bit enable or disable. 523 * @retval None 524 */ 525 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) 526 527 /** 528 * @brief Configure ADC continuous conversion mode. 529 * @param __CONTINUOUS_MODE__ Continuous mode. 530 * @retval None 531 */ 532 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) 533 534 /** 535 * @brief Configure the ADC DMA continuous request. 536 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 537 * @retval None 538 */ 539 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos) 540 541 /** 542 * @brief Configure the channel number into offset OFRx register. 543 * @param __CHANNEL__ ADC Channel. 544 * @retval None 545 */ 546 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos) 547 548 /** 549 * @brief Configure the channel number into differential mode selection register. 550 * @param __CHANNEL__ ADC Channel. 551 * @retval None 552 */ 553 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__)) 554 555 /** 556 * @brief Configure calibration factor in differential mode to be set into calibration register. 557 * @param __CALIBRATION_FACTOR__ Calibration factor value. 558 * @retval None 559 */ 560 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos) 561 562 /** 563 * @brief Calibration factor in differential mode to be retrieved from calibration register. 564 * @param __CALIBRATION_FACTOR__ Calibration factor value. 565 * @retval None 566 */ 567 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos) 568 569 /** 570 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. 571 * @param __THRESHOLD__ Threshold value. 572 * @retval None 573 */ 574 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL) 575 576 #if defined(ADC_MULTIMODE_SUPPORT) 577 /** 578 * @brief Configure the ADC DMA continuous request for ADC multimode. 579 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 580 * @retval None 581 */ 582 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) 583 #endif /* ADC_MULTIMODE_SUPPORT */ 584 585 /** 586 * @brief Shift the offset with respect to the selected ADC resolution. 587 * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. 588 * If resolution 12 bits, no shift. 589 * If resolution 10 bits, shift of 2 ranks on the left. 590 * If resolution 8 bits, shift of 4 ranks on the left. 591 * If resolution 6 bits, shift of 6 ranks on the left. 592 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 593 * @param __HANDLE__ ADC handle 594 * @param __OFFSET__ Value to be shifted 595 * @retval None 596 */ 597 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 598 ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) 599 600 /** 601 * @brief Shift the AWD1 threshold with respect to the selected ADC resolution. 602 * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. 603 * If resolution 12 bits, no shift. 604 * If resolution 10 bits, shift of 2 ranks on the left. 605 * If resolution 8 bits, shift of 4 ranks on the left. 606 * If resolution 6 bits, shift of 6 ranks on the left. 607 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 608 * @param __HANDLE__ ADC handle 609 * @param __THRESHOLD__ Value to be shifted 610 * @retval None 611 */ 612 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 613 ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) 614 615 /** 616 * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. 617 * @note Thresholds have to be left-aligned on bit 7. 618 * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded). 619 * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). 620 * If resolution 8 bits, no shift. 621 * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0). 622 * @param __HANDLE__ ADC handle 623 * @param __THRESHOLD__ Value to be shifted 624 * @retval None 625 */ 626 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 627 ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \ 628 ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ 629 ((__THRESHOLD__) << 2UL) \ 630 ) 631 632 /** 633 * @brief Clear Common Control Register. 634 * @param __HANDLE__ ADC handle. 635 * @retval None 636 */ 637 #if defined(ADC_MULTIMODE_SUPPORT) 638 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ 639 ADC_CCR_CKMODE | \ 640 ADC_CCR_PRESC | \ 641 ADC_CCR_VBATEN | \ 642 ADC_CCR_TSEN | \ 643 ADC_CCR_VREFEN | \ 644 ADC_CCR_MDMA | \ 645 ADC_CCR_DMACFG | \ 646 ADC_CCR_DELAY | \ 647 ADC_CCR_DUAL) 648 #else 649 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ 650 ADC_CCR_CKMODE | \ 651 ADC_CCR_PRESC | \ 652 ADC_CCR_VBATEN | \ 653 ADC_CCR_TSEN | \ 654 ADC_CCR_VREFEN) 655 656 #endif /* ADC_MULTIMODE_SUPPORT */ 657 658 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) 659 /** 660 * @brief Set handle instance of the ADC slave associated to the ADC master. 661 * @param __HANDLE_MASTER__ ADC master handle. 662 * @param __HANDLE_SLAVE__ ADC slave handle. 663 * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. 664 * @retval None 665 */ 666 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 667 ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) ) 668 #endif /* defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 669 670 671 /** 672 * @brief Verify the ADC instance connected to the temperature sensor. 673 * @param __HANDLE__ ADC handle. 674 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 675 */ 676 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 677 /* The temperature sensor measurement path (channel 17) is available on ADC1 */ 678 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 679 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 680 /* The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */ 681 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) 682 #endif 683 684 /** 685 * @brief Verify the ADC instance connected to the battery voltage VBAT. 686 * @param __HANDLE__ ADC handle. 687 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 688 */ 689 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 690 /* The battery voltage measurement path (channel 18) is available on ADC1 */ 691 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 692 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 693 /* The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */ 694 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) 695 #endif 696 697 /** 698 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. 699 * @param __HANDLE__ ADC handle. 700 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 701 */ 702 /* The internal voltage reference VREFINT measurement path (channel 0) is available on ADC1 */ 703 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 704 705 /** 706 * @brief Verify the length of scheduled injected conversions group. 707 * @param __LENGTH__ number of programmed conversions. 708 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) 709 */ 710 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) 711 712 /** 713 * @brief Calibration factor size verification (7 bits maximum). 714 * @param __CALIBRATION_FACTOR__ Calibration factor value. 715 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 716 */ 717 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) 718 719 720 /** 721 * @brief Verify the ADC channel setting. 722 * @param __HANDLE__ ADC handle. 723 * @param __CHANNEL__ programmed ADC channel. 724 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 725 */ 726 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 727 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \ 728 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 729 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 730 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 731 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 732 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 733 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 734 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 735 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 736 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 737 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 738 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 739 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 740 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 741 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 742 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 743 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 744 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 745 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 746 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 747 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 748 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 749 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1) || \ 750 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2))) 751 #elif defined (STM32L412xx) || defined (STM32L422xx) 752 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ 753 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 754 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 755 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 756 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 757 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 758 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 759 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 760 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 761 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 762 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 763 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 764 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 765 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 766 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 767 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 768 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 769 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 770 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 771 ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \ 772 ((((__HANDLE__)->Instance) == ADC2) && \ 773 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 774 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 775 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 776 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 777 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 778 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 779 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 780 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 781 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 782 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 783 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 784 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 785 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 786 ((__CHANNEL__) == ADC_CHANNEL_16) ))) 787 #elif defined (STM32L4P5xx) || defined (STM32L4Q5xx) 788 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ 789 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 790 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 791 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 792 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 793 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 794 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 795 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 796 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 797 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 798 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 799 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 800 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 801 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 802 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 803 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 804 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 805 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 806 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 807 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 808 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 809 ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \ 810 ((((__HANDLE__)->Instance) == ADC2) && \ 811 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 812 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 813 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 814 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 815 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 816 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 817 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 818 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 819 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 820 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 821 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 822 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 823 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 824 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 825 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 826 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 827 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 828 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 829 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2)|| \ 830 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2) ))) 831 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 832 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ 833 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 834 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 835 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 836 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 837 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 838 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 839 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 840 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 841 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 842 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 843 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 844 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 845 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 846 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 847 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 848 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 849 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 850 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 851 ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \ 852 ((((__HANDLE__)->Instance) == ADC2) && \ 853 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 854 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 855 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 856 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 857 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 858 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 859 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 860 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 861 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 862 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 863 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 864 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 865 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 866 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 867 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 868 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 869 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 870 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 871 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2) || \ 872 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2))) || \ 873 ((((__HANDLE__)->Instance) == ADC3) && \ 874 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 875 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 876 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 877 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 878 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 879 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 880 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 881 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 882 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 883 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 884 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 885 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 886 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 887 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 888 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 889 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 890 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC3) || \ 891 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC3) ))) 892 #endif 893 894 /** 895 * @brief Verify the ADC channel setting in differential mode. 896 * @param __HANDLE__ ADC handle. 897 * @param __CHANNEL__ programmed ADC channel. 898 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 899 */ 900 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 901 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 902 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 903 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 904 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 905 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 906 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 907 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 908 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 909 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 910 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 911 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 912 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 913 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 914 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 915 ((__CHANNEL__) == ADC_CHANNEL_15) ) 916 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 917 /* For ADC1 and ADC2, channels 1 to 15 are available in differential mode, 918 channels 0, 16 to 18 can be only used in single-ended mode. 919 For ADC3, channels 1 to 3 and 6 to 12 are available in differential mode, 920 channels 4, 5 and 13 to 18 can only be used in single-ended mode. */ 921 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ((((((__HANDLE__)->Instance) == ADC1) || \ 922 (((__HANDLE__)->Instance) == ADC2)) && \ 923 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 924 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 925 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 926 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 927 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 928 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 929 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 930 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 931 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 932 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 933 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 934 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 935 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 936 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 937 ((__CHANNEL__) == ADC_CHANNEL_15))) || \ 938 ((((__HANDLE__)->Instance) == ADC3) && \ 939 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 940 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 941 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 942 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 943 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 944 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 945 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 946 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 947 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 948 ((__CHANNEL__) == ADC_CHANNEL_12) ))) 949 #endif 950 951 /** 952 * @brief Verify the ADC single-ended input or differential mode setting. 953 * @param __SING_DIFF__ programmed channel setting. 954 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) 955 */ 956 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ 957 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) 958 959 /** 960 * @brief Verify the ADC offset management setting. 961 * @param __OFFSET_NUMBER__ ADC offset management. 962 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) 963 */ 964 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ 965 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ 966 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ 967 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ 968 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) 969 970 /** 971 * @brief Verify the ADC injected channel setting. 972 * @param __CHANNEL__ programmed ADC injected channel. 973 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 974 */ 975 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ 976 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ 977 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ 978 ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) 979 980 /** 981 * @brief Verify the ADC injected conversions external trigger. 982 * @param __HANDLE__ ADC handle. 983 * @param __INJTRIG__ programmed ADC injected conversions external trigger. 984 * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) 985 */ 986 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 987 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 988 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 989 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 990 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 991 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 992 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 993 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 994 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 995 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 996 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 997 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 998 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 999 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 1000 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 1001 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 1002 ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) 1003 1004 /** 1005 * @brief Verify the ADC edge trigger setting for injected group. 1006 * @param __EDGE__ programmed ADC edge trigger setting. 1007 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 1008 */ 1009 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 1010 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 1011 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 1012 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 1013 1014 #if defined(ADC_MULTIMODE_SUPPORT) 1015 /** 1016 * @brief Verify the ADC multimode setting. 1017 * @param __MODE__ programmed ADC multimode setting. 1018 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1019 */ 1020 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ 1021 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ 1022 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ 1023 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ 1024 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ 1025 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ 1026 ((__MODE__) == ADC_DUALMODE_INTERL) || \ 1027 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) 1028 1029 /** 1030 * @brief Verify the ADC multimode DMA access setting. 1031 * @param __MODE__ programmed ADC multimode DMA access setting. 1032 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1033 */ 1034 #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ 1035 ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \ 1036 ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) ) 1037 1038 /** 1039 * @brief Verify the ADC multimode delay setting. 1040 * @param __DELAY__ programmed ADC multimode delay setting. 1041 * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) 1042 */ 1043 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ 1044 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ 1045 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ 1046 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ 1047 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 1048 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 1049 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 1050 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 1051 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ 1052 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ 1053 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ 1054 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) 1055 #endif /* ADC_MULTIMODE_SUPPORT */ 1056 1057 /** 1058 * @brief Verify the ADC analog watchdog setting. 1059 * @param __WATCHDOG__ programmed ADC analog watchdog setting. 1060 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) 1061 */ 1062 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ 1063 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ 1064 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) 1065 1066 /** 1067 * @brief Verify the ADC analog watchdog mode setting. 1068 * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. 1069 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) 1070 */ 1071 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ 1072 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 1073 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 1074 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 1075 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 1076 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 1077 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 1078 1079 /** 1080 * @brief Verify the ADC conversion (regular or injected or both). 1081 * @param __CONVERSION__ ADC conversion group. 1082 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) 1083 */ 1084 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ 1085 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ 1086 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) 1087 1088 /** 1089 * @brief Verify the ADC event type. 1090 * @param __EVENT__ ADC event. 1091 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) 1092 */ 1093 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ 1094 ((__EVENT__) == ADC_AWD_EVENT) || \ 1095 ((__EVENT__) == ADC_AWD2_EVENT) || \ 1096 ((__EVENT__) == ADC_AWD3_EVENT) || \ 1097 ((__EVENT__) == ADC_OVR_EVENT) || \ 1098 ((__EVENT__) == ADC_JQOVF_EVENT) ) 1099 1100 /** 1101 * @brief Verify the ADC oversampling ratio. 1102 * @param __RATIO__ programmed ADC oversampling ratio. 1103 * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) 1104 */ 1105 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ 1106 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ 1107 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ 1108 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ 1109 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ 1110 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ 1111 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ 1112 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) 1113 1114 /** 1115 * @brief Verify the ADC oversampling shift. 1116 * @param __SHIFT__ programmed ADC oversampling shift. 1117 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 1118 */ 1119 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 1120 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 1121 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 1122 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 1123 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 1124 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 1125 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 1126 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 1127 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) 1128 1129 /** 1130 * @brief Verify the ADC oversampling triggered mode. 1131 * @param __MODE__ programmed ADC oversampling triggered mode. 1132 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1133 */ 1134 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 1135 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 1136 1137 /** 1138 * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 1139 * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. 1140 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1141 */ 1142 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ 1143 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) 1144 1145 /** 1146 * @brief Verify the DFSDM mode configuration. 1147 * @param __HANDLE__ ADC handle. 1148 * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For 1149 * this reason, the input parameter is the ADC handle and not the configuration parameter 1150 * directly. 1151 * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) 1152 */ 1153 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 1154 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \ 1155 ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) ) 1156 #else 1157 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) 1158 #endif 1159 1160 /** 1161 * @brief Return the DFSDM configuration mode. 1162 * @param __HANDLE__ ADC handle. 1163 * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). 1164 * For this reason, the input parameter is the ADC handle and not the configuration parameter 1165 * directly. 1166 * @retval DFSDM configuration mode 1167 */ 1168 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 1169 #define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig) 1170 #else 1171 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) 1172 #endif 1173 1174 /** 1175 * @} 1176 */ 1177 1178 1179 /* Exported functions --------------------------------------------------------*/ 1180 /** @addtogroup ADCEx_Exported_Functions 1181 * @{ 1182 */ 1183 1184 /** @addtogroup ADCEx_Exported_Functions_Group1 1185 * @{ 1186 */ 1187 /* IO operation functions *****************************************************/ 1188 1189 /* ADC calibration */ 1190 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 1191 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 1192 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, 1193 uint32_t CalibrationFactor); 1194 1195 /* Blocking mode: Polling */ 1196 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); 1197 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); 1198 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1199 1200 /* Non-blocking mode: Interruption */ 1201 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); 1202 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); 1203 1204 #if defined(ADC_MULTIMODE_SUPPORT) 1205 /* ADC multimode */ 1206 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1207 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1208 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); 1209 #endif /* ADC_MULTIMODE_SUPPORT */ 1210 1211 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1212 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); 1213 1214 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 1215 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); 1216 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); 1217 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); 1218 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); 1219 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); 1220 1221 /* ADC group regular conversions stop */ 1222 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); 1223 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); 1224 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); 1225 #if defined(ADC_MULTIMODE_SUPPORT) 1226 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1227 #endif /* ADC_MULTIMODE_SUPPORT */ 1228 1229 /** 1230 * @} 1231 */ 1232 1233 /** @addtogroup ADCEx_Exported_Functions_Group2 1234 * @{ 1235 */ 1236 /* Peripheral Control functions ***********************************************/ 1237 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected); 1238 #if defined(ADC_MULTIMODE_SUPPORT) 1239 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); 1240 #endif /* ADC_MULTIMODE_SUPPORT */ 1241 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); 1242 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); 1243 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); 1244 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); 1245 1246 /** 1247 * @} 1248 */ 1249 1250 /** 1251 * @} 1252 */ 1253 1254 /** 1255 * @} 1256 */ 1257 1258 /** 1259 * @} 1260 */ 1261 1262 #ifdef __cplusplus 1263 } 1264 #endif 1265 1266 #endif /* STM32L4xx_HAL_ADC_EX_H */ 1267 1268 1269 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1270