1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef SUPERIO_ASPEED_COMMON_ROMSTAGE_H 4 #define SUPERIO_ASPEED_COMMON_ROMSTAGE_H 5 6 #include <device/pnp_type.h> 7 #include <stdint.h> 8 9 /* AST2300/2400/2500/2600 use the same memory base */ 10 #define ASPEED_MEM_BASE1 0x1E6E0000 11 #define ASPEED_MMC_BASE (ASPEED_MEM_BASE1) 12 #define ASPEED_USB_BASE (ASPEED_MEM_BASE1 + 0x1000) 13 #define ASPEED_SCU_BASE (ASPEED_MEM_BASE1 + 0x2000) 14 #define ASPEED_HACE_BASE (ASPEED_MEM_BASE1 + 0x3000) 15 #define ASPEED_JTAG_BASE (ASPEED_MEM_BASE1 + 0x4000) 16 #define ASPEED_GFX_BASE (ASPEED_MEM_BASE1 + 0x6000) 17 #define ASPEED_X_DMA_BASE (ASPEED_MEM_BASE1 + 0x7000) 18 #define ASPEED_MCTP_BASE (ASPEED_MEM_BASE1 + 0x8000) 19 #define ASPEED_ADC_BASE (ASPEED_MEM_BASE1 + 0x9000) 20 #define ASPEED_LPC_PLUS_BASE (ASPEED_MEM_BASE1 + 0xC000) 21 #define ASPEED_PCIE_BASE (ASPEED_MEM_BASE1 + 0xD000) 22 #define ASPEED_ESPI_BASE (ASPEED_MEM_BASE1 + 0xE000) 23 #define ASPEED_BAT_BASE (ASPEED_MEM_BASE1 + 0xF000) 24 #define ASPEED_MEM_BASE2 0x1E780000 25 #define ASPEED_GPIO_BASE (ASPEED_MEM_BASE2) 26 #define ASPEED_RTC_BASE (ASPEED_MEM_BASE2 + 0x1000) 27 #define ASPEED_TIMER_BASE (ASPEED_MEM_BASE2 + 0x2000) 28 #define ASPEED_UART1_BASE (ASPEED_MEM_BASE2 + 0x3000) 29 #define ASPEED_UART5_BASE (ASPEED_MEM_BASE2 + 0x4000) 30 #define ASPEED_WDT_BASE (ASPEED_MEM_BASE2 + 0x5000) 31 #define ASPEED_PWM_FAN_BASE (ASPEED_MEM_BASE2 + 0x6000) 32 #define ASPEED_VUART_BASE (ASPEED_MEM_BASE2 + 0x7000) 33 #define ASPEED_PUART_BASE (ASPEED_MEM_BASE2 + 0x8000) 34 #define ASPEED_LPC_BASE (ASPEED_MEM_BASE2 + 0x9000) 35 #define ASPEED_I2C_BASE (ASPEED_MEM_BASE2 + 0xA000) 36 #define ASPEED_PECI_BASE (ASPEED_MEM_BASE2 + 0xB000) 37 #define ASPEED_APB2PCI_BASE (ASPEED_MEM_BASE2 + 0xC000) 38 #define ASPEED_UART2_BASE (ASPEED_MEM_BASE2 + 0xD000) 39 #define ASPEED_UART3_BASE (ASPEED_MEM_BASE2 + 0xE000) 40 #define ASPEED_UART4_BASE (ASPEED_MEM_BASE2 + 0xF000) 41 42 /* System Control Unit */ 43 #define PRO_KEY_REG 0x00 44 #define PRO_KEY_PASSWORD 0x1688A8A8 45 #define SYS_RESET_CTL_REG 0x04 46 #define CLK_SEL_REG 0x08 47 #define CLK_STOP_CTL_REG 0x0C 48 #define FRQ_CNT_CTL_REG 0x10 49 #define FRQ_CNT_CMP_REG 0x14 50 #define INT_CTL_STS_REG 0x18 51 #define D2_PLL_PARM_REG 0x1C 52 #define M_PLL_PARM_REG 0x20 53 #define H_PLL_PARM_REG 0x24 54 #define D_PLL_PARM_REG 0x28 55 #define MISC_CTL_REG 0x2C 56 #define PCI_CFG_SET_REG1 0x30 57 #define PCI_CFG_SET_REG2 0x34 58 #define PCI_CFG_SET_REG3 0x38 59 #define SYS_RESET_CTL_STS_REG 0x3C 60 #define VGA_FUNC_HANDSHAKE_REG1 0x40 61 #define VGA_FUNC_HANDSHAKE_REG2 0x44 62 #define MAC_CLK_DELAY_SET_REG 0x48 63 #define MISC_2_CTL_REG 0x4C 64 #define VGA_SCRATCH_REG1 0x50 65 #define VGA_SCRATCH_REG2 0x54 66 #define VGA_SCRATCH_REG3 0x58 67 #define VGA_SCRATCH_REG4 0x5C 68 #define VGA_SCRATCH_REG5 0x60 69 #define VGA_SCRATCH_REG6 0x64 70 #define VGA_SCRATCH_REG7 0x68 71 #define VGA_SCRATCH_REG8 0x6C 72 #define HW_STRAP_REG 0x70 73 #define RAN_NUM_GEN_CTL_REG 0x74 74 #define RAN_NUM_GEN_DATA_OUT_REG 0x78 75 #define SILICON_REV_ID_REG 0x7C 76 #define MUL_FUNC_PIN_CTL1_REG 0x80 77 #define UART3_TXD3_EN_BIT 22 78 #define UART3_RXD3_EN_BIT 23 79 #define UART4_TXD4_EN_BIT 30 80 #define UART4_RXD4_EN_BIT 31 81 #define MUL_FUNC_PIN_CTL2_REG 0x84 82 #define UART1_TXD1_EN_BIT 22 83 #define UART1_RXD1_EN_BIT 23 84 #define UART2_TXD2_EN_BIT 30 85 #define UART2_RXD2_EN_BIT 31 86 #define MUL_FUNC_PIN_CTL3_REG 0x88 87 #define MUL_FUNC_PIN_CTL4_REG 0x8C 88 #define MUL_FUNC_PIN_CTL5_REG 0x90 89 #define MUL_FUNC_PIN_CTL6_REG 0x94 90 #define DIGI_VIDEO_OUT_PINS_DIS 0 91 #define DIGI_VIDEO_OUT_PINS_EN 1 92 #define EXTRST_RESET_SEL_REG 0x9C 93 #define MUL_FUNC_PIN_CTL7_REG 0xA0 94 #define MUL_FUNC_PIN_CTL8_REG 0xA4 95 #define MUL_FUNC_PIN_CTL9_REG 0xA8 96 #define MUL_FUNC_PIN_CTL10_REG 0xAC 97 #define MAC_CLK_DELAY_100M_REG 0xB8 98 #define MAC_CLK_DELAY_10M_REG 0xBC 99 #define PWR_SAVE_WAKEUP_EN_REG 0xC0 100 #define PWR_SAVE_WAKEUP_CTL_REG 0xC4 101 #define SYS_RESET_CTL_SET2_REG 0xD4 102 #define CLK_SEL_SET2_REG 0xD8 103 #define CLK_STOP_CTL_SET2_REG 0xDC 104 #define SCU_FREE_RUN_CNT_READ_BACK_REG 0xE0 105 #define SCU_FREE_RUN_CNT_EXT_READ_BACK_REG 0xE4 106 #define CLK_DUTY_MEASURE_CTL_REG 0xE8 107 #define CLK_DUTY_MEASURE_RESULT_REG 0xEC 108 #define CPU2_CTL_REG 0x100 109 #define CPU2_BASE_ADDR_SEG_REG1 0x104 110 #define CPU2_BASE_ADDR_SEG_REG2 0x108 111 #define CPU2_BASE_ADDR_SEG_REG3 0x10C 112 #define CPU2_BASE_ADDR_SEG_REG4 0x110 113 #define CPU2_BASE_ADDR_SEG_REG5 0x114 114 #define CPU2_BASE_ADDR_SEG_REG6 0x118 115 #define CPU2_BASE_ADDR_SEG_REG7 0x11C 116 #define CPU2_BASE_ADDR_SEG_REG8 0x120 117 #define CPU2_BASE_ADDR_SEG_REG9 0x124 118 #define CPU2_CACHE_FUNC_CTL_REG 0x128 119 #define D_PLL_EXT_PARM_REG1 0x130 120 #define D_PLL_EXT_PARM_REG2 0x134 121 #define D_PLL_EXT_PARM_REG3 0x138 122 #define D2_PLL_EXT_PARM_REG1 0x13C 123 #define D2_PLL_EXT_PARM_REG2 0x140 124 #define D2_PLL_EXT_PARM_REG3 0x144 125 #define EXT_PARM_M_H_PLL_REG 0x148 126 #define CHIP_UNIQ_ID_L_REG 0x150 127 #define CHIP_UNIQ_ID_H_REG 0x154 128 #define GEN_UART_24M_H_PLL_REG 0x160 129 #define PCIE_CFG_SET_CTL_REG 0x180 130 #define BMC_MMIO_DECODE_SET_REG 0x184 131 #define FIRST_RELO_CTL_DECODE_AREA_LOCA_REG 0x188 132 #define SECOND_RELO_CTL_DECODE_AREA_LOCA_REG 0x18C 133 #define MAILBOX_DECODE_AREA_LOCA_REG 0x190 134 #define SHARED_SRAM_AREA_DECODE_LOCA_REG1 0x194 135 #define SHARED_SRAM_AREA_DECODE_LOCA_REG2 0x198 136 #define BMC_DEV_CLASS_CODE_REV_ID_REG 0x19C 137 #define BMC_DEV_ID_REG 0x1A4 138 #define CLK_DUTY_SEL_REG 0x1DC 139 140 /* LPC Controller */ 141 #define HICR0_REG 0x00 142 #define HICR1_REG 0x04 143 #define HICR2_REG 0x08 144 #define HICR3_REG 0x0C 145 #define HICR4_REG 0x10 146 #define LADR3H_REG 0x14 147 #define LADR3L_REG 0x18 148 #define LADR12H_REG 0x1C 149 #define LADR12L_REG 0x20 150 #define IDR1_REG 0x24 151 #define IDR2_REG 0x28 152 #define IDR3_REG 0x2C 153 #define ODR1_REG 0x30 154 #define ODR2_REG 0x34 155 #define ODR3_REG 0x38 156 #define STR1_REG 0x3C 157 #define STR2_REG 0x40 158 #define STR3_REG 0x44 159 #define BTR0_REG 0x48 160 #define BRT1_REG 0x4C 161 #define BTCSR0_REG 0x50 162 #define BTCSR1_REG 0x54 163 #define BTCR_REG 0x58 164 #define BTDTR_REG 0x5C 165 #define BTIMSR_REG 0x60 166 #define BTFVSR0_REG 0x64 167 #define BTFVSR1_REG 0x68 168 #define SIRQCR0_REG 0x70 169 #define SIRQCR1_REG 0x74 170 #define SIRQCR2_REG 0x78 171 #define SIRQCR3_REG 0x7C 172 #define HICR5_REG 0x80 173 #define SNOOP_ADDR_EN 0 174 #define HICR6_REG 0x84 175 #define HICR7_REG 0x88 176 #define HICR8_REG 0x8C 177 #define SNPWADR_REG 0x90 178 #define SNOOP_ADDR_PORT80 0x80 179 #define SNPWDR_REG 0x94 180 #define HICR9_REG 0x98 181 #define HICRA_REG 0x9C 182 #define LHCR0_REG 0xA0 183 #define LHCR1_REG 0xA4 184 #define LHCR2_REG 0xA8 185 #define LHCR3_REG 0xAC 186 #define LHCR4_REG 0xB0 187 #define LHCR5_REG 0xB4 188 #define LHCR6_REG 0xB8 189 #define LHCR7_REG 0xBC 190 #define LHCR8_REG 0xC0 191 #define PCCR6_REG 0xC4 192 #define LHCRA_REG 0xC8 193 #define LHCRB_REG 0xCC 194 #define PCCR4_REG 0xD0 195 #define PCCR5_REG 0xD4 196 #define HICRB_REG 0x100 197 #define HICRC_REG 0x104 198 #define HISR0_REG 0x108 199 #define HISR1_REG 0x10C 200 #define LADR4_REG 0x110 201 #define IDR4_REG 0x114 202 #define ODR4_REG 0x118 203 #define STR4_REG 0x11C 204 #define LSADR12_REG 0x120 205 #define IDR5_REG 0x124 206 #define ODR5_REG 0x12C 207 #define PCCR0_REG 0x130 208 #define PCCR1_REG 0x134 209 #define PCCR2_REG 0x138 210 #define PCCR3_REG 0x13C 211 #define IBTCR0_REG 0x140 212 #define IBTCR1_REG 0x144 213 #define IBTCR2_REG 0x148 214 #define IBTCR3_REG 0x14C 215 #define IBTCR4_REG 0x150 216 #define IBTCR5_REG 0x154 217 #define IBTCR6_REG 0x158 218 #define SRUART1_REG 0x160 219 #define SRUART2_REG 0x164 220 #define SRUART3_REG 0x168 221 #define SRUART4_REG 0x16C 222 #define SCR0SIO_REG 0x170 223 #define SCR1SIO_REG 0x174 224 #define SCR2SIO_REG 0x178 225 #define SCR3SIO_REG 0x17C 226 #define SWCR_03_00_REG 0x180 227 #define SWCR_07_04_REG 0x184 228 #define SWCR_0B_08_REG 0x188 229 #define SWCR_0F_0C_REG 0x18C 230 #define SWCR_13_10_REG 0x190 231 #define SWCR_17_14_REG 0x194 232 #define SWCR_1B_18_REG 0x198 233 #define SWCR_1F_1C_REG 0x19C 234 #define ACPI_E3_E0_REG 0x1A0 235 #define ACPI_C1_C0_REG 0x1A4 236 #define ACPI_B3_B0_REG 0x1A8 237 #define ACPI_B7_B4_REG 0x1AC 238 #define MBXDAT_0_REG 0x200 239 #define MBXDAT_1_REG 0x204 240 #define MBXDAT_2_REG 0x208 241 #define MBXDAT_3_REG 0x20C 242 #define MBXDAT_4_REG 0x210 243 #define MBXDAT_5_REG 0x214 244 #define MBXDAT_6_REG 0x218 245 #define MBXDAT_7_REG 0x21C 246 #define MBXDAT_8_REG 0x220 247 #define MBXDAT_9_REG 0x224 248 #define MBXDAT_A_REG 0x228 249 #define MBXDAT_B_REG 0x22C 250 #define MBXDAT_C_REG 0x230 251 #define MBXDAT_D_REG 0x234 252 #define MBXDAT_E_REG 0x238 253 #define MBXDAT_F_REG 0x23C 254 #define MBXSTS_0_REG 0x240 255 #define MBXSTS_1_REG 0x244 256 #define MBXBCR_REG 0x248 257 #define MBXHCR_REG 0x24C 258 #define MBXBIE_0_REG 0x250 259 #define MBXBIE_1_REG 0x254 260 #define MBXHIE_0_REG 0x258 261 #define MBXHIE_1_REG 0x25C 262 263 /* GPIO Controller */ 264 #define A_B_C_D_DATA_VALUE_REG 0x00 265 #define A_B_C_D_DIRECTION_REG 0x04 266 #define A_B_C_D_INT_EN_REG 0x08 267 #define A_B_C_D_INT_SEN_T0_REG 0x0C 268 #define A_B_C_D_INT_SEN_T1_REG 0x10 269 #define A_B_C_D_INT_SEN_T2_REG 0x14 270 #define A_B_C_D_INT_STS_REG 0x18 271 #define A_B_C_D_RESET_TOLE_REG 0x1C 272 #define E_F_G_H_DATA_VALUE_REG 0x20 273 #define E_F_G_H_DIRECTION_REG 0x24 274 #define E_F_G_H_INT_EN_REG 0x28 275 #define E_F_G_H_INT_SEN_T0_REG 0x2C 276 #define E_F_G_H_INT_SEN_T1_REG 0x30 277 #define E_F_G_H_INT_SEN_T2_REG 0x34 278 #define E_F_G_H_INT_STS_REG 0x38 279 #define E_F_G_H_RESET_TOLE_REG 0x3C 280 #define A_B_C_D_DEBOUNCE_SET_REG1 0x40 281 #define A_B_C_D_DEBOUNCE_SET_REG2 0x44 282 #define E_F_G_H_DEBOUNCE_SET_REG1 0x48 283 #define E_F_G_H_DEBOUNCE_SET_REG2 0x4C 284 #define DEBOUNCE_TIMER_SET_REG1 0x50 285 #define DEBOUNCE_TIMER_SET_REG2 0x54 286 #define DEBOUNCE_TIMER_SET_REG3 0x58 287 #define A_B_C_D_CMD_SOURCE0_REG 0x60 288 #define A_B_C_D_CMD_SOURCE1_REG 0x64 289 #define E_F_G_H_CMD_SOURCE0_REG 0x68 290 #define E_F_G_H_CMD_SOURCE1_REG 0x6C 291 #define I_J_K_L_DATA_VALUE_REG 0x70 292 #define I_J_K_L_DIRECTION_REG 0x74 293 #define M_N_O_P_DATA_VALUE_REG 0x78 294 #define M_N_O_P_DIRECTION_REG 0x7C 295 #define Q_R_S_T_DATA_VALUE_REG 0x80 296 #define Q_R_S_T_DIRECTION_REG 0x84 297 #define U_V_W_X_DATA_VALUE_REG 0x88 298 #define U_V_W_X_DIRECTION_REG 0x8C 299 #define I_J_K_L_CMD_SOURCE0_REG 0x90 300 #define I_J_K_L_CMD_SOURCE1_REG 0x94 301 #define I_J_K_L_INT_EN_REG 0x98 302 #define I_J_K_L_INT_SEN_T0_REG 0x9C 303 #define I_J_K_L_INT_SEN_T1_REG 0xA0 304 #define I_J_K_L_INT_SEN_T2_REG 0xA4 305 #define I_J_K_L_INT_STS_REG 0xA8 306 #define I_J_K_L_RESET_TOLE_REG 0xAC 307 #define I_J_K_L_DEBOUNCE_SET_REG1 0xB0 308 #define I_J_K_L_DEBOUNCE_SET_REG2 0xB4 309 #define I_J_K_L_INPUT_MASK 0xB8 310 #define A_B_C_D_DATA_READ_REG 0xC0 311 #define E_F_G_H_DATA_READ_REG 0xC4 312 #define I_J_K_L_DATA_READ_REG 0xC8 313 #define M_N_O_P_DATA_READ_REG 0xCC 314 #define Q_R_S_T_DATA_READ_REG 0xD0 315 #define U_V_W_X_DATA_READ_REG 0xD4 316 #define Y_Z_AA_AB_DATA_READ_REG 0xD8 317 #define AC_DATA_READ_REG 0xDC 318 #define M_N_O_P_CMD_SOURCE0_REG 0xE0 319 #define M_N_O_P_CMD_SOURCE1_REG 0xE4 320 #define M_N_O_P_INT_EN_REG 0xE8 321 #define M_N_O_P_INT_SEN_T0_REG 0xEC 322 #define M_N_O_P_INT_SEN_T1_REG 0xF0 323 #define M_N_O_P_INT_SEN_T2_REG 0xF4 324 #define M_N_O_P_INT_STS_REG 0xF8 325 #define M_N_O_P_RESET_TOLE_REG 0xFC 326 #define M_N_O_P_DEBOUNCE_SET_REG1 0x100 327 #define M_N_O_P_DEBOUNCE_SET_REG2 0x104 328 #define M_N_O_P_INPUT_MASK 0x108 329 #define Q_R_S_T_CMD_SOURCE0_REG 0x110 330 #define Q_R_S_T_CMD_SOURCE1_REG 0x114 331 #define Q_R_S_T_INT_EN_REG 0x118 332 #define Q_R_S_T_INT_SEN_T0_REG 0x11C 333 #define Q_R_S_T_INT_SEN_T1_REG 0x120 334 #define Q_R_S_T_INT_SEN_T2_REG 0x124 335 #define Q_R_S_T_INT_STS_REG 0x128 336 #define Q_R_S_T_RESET_TOLE_REG 0x12C 337 #define Q_R_S_T_DEBOUNCE_SET_REG1 0x130 338 #define Q_R_S_T_DEBOUNCE_SET_REG2 0x134 339 #define Q_R_S_T_INPUT_MASK 0x138 340 #define U_V_W_X_CMD_SOURCE0_REG 0x140 341 #define U_V_W_X_CMD_SOURCE1_REG 0x144 342 #define U_V_W_X_INT_EN_REG 0x148 343 #define U_V_W_X_INT_SEN_T0_REG 0x14C 344 #define U_V_W_X_INT_SEN_T1_REG 0x150 345 #define U_V_W_X_INT_SEN_T2_REG 0x154 346 #define U_V_W_X_INT_STS_REG 0x158 347 #define U_V_W_X_RESET_TOLE_REG 0x15C 348 #define U_V_W_X_DEBOUNCE_SET_REG1 0x160 349 #define U_V_W_X_DEBOUNCE_SET_REG2 0x164 350 #define U_V_W_X_INPUT_MASK 0x168 351 #define Y_Z_AA_AB_CMD_SOURCE0_REG 0x170 352 #define Y_Z_AA_AB_CMD_SOURCE1_REG 0x174 353 #define Y_Z_AA_AB_INT_EN_REG 0x178 354 #define Y_Z_AA_AB_INT_SEN_T0_REG 0x17C 355 #define Y_Z_AA_AB_INT_SEN_T1_REG 0x180 356 #define Y_Z_AA_AB_INT_SEN_T2_REG 0x184 357 #define Y_Z_AA_AB_INT_STS_REG 0x188 358 #define Y_Z_AA_AB_RESET_TOLE_REG 0x18C 359 #define Y_Z_AA_AB_DEBOUNCE_SET_REG1 0x190 360 #define Y_Z_AA_AB_DEBOUNCE_SET_REG2 0x194 361 #define Y_Z_AA_AB_INPUT_MASK 0x198 362 #define AC_CMD_SOURCE0_REG 0x1A0 363 #define AC_CMD_SOURCE1_REG 0x1A4 364 #define AC_INT_EN_REG 0x1A8 365 #define AC_INT_SEN_T0_REG 0x1AC 366 #define AC_INT_SEN_T1_REG 0x1B0 367 #define AC_INT_SEN_T2_REG 0x1B4 368 #define AC_INT_STS_REG 0x1B8 369 #define AC_RESET_TOLE_REG 0x1BC 370 #define AC_DEBOUNCE_SET_REG1 0x1C0 371 #define AC_DEBOUNCE_SET_REG2 0x1C4 372 #define AC_INPUT_MASK 0x1C8 373 #define A_B_C_D_INPUT_MASK 0x1D0 374 #define E_F_G_H_INPUT_MASK 0x1D4 375 #define Y_Z_AA_AB_DATA_VALUE_REG 0x1E0 376 #define Y_Z_AA_AB_DIRECTION_REG 0x1E4 377 #define AC_DATA_VALUE_REG 0x1E8 378 #define AC_DIRECTION_REG 0x1EC 379 380 /* SuperIO Controller */ 381 #define LDN_ILPC2AHB 0xD 382 #define LDN_SUART1 0x02 383 #define LDN_SUART2 0x03 384 #define LDN_SUART3 0x0B 385 #define LDN_SUART4 0x0C 386 #define LDN_SEL_REG 0x07 387 #define ACT_REG 0x30 388 #define ACTIVATE_VALUE 0x01 389 #define DEACTIVATE_VALUE 0x00 390 #define PORT80_GPIO_EN 0x80 391 #define PORT80_GPIO_SEL_REG 0x38 392 #define INV_GPIO_EN 0x80 393 #define LPC2AHB_ADD0_REG 0xF0 394 #define LPC2AHB_ADD1_REG 0xF1 395 #define LPC2AHB_ADD2_REG 0xF2 396 #define LPC2AHB_ADD3_REG 0xF3 397 #define LPC2AHB_DAT0_REG 0xF4 398 #define LPC2AHB_DAT1_REG 0xF5 399 #define LPC2AHB_DAT2_REG 0xF6 400 #define LPC2AHB_DAT3_REG 0xF7 401 #define LPC2AHB_LEN_REG 0xF8 402 #define LPC2AHB_1_BYTE 0x00 403 #define LPC2AHB_2_BYTE 0x01 404 #define LPC2AHB_4_BYTE 0x02 405 #define LPC2AHB_RW_REG 0xFE 406 407 #define ASPEED_ENTRY_KEY 0xA5 408 #define ASPEED_EXIT_KEY 0xAA 409 410 #define TO_BE_UPDATE 0 411 #define AndMask32(HighBit, LowBit) ~((((uint32_t)1 << (HighBit - LowBit + 1)) - 1) << LowBit) 412 413 typedef enum { 414 GPIOA = 0, 415 GPIOB, 416 GPIOC, 417 GPIOD, 418 GPIOE, 419 GPIOF, 420 GPIOG, 421 GPIOH, 422 GPIOI, 423 GPIOJ, 424 GPIOK, 425 GPIOL, 426 GPIOM, 427 GPION, 428 GPIOO, 429 GPIOP, 430 GPIOQ, 431 GPIOR, 432 GPIOS, 433 GPIOT, 434 GPIOU, 435 GPIOV, 436 GPIOW, 437 GPIOX, 438 GPIOY, 439 GPIOZ, 440 GPIOAA, 441 GPIOAB, 442 } gpio_group_sel; 443 444 enum { 445 Step1 = 0, 446 Step2, 447 Step3, 448 Step4, 449 Step5, 450 Step6, 451 Step7, 452 Step8, 453 Step9, 454 Step10, 455 Step11, 456 Step12, 457 Step13, 458 Step14, 459 Step15, 460 Step16, 461 Step17, 462 Step18, 463 Step19, 464 Step20, 465 }; 466 467 enum { 468 ARM = 0, 469 LPC, 470 CoprocessorCPU, 471 Reserved, 472 }; 473 474 typedef enum { 475 SIO = 0, 476 MEM, 477 NOP, 478 } config_type; 479 480 typedef struct config_data { 481 config_type type; 482 uint32_t base; 483 uint16_t reg; 484 uint32_t and; 485 uint32_t or; 486 } config_data; 487 488 void aspeed_enable_serial(pnp_devfn_t dev, uint16_t iobase); 489 void aspeed_early_config(pnp_devfn_t dev, config_data *table, uint8_t count); 490 491 /* Enable SuperIO feature which is described in ASPEED datasheet */ 492 void aspeed_enable_port80_direct_gpio(pnp_devfn_t dev, gpio_group_sel g); 493 494 /* Enable UART multi-function pins which is described in ASPEED datasheet */ 495 void aspeed_enable_uart_pin(pnp_devfn_t dev); 496 497 void pnp_enter_conf_state(pnp_devfn_t dev); 498 void pnp_exit_conf_state(pnp_devfn_t dev); 499 void lpc_read(uint8_t port, uint32_t addr, uint32_t *value); 500 void lpc_write(uint8_t port, uint32_t addr, uint32_t data); 501 502 #endif /* SUPERIO_ASPEED_COMMON_ROMSTAGE_H */ 503