1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Authors: Dave Airlie <[email protected]>
4 */
5 #ifndef __AST_DRV_H__
6 #define __AST_DRV_H__
7
8 #include "aspeed_coreboot.h"
9
10 #define PCI_CHIP_AST2000 0x2000
11 #define PCI_CHIP_AST2100 0x2010
12 #define PCI_CHIP_AST1180 0x1180
13
14 enum ast_chip {
15 AST2000,
16 AST2100,
17 AST1100,
18 AST2200,
19 AST2150,
20 AST2300,
21 AST2400,
22 AST2500,
23 AST1180,
24 };
25
26 enum ast_tx_chip {
27 AST_TX_NONE,
28 AST_TX_SIL164,
29 AST_TX_ITE66121,
30 AST_TX_DP501,
31 };
32
33 #define AST_DRAM_512Mx16 0
34 #define AST_DRAM_1Gx16 1
35 #define AST_DRAM_512Mx32 2
36 #define AST_DRAM_1Gx32 3
37 #define AST_DRAM_2Gx16 6
38 #define AST_DRAM_4Gx16 7
39 #define AST_DRAM_8Gx16 8
40
41 struct ast_fbdev;
42
43 struct ast_private {
44 struct drm_device *dev;
45
46 void __iomem *regs;
47 void __iomem *ioregs;
48 bool io_space_uses_mmap;
49
50 enum ast_chip chip;
51 bool vga2_clone;
52 uint32_t dram_bus_width;
53 uint32_t dram_type;
54 uint32_t mclk;
55 uint32_t vram_size;
56
57 struct ast_fbdev *fbdev;
58
59 int fb_mtrr;
60
61 struct drm_gem_object *cursor_cache;
62 uint64_t cursor_cache_gpu_addr;
63
64 int next_cursor;
65 bool support_wide_screen;
66 enum {
67 ast_use_p2a,
68 ast_use_dt,
69 ast_use_defaults
70 } config_mode;
71
72 enum ast_tx_chip tx_chip_type;
73 u8 dp501_maxclk;
74 u8 *dp501_fw_addr;
75 const struct firmware *dp501_fw; /* dp501 fw */
76 };
77
78 int ast_driver_load(struct drm_device *dev, unsigned long flags);
79 int ast_driver_unload(struct drm_device *dev);
80
81 #define AST_IO_AR_PORT_WRITE (0x40)
82 #define AST_IO_MISC_PORT_WRITE (0x42)
83 #define AST_IO_VGA_ENABLE_PORT (0x43)
84 #define AST_IO_SEQ_PORT (0x44)
85 #define AST_IO_DAC_INDEX_READ (0x47)
86 #define AST_IO_DAC_INDEX_WRITE (0x48)
87 #define AST_IO_DAC_DATA (0x49)
88 #define AST_IO_GR_PORT (0x4E)
89 #define AST_IO_CRTC_PORT (0x54)
90 #define AST_IO_INPUT_STATUS1_READ (0x5A)
91 #define AST_IO_MISC_PORT_READ (0x4C)
92
93 #define AST_IO_MM_OFFSET (0x380)
94
95 #define __ast_read(x) \
96 static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \
97 u##x val = 0;\
98 val = ioread##x(ast->regs + reg); \
99 return val;\
100 }
101
102 __ast_read(8);
103 __ast_read(16);
104 __ast_read(32)
105
106 #define __ast_io_read(x) \
107 static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \
108 u##x val = 0;\
109 if (ast->io_space_uses_mmap) \
110 val = ioread##x(ast->regs + reg); \
111 else \
112 val = ioread_cbio##x(ast->ioregs + reg); \
113 return val;\
114 }
115
116 __ast_io_read(8);
117 __ast_io_read(16);
118 __ast_io_read(32);
119
120 #define __ast_write(x) \
121 static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\
122 iowrite##x(val, ast->regs + reg);\
123 }
124
125 __ast_write(8);
126 __ast_write(16);
127 __ast_write(32);
128
129 #define __ast_io_write(x) \
130 static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\
131 if (ast->io_space_uses_mmap) \
132 iowrite##x(val, ast->regs + reg);\
133 else \
134 iowrite_cbio##x(val, ast->ioregs + reg);\
135 }
136
137 __ast_io_write(8);
138 __ast_io_write(16);
139 #undef __ast_io_write
140
ast_set_index_reg(struct ast_private * ast,uint32_t base,uint8_t index,uint8_t val)141 static inline void ast_set_index_reg(struct ast_private *ast,
142 uint32_t base, uint8_t index,
143 uint8_t val)
144 {
145 ast_io_write16(ast, base, ((u16)val << 8) | index);
146 }
147
148 void ast_set_index_reg_mask(struct ast_private *ast,
149 uint32_t base, uint8_t index,
150 uint8_t mask, uint8_t val);
151 uint8_t ast_get_index_reg(struct ast_private *ast,
152 uint32_t base, uint8_t index);
153 uint8_t ast_get_index_reg_mask(struct ast_private *ast,
154 uint32_t base, uint8_t index, uint8_t mask);
155
ast_open_key(struct ast_private * ast)156 static inline void ast_open_key(struct ast_private *ast)
157 {
158 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8);
159 }
160
161 #define AST_VIDMEM_SIZE_8M 0x00800000
162 #define AST_VIDMEM_SIZE_16M 0x01000000
163 #define AST_VIDMEM_SIZE_32M 0x02000000
164 #define AST_VIDMEM_SIZE_64M 0x04000000
165 #define AST_VIDMEM_SIZE_128M 0x08000000
166
167 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M
168
169 #define AST_MAX_HWC_WIDTH 64
170 #define AST_MAX_HWC_HEIGHT 64
171
172 #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH*AST_MAX_HWC_HEIGHT*2)
173 #define AST_HWC_SIGNATURE_SIZE 32
174
175 #define EINVAL 22 /* Invalid argument */
176
177 #define AST_DEFAULT_HWC_NUM 2
178 /* define for signature structure */
179 #define AST_HWC_SIGNATURE_CHECKSUM 0x00
180 #define AST_HWC_SIGNATURE_SizeX 0x04
181 #define AST_HWC_SIGNATURE_SizeY 0x08
182 #define AST_HWC_SIGNATURE_X 0x0C
183 #define AST_HWC_SIGNATURE_Y 0x10
184 #define AST_HWC_SIGNATURE_HOTSPOTX 0x14
185 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18
186
187 /* ast_mode.c stuff */
188 struct ast_vbios_stdtable {
189 u8 misc;
190 u8 seq[4];
191 u8 crtc[25];
192 u8 ar[20];
193 u8 gr[9];
194 };
195
196 struct ast_vbios_enhtable {
197 u32 ht;
198 u32 hde;
199 u32 hfp;
200 u32 hsync;
201 u32 vt;
202 u32 vde;
203 u32 vfp;
204 u32 vsync;
205 u32 dclk_index;
206 u32 flags;
207 u32 refresh_rate;
208 u32 refresh_rate_index;
209 u32 mode_id;
210 };
211
212 struct ast_vbios_dclk_info {
213 u8 param1;
214 u8 param2;
215 u8 param3;
216 };
217
218 struct ast_vbios_mode_info {
219 const struct ast_vbios_stdtable *std_table;
220 const struct ast_vbios_enhtable *enh_table;
221 };
222
223 #define DRM_MODE_FLAG_NVSYNC 1
224 #define DRM_MODE_FLAG_PVSYNC 2
225 #define DRM_MODE_FLAG_NHSYNC 4
226 #define DRM_MODE_FLAG_PHSYNC 8
227
228 struct drm_display_mode {
229 /* Proposed mode values */
230 u16 vrefresh; /* in Hz */
231 u32 clock;
232 u16 hdisplay;
233 u16 vdisplay;
234 u32 flags;
235
236 /* Actual mode we give to hw */
237 u16 crtc_hdisplay;
238 u16 crtc_htotal;
239 u16 crtc_hblank_start;
240 u16 crtc_hblank_end;
241 u16 crtc_hsync_start;
242 u16 crtc_hsync_end;
243 u16 crtc_vtotal;
244 u16 crtc_vsync_start;
245 u16 crtc_vsync_end;
246 u16 crtc_vdisplay;
247 u16 crtc_vblank_start;
248 u16 crtc_vblank_end;
249 };
250
251 struct drm_format {
252 u32 cpp[1]; /* Colors per pixel */
253 };
254
255 struct drm_framebuffer {
256 u32 pitches[1];
257 struct drm_format *format;
258 u32 mmio_addr;
259 };
260
261 struct drm_primary {
262 struct drm_framebuffer *fb;
263 };
264
265 struct drm_crtc {
266 struct drm_device *dev;
267 struct drm_primary *primary;
268 struct drm_display_mode mode;
269 };
270
271 struct drm_connector {
272 struct drm_device *dev;
273 };
274
275 enum drm_mode_status {
276 MODE_NOMODE,
277 MODE_OK
278 };
279
280 #define AST_MM_ALIGN_SHIFT 4
281 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
282
283 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
284
285 /* ast post */
286 void ast_enable_vga(struct drm_device *dev);
287 void ast_enable_mmio(struct drm_device *dev);
288 bool ast_is_vga_enabled(struct drm_device *dev);
289 void ast_post_gpu(struct drm_device *dev);
290 u32 ast_mindwm(struct ast_private *ast, u32 r);
291 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
292 /* ast dp501 */
293 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
294 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
295 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
296 u8 ast_get_dp501_max_clk(struct drm_device *dev);
297 void ast_init_3rdtx(struct drm_device *dev);
298 void ast_release_firmware(struct drm_device *dev);
299
300 /* ast mode */
301 int ast_crtc_mode_set(struct drm_crtc *crtc,
302 struct drm_display_mode *mode,
303 struct drm_display_mode *adjusted_mode);
304 enum drm_mode_status ast_mode_valid(struct drm_connector *connector,
305 const unsigned int hdisplay,
306 const unsigned int vdisplay);
307 void ast_hide_cursor(struct drm_crtc *crtc);
308 void ast_set_offset_reg(struct drm_crtc *crtc);
309 void ast_set_start_address_crt1(struct ast_private *ast, u32 offset);
310
311 /* ast_mode_corebootfb */
312 int ast_driver_framebuffer_init(struct drm_device *dev, int flags);
313 int ast_crtc_do_set_base(struct drm_crtc *crtc);
314
315 /* ast i2c */
316 int ast_software_i2c_read(struct ast_private *ast_priv, uint8_t edid[128]);
317
318 #endif
319