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3 Copyright (c) 2017-2023, Intel Corporation
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24 //!
25 //! \file mhw_vdbox_hcp_g12_X.cpp
26 //! \brief Constructs VdBox HCP commands on Gen12-based platforms
27
28 #include "mhw_vdbox_hcp_g12_X.h"
29 #include "mhw_mi_hwcmd_g12_X.h"
30 #include "mhw_vdbox_vdenc_hwcmd_g12_X.h"
31 #include "mhw_sfc_hwcmd_g12_X.h"
32 #include "mhw_vdbox_g12_X.h"
33 #include "mhw_mmio_g12.h"
34 #include "mhw_sfc_g12_X.h"
35 #include "mos_interface.h"
36 #include "hal_oca_interface.h"
37
38 static uint16_t RDOQLamdas8bits[2][2][2][52] = //[Intra Slice/Inter Slice][Intra/Inter][Luma/Chroma][QP]
39 {
40 {
41 {
42 { //Intra Luma
43 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0001, 0x0001,
44 0x0001, 0x0001, 0x0002, 0x0002, 0x0003, 0x0003, 0x0004, 0x0005,
45 0x0007, 0x0008, 0x000a, 0x000d, 0x0011, 0x0015, 0x001a, 0x0021,
46 0x002a, 0x0034, 0x0042, 0x0053, 0x0069, 0x0084, 0x00a6, 0x00d2,
47 0x0108, 0x014d, 0x01a3, 0x0210, 0x029a, 0x0347, 0x0421, 0x0533,
48 0x068d, 0x0841, 0x0a66, 0x0d1a, 0x1082, 0x14cd, 0x1a35, 0x2105,
49 0x299a, 0x346a, 0x4209, 0x5333
50 },
51 { //Intra Chroma
52 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0001, 0x0001,
53 0x0001, 0x0001, 0x0002, 0x0002, 0x0003, 0x0003, 0x0004, 0x0005,
54 0x0007, 0x0008, 0x000a, 0x000d, 0x0011, 0x0015, 0x001a, 0x0021,
55 0x002a, 0x0034, 0x0042, 0x0053, 0x0069, 0x0084, 0x00a6, 0x00d2,
56 0x0108, 0x014d, 0x01a3, 0x0210, 0x029a, 0x0347, 0x0421, 0x0533,
57 0x068d, 0x0841, 0x0a66, 0x0d1a, 0x1082, 0x14cd, 0x1a35, 0x2105,
58 0x299a, 0x346a, 0x4209, 0x5333
59 },
60 },
61 {
62 { //Inter Luma
63 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002, 0x0002, 0x0003,
64 0x0003, 0x0004, 0x0006, 0x0007, 0x0009, 0x000b, 0x000e, 0x0012,
65 0x0016, 0x001c, 0x0023, 0x002c, 0x0038, 0x0046, 0x0059, 0x0075,
66 0x009b, 0x00cc, 0x010c, 0x0160, 0x01cd, 0x025b, 0x0314, 0x0405,
67 0x053d, 0x06d2, 0x08df, 0x0b2d, 0x0e14, 0x11bd, 0x165a, 0x1c29,
68 0x237b, 0x2cb4, 0x3852, 0x46f5, 0x5967, 0x70a4, 0x8deb, 0xb2ce,
69 0xe148, 0xffff, 0xffff, 0xffff
70 },
71 { //Inter Chroma
72 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002, 0x0002, 0x0003,
73 0x0003, 0x0004, 0x0005, 0x0007, 0x0008, 0x000b, 0x000d, 0x0011,
74 0x0015, 0x001b, 0x0021, 0x002a, 0x0035, 0x0043, 0x0054, 0x006c,
75 0x008c, 0x00b4, 0x00e7, 0x0129, 0x017d, 0x01ea, 0x0275, 0x0327,
76 0x040c, 0x0530, 0x06a7, 0x0862, 0x0a8f, 0x0d4e, 0x10c3, 0x151f,
77 0x1a9c, 0x2187, 0x2a3d, 0x3538, 0x430d, 0x547b, 0x6a70, 0x861b,
78 0xa8f6, 0xd4e0, 0xffff, 0xffff
79 },
80 },
81 },
82 {
83 {
84 { //Intra Luma
85 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002, 0x0002, 0x0003,
86 0x0003, 0x0004, 0x0006, 0x0007, 0x0009, 0x000b, 0x000e, 0x0012,
87 0x0016, 0x001c, 0x0023, 0x002c, 0x0038, 0x0046, 0x0059, 0x0075,
88 0x009b, 0x00cc, 0x010c, 0x0160, 0x01cd, 0x025b, 0x0314, 0x0405,
89 0x053d, 0x06d2, 0x08df, 0x0b2d, 0x0e14, 0x11bd, 0x165a, 0x1c29,
90 0x237b, 0x2cb4, 0x3852, 0x46f5, 0x5967, 0x70a4, 0x8deb, 0xb2ce,
91 0xe148, 0xffff, 0xffff, 0xffff
92 },
93 { //Intra Chroma
94 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002, 0x0002, 0x0003,
95 0x0003, 0x0004, 0x0005, 0x0007, 0x0008, 0x000b, 0x000d, 0x0011,
96 0x0015, 0x001b, 0x0021, 0x002a, 0x0035, 0x0043, 0x0054, 0x006c,
97 0x008c, 0x00b4, 0x00e7, 0x0129, 0x017d, 0x01ea, 0x0275, 0x0327,
98 0x040c, 0x0530, 0x06a7, 0x0862, 0x0a8f, 0x0d4e, 0x10c3, 0x151f,
99 0x1a9c, 0x2187, 0x2a3d, 0x3538, 0x430d, 0x547b, 0x6a70, 0x861b,
100 0xa8f6, 0xd4e0, 0xffff, 0xffff
101 },
102 },
103 {
104 { //Inter Luma
105 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002, 0x0002, 0x0003,
106 0x0003, 0x0004, 0x0006, 0x0007, 0x0009, 0x000b, 0x000e, 0x0012,
107 0x0016, 0x001c, 0x0023, 0x002c, 0x0038, 0x0046, 0x0059, 0x0075,
108 0x009b, 0x00cc, 0x010c, 0x0160, 0x01cd, 0x025b, 0x0314, 0x0405,
109 0x053d, 0x06d2, 0x08df, 0x0b2d, 0x0e14, 0x11bd, 0x165a, 0x1c29,
110 0x237b, 0x2cb4, 0x3852, 0x46f5, 0x5967, 0x70a4, 0x8deb, 0xb2ce,
111 0xe148, 0xffff, 0xffff, 0xffff
112 },
113 { //Inter Chroma
114 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002, 0x0002, 0x0003,
115 0x0003, 0x0004, 0x0005, 0x0007, 0x0008, 0x000b, 0x000d, 0x0011,
116 0x0015, 0x001b, 0x0021, 0x002a, 0x0035, 0x0043, 0x0054, 0x006c,
117 0x008c, 0x00b4, 0x00e7, 0x0129, 0x017d, 0x01ea, 0x0275, 0x0327,
118 0x040c, 0x0530, 0x06a7, 0x0862, 0x0a8f, 0x0d4e, 0x10c3, 0x151f,
119 0x1a9c, 0x2187, 0x2a3d, 0x3538, 0x430d, 0x547b, 0x6a70, 0x861b,
120 0xa8f6, 0xd4e0, 0xffff, 0xffff
121 },
122 },
123 }
124 };
125
126 static uint16_t RDOQLamdas10bits[2][2][2][64] = //[Intra Slice/Inter Slice][Intra/Inter][Luma/Chroma][QP]
127 {
128 {
129 {
130 { //Intra Luma
131 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
132 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
133 0x0000, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002, 0x0002,
134 0x0003, 0x0003, 0x0004, 0x0005, 0x0007, 0x0008, 0x000a, 0x000d,
135 0x0011, 0x0015, 0x001a, 0x0021, 0x002a, 0x0034, 0x0042, 0x0053,
136 0x0069, 0x0084, 0x00a6, 0x00d2, 0x0108, 0x014d, 0x01a3, 0x0210,
137 0x029a, 0x0347, 0x0421, 0x0533, 0x068d, 0x0841, 0x0a66, 0x0d1a,
138 0x1082, 0x14cd, 0x1a35, 0x2105, 0x299a, 0x346a, 0x4209, 0x5333
139 },
140 { //Intra Chroma
141 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
142 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
143 0x0000, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002, 0x0002,
144 0x0003, 0x0003, 0x0004, 0x0005, 0x0007, 0x0008, 0x000a, 0x000d,
145 0x0011, 0x0015, 0x001a, 0x0021, 0x002a, 0x0034, 0x0042, 0x0053,
146 0x0069, 0x0084, 0x00a6, 0x00d2, 0x0108, 0x014d, 0x01a3, 0x0210,
147 0x029a, 0x0347, 0x0421, 0x0533, 0x068d, 0x0841, 0x0a66, 0x0d1a,
148 0x1082, 0x14cd, 0x1a35, 0x2105, 0x299a, 0x346a, 0x4209, 0x5333
149 },
150 },
151 {
152 { //Inter Luma
153 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
154 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0001, 0x0001, 0x0001,
155 0x0001, 0x0002, 0x0002, 0x0003, 0x0003, 0x0004, 0x0006, 0x0007,
156 0x0009, 0x000b, 0x000e, 0x0012, 0x0016, 0x001c, 0x0023, 0x002c,
157 0x0038, 0x0046, 0x0059, 0x0075, 0x009b, 0x00cc, 0x010c, 0x0160,
158 0x01cd, 0x025b, 0x0314, 0x0405, 0x053d, 0x06d2, 0x08df, 0x0b2d,
159 0x0e14, 0x11bd, 0x165a, 0x1c29, 0x237b, 0x2cb4, 0x3852, 0x46f5,
160 0x5967, 0x70a4, 0x8deb, 0xb2ce, 0xe148, 0xffff, 0xffff, 0xffff
161 },
162 { //Inter Chroma
163 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
164 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0001, 0x0001, 0x0001,
165 0x0001, 0x0002, 0x0002, 0x0003, 0x0003, 0x0004, 0x0005, 0x0007,
166 0x0008, 0x000b, 0x000d, 0x0011, 0x0015, 0x001b, 0x0021, 0x002a,
167 0x0035, 0x0043, 0x0054, 0x006c, 0x008c, 0x00b4, 0x00e7, 0x0129,
168 0x017d, 0x01ea, 0x0275, 0x0327, 0x040c, 0x0530, 0x06a7, 0x0862,
169 0x0a8f, 0x0d4e, 0x10c3, 0x151f, 0x1a9c, 0x2187, 0x2a3d, 0x3538,
170 0x430d, 0x547b, 0x6a70, 0x861b, 0xa8f6, 0xd4e0, 0xffff, 0xffff
171 },
172 },
173 },
174 {
175 {
176 { //Intra Luma
177 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
178 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0001, 0x0001, 0x0001,
179 0x0001, 0x0002, 0x0002, 0x0003, 0x0003, 0x0004, 0x0006, 0x0007,
180 0x0009, 0x000b, 0x000e, 0x0012, 0x0016, 0x001c, 0x0023, 0x002c,
181 0x0038, 0x0046, 0x0059, 0x0075, 0x009b, 0x00cc, 0x010c, 0x0160,
182 0x01cd, 0x025b, 0x0314, 0x0405, 0x053d, 0x06d2, 0x08df, 0x0b2d,
183 0x0e14, 0x11bd, 0x165a, 0x1c29, 0x237b, 0x2cb4, 0x3852, 0x46f5,
184 0x5967, 0x70a4, 0x8deb, 0xb2ce, 0xe148, 0xffff, 0xffff, 0xffff
185 },
186 { //Intra Chroma
187 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
188 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0001, 0x0001, 0x0001,
189 0x0001, 0x0002, 0x0002, 0x0003, 0x0003, 0x0004, 0x0005, 0x0007,
190 0x0008, 0x000b, 0x000d, 0x0011, 0x0015, 0x001b, 0x0021, 0x002a,
191 0x0035, 0x0043, 0x0054, 0x006c, 0x008c, 0x00b4, 0x00e7, 0x0129,
192 0x017d, 0x01ea, 0x0275, 0x0327, 0x040c, 0x0530, 0x06a7, 0x0862,
193 0x0a8f, 0x0d4e, 0x10c3, 0x151f, 0x1a9c, 0x2187, 0x2a3d, 0x3538,
194 0x430d, 0x547b, 0x6a70, 0x861b, 0xa8f6, 0xd4e0, 0xffff, 0xffff
195 },
196 },
197 {
198 { //Inter Luma
199 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
200 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0001, 0x0001, 0x0001,
201 0x0001, 0x0002, 0x0002, 0x0003, 0x0003, 0x0004, 0x0006, 0x0007,
202 0x0009, 0x000b, 0x000e, 0x0012, 0x0016, 0x001c, 0x0023, 0x002c,
203 0x0038, 0x0046, 0x0059, 0x0075, 0x009b, 0x00cc, 0x010c, 0x0160,
204 0x01cd, 0x025b, 0x0314, 0x0405, 0x053d, 0x06d2, 0x08df, 0x0b2d,
205 0x0e14, 0x11bd, 0x165a, 0x1c29, 0x237b, 0x2cb4, 0x3852, 0x46f5,
206 0x5967, 0x70a4, 0x8deb, 0xb2ce, 0xe148, 0xffff, 0xffff, 0xffff
207 },
208 { //Inter Chroma
209 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
210 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0001, 0x0001, 0x0001,
211 0x0001, 0x0002, 0x0002, 0x0003, 0x0003, 0x0004, 0x0005, 0x0007,
212 0x0008, 0x000b, 0x000d, 0x0011, 0x0015, 0x001b, 0x0021, 0x002a,
213 0x0035, 0x0043, 0x0054, 0x006c, 0x008c, 0x00b4, 0x00e7, 0x0129,
214 0x017d, 0x01ea, 0x0275, 0x0327, 0x040c, 0x0530, 0x06a7, 0x0862,
215 0x0a8f, 0x0d4e, 0x10c3, 0x151f, 0x1a9c, 0x2187, 0x2a3d, 0x3538,
216 0x430d, 0x547b, 0x6a70, 0x861b, 0xa8f6, 0xd4e0, 0xffff, 0xffff
217 },
218 },
219 }
220 };
221
222 static uint16_t RDOQLamdas12bits[2][2][2][76] = //[Intra Slice/Inter Slice][Intra/Inter][Luma/Chroma][QP]
223 {
224 {
225 {
226 { //Intra Luma
227 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
228 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
229 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
230 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0001, 0x0001,
231 0x0001, 0x0001, 0x0002, 0x0002, 0x0003, 0x0003, 0x0004, 0x0005,
232 0x0007, 0x0008, 0x000a, 0x000d, 0x0011, 0x0015, 0x001a, 0x0021,
233 0x002a, 0x0034, 0x0042, 0x0053, 0x0069, 0x0084, 0x00a6, 0x00d2,
234 0x0108, 0x014d, 0x01a3, 0x0210, 0x029a, 0x0347, 0x0421, 0x0533,
235 0x068d, 0x0841, 0x0a66, 0x0d1a, 0x1082, 0x14cd, 0x1a35, 0x2105,
236 0x299a, 0x346a, 0x4209, 0x5333
237 },
238 { //Intra Chroma
239 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
240 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
241 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
242 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0001, 0x0001,
243 0x0001, 0x0001, 0x0002, 0x0002, 0x0003, 0x0003, 0x0004, 0x0005,
244 0x0007, 0x0008, 0x000a, 0x000d, 0x0011, 0x0015, 0x001a, 0x0021,
245 0x002a, 0x0034, 0x0042, 0x0053, 0x0069, 0x0084, 0x00a6, 0x00d2,
246 0x0108, 0x014d, 0x01a3, 0x0210, 0x029a, 0x0347, 0x0421, 0x0533,
247 0x068d, 0x0841, 0x0a66, 0x0d1a, 0x1082, 0x14cd, 0x1a35, 0x2105,
248 0x299a, 0x346a, 0x4209, 0x5333
249 },
250 },
251 {
252 { //Inter Luma
253
254 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
255 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
256 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
257 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002, 0x0002, 0x0003,
258 0x0003, 0x0004, 0x0006, 0x0007, 0x0009, 0x000b, 0x000e, 0x0012,
259 0x0016, 0x001c, 0x0023, 0x002c, 0x0038, 0x0046, 0x0059, 0x0075,
260 0x009b, 0x00cc, 0x010c, 0x0160, 0x01cd, 0x025b, 0x0314, 0x0405,
261 0x053d, 0x06d2, 0x08df, 0x0b2d, 0x0e14, 0x11bd, 0x165a, 0x1c29,
262 0x237b, 0x2cb4, 0x3852, 0x46f5, 0x5967, 0x70a4, 0x8deb, 0xb2ce,
263 0xe148, 0xffff, 0xffff, 0xffff
264 },
265 { //Inter Chroma
266 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
267 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
268 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
269 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002, 0x0002, 0x0003,
270 0x0003, 0x0004, 0x0005, 0x0007, 0x0008, 0x000b, 0x000d, 0x0011,
271 0x0015, 0x001b, 0x0021, 0x002a, 0x0035, 0x0043, 0x0054, 0x006c,
272 0x008c, 0x00b4, 0x00e7, 0x0129, 0x017d, 0x01ea, 0x0275, 0x0327,
273 0x040c, 0x0530, 0x06a7, 0x0862, 0x0a8f, 0x0d4e, 0x10c3, 0x151f,
274 0x1a9c, 0x2187, 0x2a3d, 0x3538, 0x430d, 0x547b, 0x6a70, 0x861b,
275 0xa8f6, 0xd4e0, 0xffff, 0xffff
276 },
277 },
278 },
279 {
280 {
281 { //Intra Luma
282 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
283 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
284 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
285 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002, 0x0002, 0x0003,
286 0x0003, 0x0004, 0x0006, 0x0007, 0x0009, 0x000b, 0x000e, 0x0012,
287 0x0016, 0x001c, 0x0023, 0x002c, 0x0038, 0x0046, 0x0059, 0x0075,
288 0x009b, 0x00cc, 0x010c, 0x0160, 0x01cd, 0x025b, 0x0314, 0x0405,
289 0x053d, 0x06d2, 0x08df, 0x0b2d, 0x0e14, 0x11bd, 0x165a, 0x1c29,
290 0x237b, 0x2cb4, 0x3852, 0x46f5, 0x5967, 0x70a4, 0x8deb, 0xb2ce,
291 0xe148, 0xffff, 0xffff, 0xffff
292 },
293 { //Intra Chroma
294 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
295 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
296 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
297 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002, 0x0002, 0x0003,
298 0x0003, 0x0004, 0x0005, 0x0007, 0x0008, 0x000b, 0x000d, 0x0011,
299 0x0015, 0x001b, 0x0021, 0x002a, 0x0035, 0x0043, 0x0054, 0x006c,
300 0x008c, 0x00b4, 0x00e7, 0x0129, 0x017d, 0x01ea, 0x0275, 0x0327,
301 0x040c, 0x0530, 0x06a7, 0x0862, 0x0a8f, 0x0d4e, 0x10c3, 0x151f,
302 0x1a9c, 0x2187, 0x2a3d, 0x3538, 0x430d, 0x547b, 0x6a70, 0x861b,
303 0xa8f6, 0xd4e0, 0xffff, 0xffff
304 },
305 },
306 {
307 { //Inter Luma
308 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
309 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
310 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
311 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002, 0x0002, 0x0003,
312 0x0003, 0x0004, 0x0006, 0x0007, 0x0009, 0x000b, 0x000e, 0x0012,
313 0x0016, 0x001c, 0x0023, 0x002c, 0x0038, 0x0046, 0x0059, 0x0075,
314 0x009b, 0x00cc, 0x010c, 0x0160, 0x01cd, 0x025b, 0x0314, 0x0405,
315 0x053d, 0x06d2, 0x08df, 0x0b2d, 0x0e14, 0x11bd, 0x165a, 0x1c29,
316 0x237b, 0x2cb4, 0x3852, 0x46f5, 0x5967, 0x70a4, 0x8deb, 0xb2ce,
317 0xe148, 0xffff, 0xffff, 0xffff
318 },
319 { //Inter Chroma
320 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
321 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
322 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
323 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002, 0x0002, 0x0003,
324 0x0003, 0x0004, 0x0005, 0x0007, 0x0008, 0x000b, 0x000d, 0x0011,
325 0x0015, 0x001b, 0x0021, 0x002a, 0x0035, 0x0043, 0x0054, 0x006c,
326 0x008c, 0x00b4, 0x00e7, 0x0129, 0x017d, 0x01ea, 0x0275, 0x0327,
327 0x040c, 0x0530, 0x06a7, 0x0862, 0x0a8f, 0x0d4e, 0x10c3, 0x151f,
328 0x1a9c, 0x2187, 0x2a3d, 0x3538, 0x430d, 0x547b, 0x6a70, 0x861b,
329 0xa8f6, 0xd4e0, 0xffff, 0xffff
330 },
331 },
332 }
333 };
334
~MhwVdboxHcpInterfaceG12()335 MhwVdboxHcpInterfaceG12::~MhwVdboxHcpInterfaceG12()
336 {
337 MHW_FUNCTION_ENTER;
338
339 #if (_DEBUG || _RELEASE_INTERNAL)
340 MOS_USER_FEATURE_VALUE_WRITE_DATA UserFeatureWriteData = __NULL_USER_FEATURE_VALUE_WRITE_DATA__;
341 UserFeatureWriteData.ValueID = __MEDIA_USER_FEATURE_VALUE_IS_CODEC_ROW_STORE_CACHE_ENABLED_ID;
342 if (m_hevcDatRowStoreCache.bEnabled ||
343 m_hevcDfRowStoreCache.bEnabled ||
344 m_hevcSaoRowStoreCache.bEnabled ||
345 m_hevcHSaoRowStoreCache.bEnabled ||
346 m_vp9HvdRowStoreCache.bEnabled ||
347 m_vp9DatRowStoreCache.bEnabled ||
348 m_vp9DfRowStoreCache.bEnabled)
349 {
350 UserFeatureWriteData.Value.i32Data = 1;
351 }
352 MOS_UserFeature_WriteValues_ID(nullptr, &UserFeatureWriteData, 1, m_osInterface->pOsContext);
353 #endif
354
355 }
356
InitMmioRegisters()357 void MhwVdboxHcpInterfaceG12::InitMmioRegisters()
358 {
359 MmioRegistersHcp *mmioRegisters = &m_mmioRegisters[MHW_VDBOX_NODE_1];
360
361 mmioRegisters->watchdogCountCtrlOffset = WATCHDOG_COUNT_CTRL_OFFSET_INIT_G12;
362 mmioRegisters->watchdogCountThresholdOffset = WATCHDOG_COUNT_THRESTHOLD_OFFSET_INIT_G12;
363 mmioRegisters->hcpDebugFEStreamOutSizeRegOffset = HCP_DEBUG_FE_STREAM_OUT_SIZE_REG_OFFSET_INIT_G12;
364 mmioRegisters->hcpEncImageStatusMaskRegOffset = HCP_ENC_IMAGE_STATUS_MASK_REG_OFFSET_INIT_G12;
365 mmioRegisters->hcpEncImageStatusCtrlRegOffset = HCP_ENC_IMAGE_STATUS_CTRL_REG_OFFSET_INIT_G12;
366 mmioRegisters->hcpEncBitstreamBytecountFrameRegOffset = HCP_ENC_BIT_STREAM_BYTE_COUNT_FRAME_REG_OFFSET_INIT_G12;
367 mmioRegisters->hcpEncBitstreamSeBitcountFrameRegOffset = HCP_ENC_BIT_STREAM_SE_BIT_COUNT_FRAME_REG_OFFSET_INIT_G12;
368 mmioRegisters->hcpEncBitstreamBytecountFrameNoHeaderRegOffset = HCP_ENC_BIT_STREAM_BYTE_COUNT_FRAME_NO_HEADER_REG_OFFSET_INIT_G12;
369 mmioRegisters->hcpEncQpStatusCountRegOffset = HCP_ENC_QP_STATUS_COUNT_REG_OFFSET_INIT_G12;
370 mmioRegisters->hcpEncSliceCountRegOffset = HCP_ENC_SLICE_COUNT_REG_OFFSET_INIT_G12;
371 mmioRegisters->hcpEncVdencModeTimerRegOffset = HCP_ENC_VDENC_MODE_TIMER_REG_OFFSET_INIT_G12;
372 mmioRegisters->hcpVp9EncBitstreamBytecountFrameRegOffset = HCP_VP9_ENC_BITSTREAM_BYTE_COUNT_FRAME_REG_OFFSET_INIT_G12;
373 mmioRegisters->hcpVp9EncBitstreamBytecountFrameNoHeaderRegOffset = HCP_VP9_ENC_BITSTREAM_BYTE_COUNT_FRAME_NO_HEADER_REG_OFFSET_INIT_G12;
374 mmioRegisters->hcpVp9EncImageStatusMaskRegOffset = HCP_VP9_ENC_IMAGE_STATUS_MASK_REG_OFFSET_INIT_G12;
375 mmioRegisters->hcpVp9EncImageStatusCtrlRegOffset = HCP_VP9_ENC_IMAGE_STATUS_CTRL_REG_OFFSET_INIT_G12;
376 mmioRegisters->csEngineIdOffset = CS_ENGINE_ID_OFFSET_INIT_G12;
377 mmioRegisters->hcpDecStatusRegOffset = HCP_DEC_STATUS_REG_OFFSET_INIT_G12;
378 mmioRegisters->hcpCabacStatusRegOffset = HCP_CABAC_STATUS_REG_OFFSET_INIT_G12;
379 mmioRegisters->hcpFrameCrcRegOffset = HCP_FRAME_CRC_REG_OFFSET_INIT_G12;
380
381 m_mmioRegisters[MHW_VDBOX_NODE_2] = m_mmioRegisters[MHW_VDBOX_NODE_1];
382 }
383
InitRowstoreUserFeatureSettings()384 void MhwVdboxHcpInterfaceG12::InitRowstoreUserFeatureSettings()
385 {
386 MOS_USER_FEATURE_VALUE_DATA userFeatureData;
387 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
388
389 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
390 if (m_osInterface->bSimIsActive)
391 {
392 // GEN12 can support row store cache
393 userFeatureData.u32Data = 1;
394 }
395 else
396 {
397 userFeatureData.u32Data = 0;
398 }
399
400 userFeatureData.i32DataFlag = MOS_USER_FEATURE_VALUE_DATA_FLAG_CUSTOM_DEFAULT_VALUE_TYPE;
401 #if (_DEBUG || _RELEASE_INTERNAL)
402 MOS_UserFeature_ReadValue_ID(
403 nullptr,
404 __MEDIA_USER_FEATURE_VALUE_ROWSTORE_CACHE_DISABLE_ID,
405 &userFeatureData,
406 m_osInterface->pOsContext);
407 #endif // _DEBUG || _RELEASE_INTERNAL
408 m_rowstoreCachingSupported = userFeatureData.i32Data ? false : true;
409
410 if (m_rowstoreCachingSupported)
411 {
412 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
413 #if (_DEBUG || _RELEASE_INTERNAL)
414 MOS_UserFeature_ReadValue_ID(
415 nullptr,
416 __MEDIA_USER_FEATURE_VALUE_HEVCDATROWSTORECACHE_DISABLE_ID,
417 &userFeatureData,
418 m_osInterface->pOsContext);
419 #endif // _DEBUG || _RELEASE_INTERNAL
420 m_hevcDatRowStoreCache.bSupported = userFeatureData.i32Data ? false : true;
421
422 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
423 #if (_DEBUG || _RELEASE_INTERNAL)
424 MOS_UserFeature_ReadValue_ID(
425 nullptr,
426 __MEDIA_USER_FEATURE_VALUE_HEVCDFROWSTORECACHE_DISABLE_ID,
427 &userFeatureData,
428 m_osInterface->pOsContext);
429 #endif // _DEBUG || _RELEASE_INTERNAL
430 m_hevcDfRowStoreCache.bSupported = userFeatureData.i32Data ? false : true;
431
432 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
433 #if (_DEBUG || _RELEASE_INTERNAL)
434 MOS_UserFeature_ReadValue_ID(
435 nullptr,
436 __MEDIA_USER_FEATURE_VALUE_HEVCSAOROWSTORECACHE_DISABLE_ID,
437 &userFeatureData,
438 m_osInterface->pOsContext);
439 #endif // _DEBUG || _RELEASE_INTERNAL
440 m_hevcSaoRowStoreCache.bSupported = userFeatureData.i32Data ? false : true;
441 m_hevcHSaoRowStoreCache.bSupported = m_hevcSaoRowStoreCache.bSupported;
442
443 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
444 #if (_DEBUG || _RELEASE_INTERNAL)
445 MOS_UserFeature_ReadValue_ID(
446 nullptr,
447 __MEDIA_USER_FEATURE_VALUE_VP9_HVDROWSTORECACHE_DISABLE_ID,
448 &userFeatureData,
449 m_osInterface->pOsContext);
450 #endif // _DEBUG || _RELEASE_INTERNAL
451 m_vp9HvdRowStoreCache.bSupported = userFeatureData.i32Data ? false : true;
452
453 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
454 #if (_DEBUG || _RELEASE_INTERNAL)
455 MOS_UserFeature_ReadValue_ID(
456 nullptr,
457 __MEDIA_USER_FEATURE_VALUE_VP9_DATROWSTORECACHE_DISABLE_ID,
458 &userFeatureData,
459 m_osInterface->pOsContext);
460 #endif // _DEBUG || _RELEASE_INTERNAL
461 m_vp9DatRowStoreCache.bSupported = userFeatureData.i32Data ? false : true;
462
463 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
464 #if (_DEBUG || _RELEASE_INTERNAL)
465 MOS_UserFeature_ReadValue_ID(
466 nullptr,
467 __MEDIA_USER_FEATURE_VALUE_VP9_DFROWSTORECACHE_DISABLE_ID,
468 &userFeatureData,
469 m_osInterface->pOsContext);
470 #endif // _DEBUG || _RELEASE_INTERNAL
471 m_vp9DfRowStoreCache.bSupported = userFeatureData.i32Data ? false : true;
472 }
473 }
474
GetRowstoreCachingAddrs(PMHW_VDBOX_ROWSTORE_PARAMS rowstoreParams)475 MOS_STATUS MhwVdboxHcpInterfaceG12::GetRowstoreCachingAddrs(
476 PMHW_VDBOX_ROWSTORE_PARAMS rowstoreParams)
477 {
478 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
479
480 MHW_ASSERT(rowstoreParams);
481
482 MHW_FUNCTION_ENTER;
483
484 bool is8bit = rowstoreParams->ucBitDepthMinus8 == 0;
485 bool is10bit = rowstoreParams->ucBitDepthMinus8 == 1 || rowstoreParams->ucBitDepthMinus8 == 2;
486 bool is12bit = rowstoreParams->ucBitDepthMinus8 > 2;
487 bool isLcu32or64 = rowstoreParams->ucLCUSize == 32 || rowstoreParams->ucLCUSize == 64;
488 bool isGt2k = rowstoreParams->dwPicWidth > 2048;
489 bool isGt4k = rowstoreParams->dwPicWidth > 4096;
490 bool isGt8k = rowstoreParams->dwPicWidth > 8192;
491
492 uint32_t index = 0;
493
494 //HCP pipe for both HEVC decoder and HEVC encoder
495 if (rowstoreParams->Mode == CODECHAL_DECODE_MODE_HEVCVLD || rowstoreParams->Mode == CODECHAL_ENCODE_MODE_HEVC)
496 {
497 m_hevcDatRowStoreCache.bEnabled = false;
498 m_hevcDatRowStoreCache.dwAddress = 0;
499 m_hevcDfRowStoreCache.bEnabled = false;
500 m_hevcDfRowStoreCache.dwAddress = 0;
501 m_hevcSaoRowStoreCache.bEnabled = false;
502 m_hevcSaoRowStoreCache.dwAddress = 0;
503 m_hevcHSaoRowStoreCache.bEnabled = false;
504 m_hevcHSaoRowStoreCache.dwAddress = 0;
505
506 if (isGt8k)
507 {
508 // Gen12 does not support row store cache for pic width > 8K
509 return eStatus;
510 }
511
512 if ((rowstoreParams->ucChromaFormat == HCP_CHROMA_FORMAT_YUV420) ||
513 (rowstoreParams->ucChromaFormat == HCP_CHROMA_FORMAT_YUV422))
514 {
515 index = 2 * isGt4k + isLcu32or64;
516 }
517 else if (rowstoreParams->ucChromaFormat == HCP_CHROMA_FORMAT_YUV444)
518 {
519 uint32_t subidx = is12bit ? 2 : (is10bit ? 1 : 0);
520 index = 4 + 6 * isLcu32or64 + 2 * subidx + isGt4k;
521 }
522 else
523 {
524 return eStatus;
525 }
526
527 if (m_hevcDatRowStoreCache.bSupported)
528 {
529 m_hevcDatRowStoreCache.bEnabled = RowStoreCacheEnableHEVC[index][0];
530 m_hevcDatRowStoreCache.dwAddress = RowStoreCacheAddrHEVC[index][0];
531 }
532
533 if (m_hevcDfRowStoreCache.bSupported)
534 {
535 m_hevcDfRowStoreCache.bEnabled = RowStoreCacheEnableHEVC[index][1];
536 m_hevcDfRowStoreCache.dwAddress = RowStoreCacheAddrHEVC[index][1];
537 }
538
539 if (m_hevcSaoRowStoreCache.bSupported)
540 {
541 m_hevcSaoRowStoreCache.bEnabled = RowStoreCacheEnableHEVC[index][2];
542 m_hevcSaoRowStoreCache.dwAddress = RowStoreCacheAddrHEVC[index][2];
543 }
544
545 if (m_hevcHSaoRowStoreCache.bSupported)
546 {
547 m_hevcHSaoRowStoreCache.bEnabled = RowStoreCacheEnableHEVC[index][4];
548 m_hevcHSaoRowStoreCache.dwAddress = RowStoreCacheAddrHEVC[index][4];
549 }
550 }
551
552 if (rowstoreParams->Mode == CODECHAL_DECODE_MODE_VP9VLD || rowstoreParams->Mode == CODECHAL_ENCODE_MODE_VP9)
553 {
554 m_vp9HvdRowStoreCache.bEnabled = false;
555 m_vp9HvdRowStoreCache.dwAddress = 0;
556 m_vp9DatRowStoreCache.bEnabled = false;
557 m_vp9DatRowStoreCache.dwAddress = 0;
558 m_vp9DfRowStoreCache.bEnabled = false;
559 m_vp9DfRowStoreCache.dwAddress = 0;
560
561 if (isGt8k)
562 {
563 // Gen12 does not support row store cache for pic width > 8K
564 return eStatus;
565 }
566
567 if ((rowstoreParams->ucChromaFormat >= HCP_CHROMA_FORMAT_YUV420) &&
568 (rowstoreParams->ucChromaFormat <= HCP_CHROMA_FORMAT_YUV444))
569 {
570 index = 4 * (rowstoreParams->ucChromaFormat - HCP_CHROMA_FORMAT_YUV420) + 2 * (!is8bit) + isGt4k;
571 }
572 else
573 {
574 return eStatus;
575 }
576
577 if (rowstoreParams->ucChromaFormat == HCP_CHROMA_FORMAT_YUV444 && !is8bit)
578 {
579 index += isGt2k;
580 }
581
582 if (m_vp9HvdRowStoreCache.bSupported)
583 {
584 m_vp9HvdRowStoreCache.bEnabled = RowStoreCacheEnableVP9[index][0];
585 m_vp9HvdRowStoreCache.dwAddress = RowStoreCacheAddrVP9[index][0];
586 }
587
588 if (m_vp9DatRowStoreCache.bSupported)
589 {
590 m_vp9DatRowStoreCache.bEnabled = RowStoreCacheEnableVP9[index][1];
591 m_vp9DatRowStoreCache.dwAddress = RowStoreCacheAddrVP9[index][1];
592 }
593
594 if (m_vp9DfRowStoreCache.bSupported)
595 {
596 m_vp9DfRowStoreCache.bEnabled = RowStoreCacheEnableVP9[index][2];
597 m_vp9DfRowStoreCache.dwAddress = RowStoreCacheAddrVP9[index][2];
598 }
599
600 }
601
602 return eStatus;
603 }
604
GetHcpStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)605 MOS_STATUS MhwVdboxHcpInterfaceG12::GetHcpStateCommandSize(
606 uint32_t mode,
607 uint32_t *commandsSize,
608 uint32_t *patchListSize,
609 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
610 {
611 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
612
613 MHW_FUNCTION_ENTER;
614
615 uint32_t maxSize = 0;
616 uint32_t patchListMaxSize = 0;
617 uint32_t standard = CodecHal_GetStandardFromMode(mode);
618 MHW_CHK_NULL_RETURN(params);
619 auto paramsG12 = dynamic_cast<PMHW_VDBOX_STATE_CMDSIZE_PARAMS_G12>(params);
620 MHW_CHK_NULL_RETURN(paramsG12);
621
622 if (standard == CODECHAL_HEVC)
623 {
624 maxSize =
625 mhw_vdbox_vdenc_g12_X::VD_PIPELINE_FLUSH_CMD::byteSize +
626 mhw_mi_g12_X::MI_FLUSH_DW_CMD::byteSize +
627 mhw_vdbox_hcp_g12_X::HCP_PIPE_MODE_SELECT_CMD::byteSize +
628 mhw_vdbox_hcp_g12_X::HCP_SURFACE_STATE_CMD::byteSize +
629 mhw_vdbox_hcp_g12_X::HCP_PIPE_BUF_ADDR_STATE_CMD::byteSize +
630 mhw_vdbox_hcp_g12_X::HCP_IND_OBJ_BASE_ADDR_STATE_CMD::byteSize +
631 mhw_mi_g12_X::MI_LOAD_REGISTER_REG_CMD::byteSize * 8;
632
633 patchListMaxSize =
634 PATCH_LIST_COMMAND(VD_PIPELINE_FLUSH_CMD) +
635 PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD) +
636 PATCH_LIST_COMMAND(HCP_PIPE_MODE_SELECT_CMD) +
637 PATCH_LIST_COMMAND(HCP_SURFACE_STATE_CMD) +
638 PATCH_LIST_COMMAND(HCP_PIPE_BUF_ADDR_STATE_CMD) +
639 PATCH_LIST_COMMAND(HCP_IND_OBJ_BASE_ADDR_STATE_CMD);
640
641 if (mode == CODECHAL_ENCODE_MODE_HEVC)
642 {
643 /* HCP_QM_STATE_CMD may be issued up to 20 times: 3x Colour Component plus 2x intra/inter plus 4x SizeID minus 4 for the 32x32 chroma components.
644 HCP_FQP_STATE_CMD may be issued up to 8 times: 4 scaling list per intra and inter. */
645 maxSize +=
646 2 * mhw_mi_g12_X::VD_CONTROL_STATE_CMD::byteSize +
647 mhw_vdbox_hcp_g12_X::HCP_SURFACE_STATE_CMD::byteSize + // encoder needs two surface state commands. One is for raw and another one is for recon surfaces.
648 20 * mhw_vdbox_hcp_g12_X::HCP_QM_STATE_CMD::byteSize +
649 8 * mhw_vdbox_hcp_g12_X::HCP_FQM_STATE_CMD::byteSize +
650 mhw_vdbox_hcp_g12_X::HCP_PIC_STATE_CMD::byteSize +
651 mhw_vdbox_hcp_g12_X::HEVC_VP9_RDOQ_STATE_CMD::byteSize + // RDOQ
652 2 * mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize + // Slice level commands
653 2 * mhw_mi_g12_X::MI_FLUSH_DW_CMD::byteSize + // need for Status report, Mfc Status and
654 10 * mhw_mi_g12_X::MI_STORE_REGISTER_MEM_CMD::byteSize + // 8 for BRCStatistics and 2 for RC6 WAs
655 mhw_mi_g12_X::MI_LOAD_REGISTER_MEM_CMD::byteSize + // 1 for RC6 WA
656 2 * mhw_vdbox_hcp_g12_X::HCP_PAK_INSERT_OBJECT_CMD::byteSize + // Two PAK insert object commands are for headers before the slice header and the header for the end of stream
657 4 * mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize + // two (BRC+reference frame) for clean-up HW semaphore memory and another two for signal it
658 17 * mhw_mi_g12_X::MI_SEMAPHORE_WAIT_CMD::byteSize +// Use HW wait command for each reference and one wait for current semaphore object
659 mhw_mi_g12_X::MI_SEMAPHORE_WAIT_CMD::byteSize + // Use HW wait command for each BRC pass
660 + mhw_mi_g12_X::MI_SEMAPHORE_WAIT_CMD::byteSize // Use HW wait command for each VDBOX
661 + 2 * mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize // One is for reset and another one for set per VDBOX
662 + 8 * mhw_mi_g12_X::MI_COPY_MEM_MEM_CMD::byteSize // Need to copy SSE statistics/ Slice Size overflow into memory
663 ;
664
665 patchListMaxSize +=
666 20 * PATCH_LIST_COMMAND(HCP_QM_STATE_CMD) +
667 8 * PATCH_LIST_COMMAND(HCP_FQM_STATE_CMD) +
668 PATCH_LIST_COMMAND(HCP_PIC_STATE_CMD) +
669 PATCH_LIST_COMMAND(MI_BATCH_BUFFER_START_CMD) + // When BRC is on, HCP_PIC_STATE_CMD command is in the BB
670 2 * PATCH_LIST_COMMAND(MI_STORE_DATA_IMM_CMD) + // Slice level commands
671 2 * PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD) + // need for Status report, Mfc Status and
672 11 * PATCH_LIST_COMMAND(MI_STORE_REGISTER_MEM_CMD) + // 8 for BRCStatistics and 3 for RC6 WAs
673 22 * PATCH_LIST_COMMAND(MI_STORE_DATA_IMM_CMD) // Use HW wait commands plus its memory clean-up and signal (4+ 16 + 1 + 1)
674 + 8 * PATCH_LIST_COMMAND(MI_BATCH_BUFFER_START_CMD) // At maximal, there are 8 batch buffers for 8 VDBOXes for VE. Each box has one BB.
675 + PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD) // Need one flush before copy command
676 + PATCH_LIST_COMMAND(MFX_WAIT_CMD) // Need one wait after copy command
677 + 3 * PATCH_LIST_COMMAND(MI_STORE_DATA_IMM_CMD) // one wait commands and two for reset and set semaphore memory
678 + 8 * PATCH_LIST_COMMAND(MI_COPY_MEM_MEM_CMD) // Need to copy SSE statistics/ Slice Size overflow into memory
679 ;
680 }
681 else
682 {
683 maxSize +=
684 2 * mhw_mi_g12_X::VD_CONTROL_STATE_CMD::byteSize + // VD_CONTROL_STATE Hcp init and flush
685 20 * mhw_vdbox_hcp_g12_X::HCP_QM_STATE_CMD::byteSize +
686 mhw_vdbox_hcp_g12_X::HCP_PIC_STATE_CMD::byteSize +
687 mhw_vdbox_hcp_g12_X::HCP_TILE_STATE_CMD::byteSize;
688
689 patchListMaxSize +=
690 20 * PATCH_LIST_COMMAND(HCP_QM_STATE_CMD) +
691 PATCH_LIST_COMMAND(HCP_PIC_STATE_CMD) +
692 PATCH_LIST_COMMAND(HCP_TILE_STATE_CMD);
693
694 if (params->bSfcInUse)
695 {
696 maxSize +=
697 mhw_sfc_g12_X::SFC_LOCK_CMD::byteSize +
698 2 * mhw_mi_g12_X::VD_CONTROL_STATE_CMD::byteSize +
699 mhw_sfc_g12_X::SFC_STATE_CMD::byteSize +
700 mhw_sfc_g12_X::SFC_AVS_STATE_CMD::byteSize +
701 mhw_sfc_g12_X::SFC_AVS_LUMA_Coeff_Table_CMD::byteSize +
702 mhw_sfc_g12_X::SFC_AVS_CHROMA_Coeff_Table_CMD::byteSize +
703 mhw_sfc_g12_X::SFC_IEF_STATE_CMD::byteSize +
704 mhw_sfc_g12_X::SFC_FRAME_START_CMD::byteSize;
705 patchListMaxSize +=
706 MhwSfcInterfaceG12::CommandsNumberOfAddresses::SFC_STATE_CMD_NUMBER_OF_ADDRESSES +
707 MhwSfcInterfaceG12::CommandsNumberOfAddresses::SFC_AVS_CHROMA_Coeff_Table_CMD_NUMBER_OF_ADDRESSES +
708 MhwSfcInterfaceG12::CommandsNumberOfAddresses::SFC_AVS_LUMA_Coeff_Table_CMD_NUMBER_OF_ADDRESSES +
709 MhwSfcInterfaceG12::CommandsNumberOfAddresses::SFC_AVS_STATE_CMD_NUMBER_OF_ADDRESSES +
710 MhwSfcInterfaceG12::CommandsNumberOfAddresses::SFC_FRAME_START_CMD_NUMBER_OF_ADDRESSES +
711 MhwSfcInterfaceG12::CommandsNumberOfAddresses::SFC_IEF_STATE_CMD_NUMBER_OF_ADDRESSES +
712 MhwSfcInterfaceG12::CommandsNumberOfAddresses::SFC_LOCK_CMD_NUMBER_OF_ADDRESSES;
713 }
714
715 if (paramsG12->bScalableMode)
716 {
717 // VD_CONTROL_STATE Hcp lock and unlock
718 maxSize += 2 * mhw_mi_g12_X::VD_CONTROL_STATE_CMD::byteSize;
719
720 // Due to the fact that there is no slice level command in BE status, we mainly consider commands in FE.
721 maxSize +=
722 4 * mhw_mi_g12_X::MI_ATOMIC_CMD::byteSize + // used to reset semaphore in BEs
723 2 * mhw_mi_g12_X::MI_CONDITIONAL_BATCH_BUFFER_END_CMD::byteSize + // 1 Conditional BB END for FE hang, 1 for streamout buffer writing over allocated size
724 3 * mhw_mi_g12_X::MI_SEMAPHORE_WAIT_CMD::byteSize + // for FE & BE0, BEs sync
725 15 * mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize + // for placeholder cmds to resolve the hazard between BEs sync
726 3 * mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize + // for FE status set and clear
727 3 * mhw_mi_g12_X::MI_LOAD_REGISTER_IMM_CMD::byteSize + // for FE status set
728 2 * mhw_mi_g12_X::MI_FLUSH_DW_CMD::byteSize + // 2 needed for command flush in slice level
729 2 * mhw_mi_g12_X::MI_STORE_REGISTER_MEM_CMD::byteSize + // store the carry flag of reported size in FE
730 4 * sizeof(MHW_MI_ALU_PARAMS) + // 4 ALU commands needed for substract opertaion in FE
731 mhw_mi_g12_X::MI_MATH_CMD::byteSize + // 1 needed for FE status set
732 mhw_mi_g12_X::MI_LOAD_REGISTER_REG_CMD::byteSize; // 1 needed for FE status set
733 mhw_mi_g12_X::MI_MATH_CMD::byteSize + // 1 needed for FE status set
734 mhw_mi_g12_X::MI_LOAD_REGISTER_REG_CMD::byteSize; // 1 needed for FE status set
735
736 patchListMaxSize +=
737 4 * PATCH_LIST_COMMAND(MI_ATOMIC_CMD) +
738 2 * PATCH_LIST_COMMAND(MI_CONDITIONAL_BATCH_BUFFER_END_CMD) +
739 3 * PATCH_LIST_COMMAND(MI_SEMAPHORE_WAIT_CMD) +
740 18 * PATCH_LIST_COMMAND(MI_STORE_DATA_IMM_CMD) +
741 2 * PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD) +
742 2 * PATCH_LIST_COMMAND(MI_STORE_REGISTER_MEM_CMD);
743
744 if (params->bSfcInUse)
745 {
746 maxSize +=
747 mhw_sfc_g12_X::SFC_LOCK_CMD::byteSize +
748 2 * mhw_mi_g12_X::VD_CONTROL_STATE_CMD::byteSize +
749 mhw_sfc_g12_X::SFC_STATE_CMD::byteSize +
750 mhw_sfc_g12_X::SFC_AVS_STATE_CMD::byteSize +
751 mhw_sfc_g12_X::SFC_AVS_LUMA_Coeff_Table_CMD::byteSize +
752 mhw_sfc_g12_X::SFC_AVS_CHROMA_Coeff_Table_CMD::byteSize +
753 mhw_sfc_g12_X::SFC_IEF_STATE_CMD::byteSize +
754 mhw_sfc_g12_X::SFC_FRAME_START_CMD::byteSize;
755 patchListMaxSize +=
756 MhwSfcInterfaceG12::CommandsNumberOfAddresses::SFC_STATE_CMD_NUMBER_OF_ADDRESSES +
757 MhwSfcInterfaceG12::CommandsNumberOfAddresses::SFC_AVS_CHROMA_Coeff_Table_CMD_NUMBER_OF_ADDRESSES +
758 MhwSfcInterfaceG12::CommandsNumberOfAddresses::SFC_AVS_LUMA_Coeff_Table_CMD_NUMBER_OF_ADDRESSES +
759 MhwSfcInterfaceG12::CommandsNumberOfAddresses::SFC_AVS_STATE_CMD_NUMBER_OF_ADDRESSES +
760 MhwSfcInterfaceG12::CommandsNumberOfAddresses::SFC_FRAME_START_CMD_NUMBER_OF_ADDRESSES +
761 MhwSfcInterfaceG12::CommandsNumberOfAddresses::SFC_IEF_STATE_CMD_NUMBER_OF_ADDRESSES +
762 MhwSfcInterfaceG12::CommandsNumberOfAddresses::SFC_LOCK_CMD_NUMBER_OF_ADDRESSES;
763 }
764 }
765 }
766 }
767 else if (standard == CODECHAL_VP9) // VP9 Clear Decode
768 {
769 maxSize =
770 mhw_vdbox_vdenc_g12_X::VD_PIPELINE_FLUSH_CMD::byteSize +
771 mhw_mi_g12_X::MI_FLUSH_DW_CMD::byteSize +
772 mhw_vdbox_hcp_g12_X::HCP_PIPE_MODE_SELECT_CMD::byteSize +
773 mhw_vdbox_hcp_g12_X::HCP_SURFACE_STATE_CMD::byteSize * 4 +
774 mhw_vdbox_hcp_g12_X::HCP_PIPE_BUF_ADDR_STATE_CMD::byteSize +
775 mhw_vdbox_hcp_g12_X::HCP_IND_OBJ_BASE_ADDR_STATE_CMD::byteSize +
776 mhw_vdbox_hcp_g12_X::HCP_VP9_SEGMENT_STATE_CMD::byteSize * 8 +
777 mhw_vdbox_hcp_g12_X::HCP_BSD_OBJECT_CMD::byteSize +
778 mhw_mi_g12_X::MI_LOAD_REGISTER_REG_CMD::byteSize * 8;
779
780 patchListMaxSize =
781 PATCH_LIST_COMMAND(VD_PIPELINE_FLUSH_CMD) +
782 PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD) +
783 PATCH_LIST_COMMAND(HCP_PIPE_MODE_SELECT_CMD) +
784 PATCH_LIST_COMMAND(HCP_SURFACE_STATE_CMD) * 4 +
785 PATCH_LIST_COMMAND(HCP_PIPE_BUF_ADDR_STATE_CMD) +
786 PATCH_LIST_COMMAND(HCP_IND_OBJ_BASE_ADDR_STATE_CMD) +
787 PATCH_LIST_COMMAND(HCP_VP9_SEGMENT_STATE_CMD) * 8 +
788 PATCH_LIST_COMMAND(HCP_BSD_OBJECT_CMD);
789
790 if (mode == CODECHAL_ENCODE_MODE_VP9)
791 {
792 maxSize +=
793 mhw_vdbox_hcp_g12_X::HCP_VP9_PIC_STATE_CMD::byteSize +
794 mhw_mi_g12_X::MI_FLUSH_DW_CMD::byteSize * 2 +
795 mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize * 4 +
796 mhw_mi_g12_X::MI_STORE_REGISTER_MEM_CMD::byteSize * 11 +
797 mhw_mi_g12_X::MI_COPY_MEM_MEM_CMD::byteSize * 4 +
798 mhw_mi_g12_X::MI_BATCH_BUFFER_START_CMD::byteSize * 3 +
799 mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize * 2 + // Slice level commands
800 mhw_mi_g12_X::MI_LOAD_REGISTER_MEM_CMD::byteSize * 2 +
801 mhw_vdbox_hcp_g12_X::HCP_PAK_INSERT_OBJECT_CMD::byteSize * 2 +
802 mhw_vdbox_hcp_g12_X::HCP_TILE_CODING_CMD::byteSize +
803 mhw_mi_g12_X::MI_BATCH_BUFFER_START_CMD::byteSize +
804 mhw_mi_g12_X::MI_SEMAPHORE_WAIT_CMD::byteSize + // Use HW wait command for each VDBOX
805 mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize * 3; // One is for reset and another one for set per VDBOX, one for wait
806
807 maxSize += 3 * mhw_mi_g12_X::VD_CONTROL_STATE_CMD::byteSize; // VD_CONTROL_STATE Hcp init + flush + vdenc init
808
809 patchListMaxSize +=
810 PATCH_LIST_COMMAND(HCP_VP9_PIC_STATE_CMD) +
811 PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD) * 2 +
812 PATCH_LIST_COMMAND(MI_STORE_DATA_IMM_CMD) * 4 +
813 PATCH_LIST_COMMAND(MI_STORE_REGISTER_MEM_CMD) * 11 +
814 PATCH_LIST_COMMAND(MI_COPY_MEM_MEM_CMD) * 4 +
815 PATCH_LIST_COMMAND(MI_BATCH_BUFFER_START_CMD) * 3 +
816 PATCH_LIST_COMMAND(MI_STORE_DATA_IMM_CMD) * 2 +
817 PATCH_LIST_COMMAND(HCP_PAK_INSERT_OBJECT_CMD) * 2 +
818 PATCH_LIST_COMMAND(HCP_TILE_CODING_COMMAND) +
819 PATCH_LIST_COMMAND(MI_BATCH_BUFFER_START_CMD) +
820 PATCH_LIST_COMMAND(MI_STORE_DATA_IMM_CMD) * 2;
821 }
822 else
823 {
824 maxSize += mhw_vdbox_hcp_g12_X::HCP_VP9_PIC_STATE_CMD::byteSize;
825
826 // VD_CONTROL_STATE Hcp init and flush
827 maxSize += 2 * mhw_mi_g12_X::VD_CONTROL_STATE_CMD::byteSize;
828
829 patchListMaxSize += PATCH_LIST_COMMAND(HCP_VP9_PIC_STATE_CMD);
830
831 if (params->bSfcInUse)
832 {
833 maxSize +=
834 mhw_sfc_g12_X::SFC_LOCK_CMD::byteSize +
835 2 * mhw_mi_g12_X::VD_CONTROL_STATE_CMD::byteSize +
836 mhw_sfc_g12_X::SFC_STATE_CMD::byteSize +
837 mhw_sfc_g12_X::SFC_AVS_STATE_CMD::byteSize +
838 mhw_sfc_g12_X::SFC_AVS_LUMA_Coeff_Table_CMD::byteSize +
839 mhw_sfc_g12_X::SFC_AVS_CHROMA_Coeff_Table_CMD::byteSize +
840 mhw_sfc_g12_X::SFC_IEF_STATE_CMD::byteSize +
841 mhw_sfc_g12_X::SFC_FRAME_START_CMD::byteSize;
842 }
843
844 if (paramsG12->bScalableMode)
845 {
846 // VD_CONTROL_STATE Hcp lock and unlock
847 maxSize += 2 * mhw_mi_g12_X::VD_CONTROL_STATE_CMD::byteSize;
848
849 maxSize +=
850 mhw_vdbox_hcp_g12_X::HCP_TILE_CODING_CMD::byteSize +
851 2 * mhw_mi_g12_X::VD_CONTROL_STATE_CMD::byteSize +
852 mhw_mi_g12_X::MI_ATOMIC_CMD::byteSize * 4 + // used to reset semaphore in BEs
853 mhw_mi_g12_X::MI_CONDITIONAL_BATCH_BUFFER_END_CMD::byteSize + // for streamout buffer writing over allocated size
854 mhw_mi_g12_X::MI_SEMAPHORE_WAIT_CMD::byteSize * 3 + // for FE & BE0, BEs sync
855 mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize * 15 + // for placeholder cmds to resolve the hazard between BEs sync
856 mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize + // for FE status set
857 mhw_mi_g12_X::MI_LOAD_REGISTER_IMM_CMD::byteSize * 3 + // for FE status set
858 mhw_mi_g12_X::MI_FLUSH_DW_CMD::byteSize + // for command flush in partition level
859 mhw_mi_g12_X::MI_STORE_REGISTER_MEM_CMD::byteSize * 2 + // store the carry flag of reported size in FE
860 4 * sizeof(MHW_MI_ALU_PARAMS) + // 4 ALU commands needed for substract opertaion in FE
861 mhw_mi_g12_X::MI_MATH_CMD::byteSize + // 1 needed for FE status set
862 mhw_mi_g12_X::MI_LOAD_REGISTER_REG_CMD::byteSize; // 1 needed for FE status set
863 mhw_mi_g12_X::MI_MATH_CMD::byteSize + // 1 needed for FE status set
864 mhw_mi_g12_X::MI_LOAD_REGISTER_REG_CMD::byteSize; // 1 needed for FE status set
865
866 patchListMaxSize +=
867 PATCH_LIST_COMMAND(HCP_TILE_CODING_COMMAND) +
868 PATCH_LIST_COMMAND(MI_ATOMIC_CMD) * 4 +
869 PATCH_LIST_COMMAND(MI_CONDITIONAL_BATCH_BUFFER_END_CMD) +
870 PATCH_LIST_COMMAND(MI_SEMAPHORE_WAIT_CMD) * 3 +
871 PATCH_LIST_COMMAND(MI_STORE_DATA_IMM_CMD) +
872 PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD) +
873 PATCH_LIST_COMMAND(MI_STORE_REGISTER_MEM_CMD) * 2;
874
875 if (params->bSfcInUse)
876 {
877 maxSize +=
878 mhw_sfc_g12_X::SFC_LOCK_CMD::byteSize +
879 2 * mhw_mi_g12_X::VD_CONTROL_STATE_CMD::byteSize +
880 mhw_sfc_g12_X::SFC_STATE_CMD::byteSize +
881 mhw_sfc_g12_X::SFC_AVS_STATE_CMD::byteSize +
882 mhw_sfc_g12_X::SFC_AVS_LUMA_Coeff_Table_CMD::byteSize +
883 mhw_sfc_g12_X::SFC_AVS_CHROMA_Coeff_Table_CMD::byteSize +
884 mhw_sfc_g12_X::SFC_IEF_STATE_CMD::byteSize +
885 mhw_sfc_g12_X::SFC_FRAME_START_CMD::byteSize;
886 }
887 }
888 }
889 }
890 else
891 {
892 MHW_ASSERTMESSAGE("Unsupported standard.");
893 eStatus = MOS_STATUS_UNKNOWN;
894 }
895
896 *commandsSize = maxSize;
897 *patchListSize = patchListMaxSize;
898
899 return eStatus;
900 }
901
GetHcpPrimitiveCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,bool modeSpecific)902 MOS_STATUS MhwVdboxHcpInterfaceG12::GetHcpPrimitiveCommandSize(
903 uint32_t mode,
904 uint32_t *commandsSize,
905 uint32_t *patchListSize,
906 bool modeSpecific)
907 {
908 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
909
910 MHW_FUNCTION_ENTER;
911
912 uint32_t standard = CodecHal_GetStandardFromMode(mode);
913 uint32_t maxSize = 0;
914 uint32_t patchListMaxSize = 0;
915
916 if (standard == CODECHAL_HEVC)
917 {
918 if (mode == CODECHAL_ENCODE_MODE_HEVC)
919 {
920 maxSize =
921 2 * mhw_vdbox_hcp_g12_X::HCP_REF_IDX_STATE_CMD::byteSize +
922 2 * mhw_vdbox_hcp_g12_X::HCP_WEIGHTOFFSET_STATE_CMD::byteSize +
923 mhw_vdbox_hcp_g12_X::HCP_SLICE_STATE_CMD::byteSize +
924 mhw_vdbox_hcp_g12_X::HCP_PAK_INSERT_OBJECT_CMD::byteSize +
925 2 * mhw_mi_g12_X::MI_BATCH_BUFFER_START_CMD::byteSize +
926 mhw_vdbox_hcp_g12_X::HCP_TILE_CODING_CMD::byteSize; // one slice cannot be with more than one tile
927
928 patchListMaxSize =
929 2 * PATCH_LIST_COMMAND(HCP_REF_IDX_STATE_CMD) +
930 2 * PATCH_LIST_COMMAND(HCP_WEIGHTOFFSET_STATE_CMD) +
931 PATCH_LIST_COMMAND(HCP_SLICE_STATE_CMD) +
932 PATCH_LIST_COMMAND(HCP_PAK_INSERT_OBJECT_CMD) +
933 2 * PATCH_LIST_COMMAND(MI_BATCH_BUFFER_START_CMD) + // One is for the PAK command and another one is for the BB when BRC and single task mode are on
934 PATCH_LIST_COMMAND(HCP_TILE_CODING_COMMAND); // HCP_TILE_CODING_STATE command
935 }
936 else
937 {
938 maxSize =
939 2 * mhw_vdbox_hcp_g12_X::HCP_REF_IDX_STATE_CMD::byteSize +
940 2 * mhw_vdbox_hcp_g12_X::HCP_WEIGHTOFFSET_STATE_CMD::byteSize +
941 mhw_vdbox_hcp_g12_X::HCP_SLICE_STATE_CMD::byteSize +
942 2 * mhw_mi_g12_X::VD_CONTROL_STATE_CMD::byteSize +
943 mhw_vdbox_hcp_g12_X::HCP_TILE_CODING_CMD::byteSize +
944 mhw_vdbox_hcp_g12_X::HCP_PALETTE_INITIALIZER_STATE_CMD::byteSize +
945 mhw_vdbox_hcp_g12_X::HCP_BSD_OBJECT_CMD::byteSize +
946 mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
947
948 patchListMaxSize =
949 2 * PATCH_LIST_COMMAND(HCP_REF_IDX_STATE_CMD) +
950 2 * PATCH_LIST_COMMAND(HCP_WEIGHTOFFSET_STATE_CMD) +
951 PATCH_LIST_COMMAND(HCP_SLICE_STATE_CMD) +
952 PATCH_LIST_COMMAND(HCP_PALETTE_INITIALIZER_STATE_CMD) +
953 PATCH_LIST_COMMAND(HCP_TILE_CODING_COMMAND) +
954 PATCH_LIST_COMMAND(HCP_BSD_OBJECT_CMD);
955 }
956 }
957 else if (standard == CODECHAL_VP9) // VP9 Clear decode does not require primitive level commands. VP9 DRM does.
958 {
959 if (modeSpecific) // VP9 DRM
960 {
961 maxSize +=
962 mhw_vdbox_hcp_g12_X::HCP_VP9_SEGMENT_STATE_CMD::byteSize * 8 +
963 mhw_vdbox_hcp_g12_X::HCP_VP9_PIC_STATE_CMD::byteSize +
964 mhw_vdbox_hcp_g12_X::HCP_BSD_OBJECT_CMD::byteSize +
965 mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
966
967 patchListMaxSize =
968 PATCH_LIST_COMMAND(HCP_VP9_SEGMENT_STATE_CMD) * 8 +
969 PATCH_LIST_COMMAND(HCP_VP9_PIC_STATE_CMD) +
970 PATCH_LIST_COMMAND(HCP_BSD_OBJECT_CMD);
971 }
972 }
973 else
974 {
975 MHW_ASSERTMESSAGE("Unsupported standard.");
976 eStatus = MOS_STATUS_UNKNOWN;
977 }
978
979 *commandsSize = maxSize;
980 *patchListSize = patchListMaxSize;
981
982 return eStatus;
983 }
984
GetHevcBufferSize(MHW_VDBOX_HCP_INTERNAL_BUFFER_TYPE bufferType,PMHW_VDBOX_HCP_BUFFER_SIZE_PARAMS hcpBufSizeParam)985 MOS_STATUS MhwVdboxHcpInterfaceG12::GetHevcBufferSize(
986 MHW_VDBOX_HCP_INTERNAL_BUFFER_TYPE bufferType,
987 PMHW_VDBOX_HCP_BUFFER_SIZE_PARAMS hcpBufSizeParam)
988 {
989 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
990
991 MHW_FUNCTION_ENTER;
992
993 MHW_MI_CHK_NULL(hcpBufSizeParam);
994
995 uint8_t bitDepthMultFactor = 0;
996 uint32_t mvtSize = 0;
997 uint32_t mvtbSize = 0;
998 uint32_t bufferSize = 0;
999 uint32_t rowStoreSzLCU = 0;
1000 uint32_t colStoreSzLCU = 0;
1001 double dbFormatMultFactor = 0;
1002
1003 uint8_t maxBitDepth = hcpBufSizeParam->ucMaxBitDepth;
1004 uint32_t lcusize = 1 << hcpBufSizeParam->dwCtbLog2SizeY;
1005 uint32_t maxFrameSize = hcpBufSizeParam->dwMaxFrameSize;
1006 // HEVC decoder has WA here, change to lcusize when the WA is removed
1007 uint32_t widthInCtb = MOS_ROUNDUP_DIVIDE(hcpBufSizeParam->dwPicWidth, 16);
1008 uint32_t heightInCtb = MOS_ROUNDUP_DIVIDE(hcpBufSizeParam->dwPicHeight, 16);
1009 uint32_t numBaseUnitsInLCU = 1 << (hcpBufSizeParam->dwCtbLog2SizeY - 2);//size in number of 4x4 in the LCU per column
1010 HCP_CHROMA_FORMAT_IDC chromaFormat = (HCP_CHROMA_FORMAT_IDC)hcpBufSizeParam->ucChromaFormat;
1011
1012 switch (bufferType)
1013 {
1014 case MHW_VDBOX_HCP_INTERNAL_BUFFER_DBLK_LINE:
1015 dbFormatMultFactor = (chromaFormat == HCP_CHROMA_FORMAT_YUV444) ? 1.5 : 1;
1016 bitDepthMultFactor = (maxBitDepth > 8) ? 2 : 1;
1017 rowStoreSzLCU = (uint32_t)(((2 * numBaseUnitsInLCU * dbFormatMultFactor * 128 * bitDepthMultFactor) + 511) / 512);
1018 bufferSize = rowStoreSzLCU * MHW_CACHELINE_SIZE * widthInCtb;
1019 break;
1020 case MHW_VDBOX_HCP_INTERNAL_BUFFER_DBLK_TILE_LINE:
1021 dbFormatMultFactor = (chromaFormat == HCP_CHROMA_FORMAT_YUV444) ? 1.5 : 1;
1022 bitDepthMultFactor = (maxBitDepth > 8) ? 2 : 1;
1023 rowStoreSzLCU = (uint32_t)(((2 * numBaseUnitsInLCU * dbFormatMultFactor * 128 * bitDepthMultFactor) + 511) / 512);
1024 bufferSize = 2 * rowStoreSzLCU * MHW_CACHELINE_SIZE * widthInCtb;
1025 break;
1026 case MHW_VDBOX_HCP_INTERNAL_BUFFER_DBLK_TILE_COL:
1027 dbFormatMultFactor = (chromaFormat == HCP_CHROMA_FORMAT_YUV420) ? 1 : 1.5;
1028 bitDepthMultFactor = (maxBitDepth > 8) ? 2 : 1;
1029 colStoreSzLCU = (uint32_t)(((2 * numBaseUnitsInLCU * dbFormatMultFactor * 128 * bitDepthMultFactor + 3 * 128 * bitDepthMultFactor) + 511) / 512);
1030 bufferSize = 2 * colStoreSzLCU * MHW_CACHELINE_SIZE * heightInCtb;
1031 break;
1032 case MHW_VDBOX_HCP_INTERNAL_BUFFER_MV_UP_RT_COL:
1033 colStoreSzLCU = 1;
1034 bufferSize = colStoreSzLCU * MHW_CACHELINE_SIZE * heightInCtb;
1035 break;
1036 case MHW_VDBOX_HCP_INTERNAL_BUFFER_META_LINE:
1037 rowStoreSzLCU = (hcpBufSizeParam->dwCtbLog2SizeY == 6) ? 2 : 1;
1038 bufferSize = rowStoreSzLCU * MHW_CACHELINE_SIZE * widthInCtb;
1039 break;
1040 case MHW_VDBOX_HCP_INTERNAL_BUFFER_META_TILE_LINE:
1041 rowStoreSzLCU = (hcpBufSizeParam->dwCtbLog2SizeY == 6) ? 4 : 2;
1042 bufferSize = rowStoreSzLCU * MHW_CACHELINE_SIZE * widthInCtb;
1043 break;
1044 case MHW_VDBOX_HCP_INTERNAL_BUFFER_META_TILE_COL:
1045 colStoreSzLCU = (hcpBufSizeParam->dwCtbLog2SizeY == 6) ? 4 : 2;
1046 bufferSize = colStoreSzLCU * MHW_CACHELINE_SIZE * heightInCtb;
1047 break;
1048 case MHW_VDBOX_HCP_INTERNAL_BUFFER_INTRA_PRED_UP_RIGHT_COL:
1049 {
1050 uint32_t colStoreSizeLCU[2][3]; //[bitdepth 8/10 or 12][LCU 16/32/64]
1051 if (chromaFormat == HCP_CHROMA_FORMAT_YUV420)
1052 {
1053 colStoreSizeLCU[0][0] = 1; colStoreSizeLCU[0][1] = 1; colStoreSizeLCU[0][2] = 1;
1054 colStoreSizeLCU[1][0] = 1; colStoreSizeLCU[1][1] = 2; colStoreSizeLCU[1][2] = 2;
1055 }
1056 else if (chromaFormat == HCP_CHROMA_FORMAT_YUV422)
1057 {
1058 colStoreSizeLCU[0][0] = 1; colStoreSizeLCU[0][1] = 1; colStoreSizeLCU[0][2] = 1;
1059 colStoreSizeLCU[1][0] = 1; colStoreSizeLCU[1][1] = 2; colStoreSizeLCU[1][2] = 2;
1060 }
1061 else
1062 {
1063 colStoreSizeLCU[0][0] = 1; colStoreSizeLCU[0][1] = 2; colStoreSizeLCU[0][2] = 2;
1064 colStoreSizeLCU[1][0] = 2; colStoreSizeLCU[1][1] = 3; colStoreSizeLCU[1][2] = 3;
1065 }
1066 colStoreSzLCU = colStoreSizeLCU[(maxBitDepth == 8) ? 0 : 1][hcpBufSizeParam->dwCtbLog2SizeY > 3 ? hcpBufSizeParam->dwCtbLog2SizeY - 4 : 0];
1067 bufferSize = colStoreSzLCU * MHW_CACHELINE_SIZE * heightInCtb;
1068 break;
1069 }
1070 case MHW_VDBOX_HCP_INTERNAL_BUFFER_INTRA_PRED_LFT_RECON_COL:
1071 {
1072 uint32_t colStoreSizeLCU[2][3]; //[bitdepth 8/10 or 12][LCU 16/32/64]
1073 if (chromaFormat == HCP_CHROMA_FORMAT_YUV420)
1074 {
1075 colStoreSizeLCU[0][0] = 1; colStoreSizeLCU[0][1] = 2; colStoreSizeLCU[0][2] = 2;
1076 colStoreSizeLCU[1][0] = 1; colStoreSizeLCU[1][1] = 2; colStoreSizeLCU[1][2] = 4;
1077 }
1078 else if (chromaFormat == HCP_CHROMA_FORMAT_YUV422)
1079 {
1080 colStoreSizeLCU[0][0] = 1; colStoreSizeLCU[0][1] = 2; colStoreSizeLCU[0][2] = 3;
1081 colStoreSizeLCU[1][0] = 2; colStoreSizeLCU[1][1] = 3; colStoreSizeLCU[1][2] = 6;
1082 }
1083 else
1084 {
1085 colStoreSizeLCU[0][0] = 1; colStoreSizeLCU[0][1] = 2; colStoreSizeLCU[0][2] = 3;
1086 colStoreSizeLCU[1][0] = 2; colStoreSizeLCU[1][1] = 3; colStoreSizeLCU[1][2] = 6;
1087 }
1088 colStoreSzLCU = colStoreSizeLCU[(maxBitDepth == 8) ? 0 : 1][hcpBufSizeParam->dwCtbLog2SizeY > 3 ? hcpBufSizeParam->dwCtbLog2SizeY - 4 : 0];
1089 bufferSize = colStoreSzLCU * MHW_CACHELINE_SIZE * heightInCtb;
1090 break;
1091 }
1092 case MHW_VDBOX_HCP_INTERNAL_BUFFER_SAO_LINE:
1093 {
1094 uint32_t uiRowStoreSizeLCU[2][3];//[bitdepth 8 or10/12][LCU 16/32/64]
1095 if (chromaFormat == HCP_CHROMA_FORMAT_YUV420 || chromaFormat == HCP_CHROMA_FORMAT_YUV422)
1096 {
1097 uiRowStoreSizeLCU[0][0] = 2; uiRowStoreSizeLCU[0][1] = 3; uiRowStoreSizeLCU[0][2] = 5;
1098 uiRowStoreSizeLCU[1][0] = 2; uiRowStoreSizeLCU[1][1] = 4; uiRowStoreSizeLCU[1][2] = 6;
1099 }
1100 else
1101 {
1102 uiRowStoreSizeLCU[0][0] = 3; uiRowStoreSizeLCU[0][1] = 4; uiRowStoreSizeLCU[0][2] = 7;
1103 uiRowStoreSizeLCU[1][0] = 3; uiRowStoreSizeLCU[1][1] = 5; uiRowStoreSizeLCU[1][2] = 8;
1104 }
1105 rowStoreSzLCU = uiRowStoreSizeLCU[(maxBitDepth < 12) ? 0 : 1][hcpBufSizeParam->dwCtbLog2SizeY > 3 ? hcpBufSizeParam->dwCtbLog2SizeY - 4 : 0];
1106 bufferSize = rowStoreSzLCU * MHW_CACHELINE_SIZE * widthInCtb;
1107 break;
1108 }
1109 case MHW_VDBOX_HCP_INTERNAL_BUFFER_SAO_TILE_LINE:
1110 {
1111 uint32_t uiRowStoreSizeLCU[2][3];//[bitdepth 8 or 10/12][LCU 16/32/64]
1112 if (chromaFormat == HCP_CHROMA_FORMAT_YUV420 || chromaFormat == HCP_CHROMA_FORMAT_YUV422)
1113 {
1114 uiRowStoreSizeLCU[0][0] = 4; uiRowStoreSizeLCU[0][1] = 6; uiRowStoreSizeLCU[0][2] = 10;
1115 uiRowStoreSizeLCU[1][0] = 4; uiRowStoreSizeLCU[1][1] = 8; uiRowStoreSizeLCU[1][2] = 12;
1116 }
1117 else
1118 {
1119 uiRowStoreSizeLCU[0][0] = 6; uiRowStoreSizeLCU[0][1] = 8; uiRowStoreSizeLCU[0][2] = 14;
1120 uiRowStoreSizeLCU[1][0] = 6; uiRowStoreSizeLCU[1][1] = 10; uiRowStoreSizeLCU[1][2] = 16;
1121 }
1122 rowStoreSzLCU = uiRowStoreSizeLCU[(maxBitDepth < 12) ? 0 : 1][hcpBufSizeParam->dwCtbLog2SizeY > 3 ? hcpBufSizeParam->dwCtbLog2SizeY - 4 : 0];
1123 bufferSize = rowStoreSzLCU * MHW_CACHELINE_SIZE * widthInCtb;
1124 break;
1125 }
1126 case MHW_VDBOX_HCP_INTERNAL_BUFFER_SAO_TILE_COL:
1127 {
1128 // [chroma_format_idc][lcu_size] = [420/422/444][lcu16/lcu32/lcu64]
1129 uint32_t formatMultFactorTab[3][3] = { { 8,10,18 },{ 10,14,24 },{ 10,14,24 } };
1130 uint32_t formatMultFactor;
1131
1132 if (chromaFormat == HCP_CHROMA_FORMAT_MONOCHROME)
1133 {
1134 eStatus = MOS_STATUS_INVALID_PARAMETER;
1135 MHW_ASSERTMESSAGE("invalid input chroma format.\n");
1136 return eStatus;
1137 }
1138
1139 formatMultFactor = formatMultFactorTab[chromaFormat - 1][hcpBufSizeParam->dwCtbLog2SizeY > 3 ? hcpBufSizeParam->dwCtbLog2SizeY - 4 : 0];
1140 colStoreSzLCU = formatMultFactor;
1141 bufferSize = colStoreSzLCU * MHW_CACHELINE_SIZE * heightInCtb;
1142 break;
1143 }
1144 case MHW_VDBOX_HCP_INTERNAL_BUFFER_HSAO_RS:
1145 {
1146 uint32_t maxTileColumn = MOS_ROUNDUP_DIVIDE(hcpBufSizeParam->dwPicWidth, 128);
1147 bufferSize = MOS_ALIGN_CEIL(widthInCtb + 3 * maxTileColumn, 4) * 16;
1148 break;
1149 }
1150 //Add HSSE here
1151 case MHW_VDBOX_HCP_INTERNAL_BUFFER_CURR_MV_TEMPORAL:
1152 mvtSize = ((((hcpBufSizeParam->dwPicWidth + 63) >> 6) * (((hcpBufSizeParam->dwPicHeight + 15) >> 4)) + 1)&(-2));
1153 mvtbSize = ((((hcpBufSizeParam->dwPicWidth + 31) >> 5) * (((hcpBufSizeParam->dwPicHeight + 31) >> 5)) + 1)&(-2));
1154 bufferSize = MOS_MAX(mvtSize, mvtbSize) * MHW_CACHELINE_SIZE;
1155 break;
1156 case MHW_VDBOX_HCP_INTERNAL_BUFFER_CABAC_STREAMOUT:
1157 //From sas, cabac stream out buffer size =
1158 //(#LCU) in picture * (Worst case LCU_CU_TU_info) + 1 byte aligned per LCU + Bitstream Size * 3
1159 if ((chromaFormat == HCP_CHROMA_FORMAT_YUV420) && (maxBitDepth == 8))
1160 {
1161 bufferSize = widthInCtb * heightInCtb * MHW_HCP_WORST_CASE_CU_TU_INFO
1162 + widthInCtb * heightInCtb
1163 + maxFrameSize * 3;
1164 }
1165 else
1166 {
1167 bufferSize = widthInCtb * heightInCtb * MHW_HCP_WORST_CASE_CU_TU_INFO_REXT
1168 + widthInCtb * heightInCtb
1169 + maxFrameSize * 3;
1170 }
1171 bufferSize = MOS_ALIGN_CEIL(bufferSize, MHW_CACHELINE_SIZE);
1172 break;
1173 default:
1174 eStatus = MOS_STATUS_INVALID_PARAMETER;
1175 break;
1176 }
1177
1178 hcpBufSizeParam->dwBufferSize = bufferSize;
1179
1180 return eStatus;
1181 }
1182
GetVp9BufferSize(MHW_VDBOX_HCP_INTERNAL_BUFFER_TYPE bufferType,PMHW_VDBOX_HCP_BUFFER_SIZE_PARAMS hcpBufSizeParam)1183 MOS_STATUS MhwVdboxHcpInterfaceG12::GetVp9BufferSize(
1184 MHW_VDBOX_HCP_INTERNAL_BUFFER_TYPE bufferType,
1185 PMHW_VDBOX_HCP_BUFFER_SIZE_PARAMS hcpBufSizeParam)
1186 {
1187 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1188
1189 MHW_FUNCTION_ENTER;
1190
1191 MHW_MI_CHK_NULL(hcpBufSizeParam);
1192
1193 uint32_t bufferSize = 0;
1194 uint32_t dblkRsbSizeMultiplier = 0;
1195 uint32_t dblkCsbSizeMultiplier = 0;
1196 uint32_t intraPredMultiplier = 0;
1197
1198 uint8_t maxBitDepth = hcpBufSizeParam->ucMaxBitDepth;
1199 uint32_t widthInSb = hcpBufSizeParam->dwPicWidth;
1200 uint32_t heightInSb = hcpBufSizeParam->dwPicHeight;
1201 uint32_t widthInMinCb = widthInSb * 64 / 8; //using smallest cb to get max width
1202 uint32_t heightInMinCb = heightInSb * 64 / 8;
1203 HCP_CHROMA_FORMAT_IDC chromaFormat = (HCP_CHROMA_FORMAT_IDC)hcpBufSizeParam->ucChromaFormat;
1204 uint32_t maxFrameSize = hcpBufSizeParam->dwMaxFrameSize;
1205
1206 if (chromaFormat == HCP_CHROMA_FORMAT_YUV420)
1207 {
1208 dblkRsbSizeMultiplier = (maxBitDepth > 8) ? 36 : 18;
1209 dblkCsbSizeMultiplier = (maxBitDepth > 8) ? 34 : 17;
1210 intraPredMultiplier = (maxBitDepth > 8) ? 4 : 2;
1211 }
1212 else if (chromaFormat == HCP_CHROMA_FORMAT_YUV444)
1213 {
1214 dblkRsbSizeMultiplier = (maxBitDepth > 8) ? 54 : 27;
1215 dblkCsbSizeMultiplier = (maxBitDepth > 8) ? 50 : 25;
1216 intraPredMultiplier = (maxBitDepth > 8) ? 6 : 3;
1217 }
1218 else
1219 {
1220 eStatus = MOS_STATUS_INVALID_PARAMETER;
1221 MHW_ASSERTMESSAGE("Format not supported.");
1222 return eStatus;
1223 }
1224
1225 switch (bufferType)
1226 {
1227 case MHW_VDBOX_HCP_INTERNAL_BUFFER_DBLK_LINE:
1228 case MHW_VDBOX_HCP_INTERNAL_BUFFER_DBLK_TILE_LINE:
1229 bufferSize = widthInSb * dblkRsbSizeMultiplier * MHW_CACHELINE_SIZE;
1230 break;
1231 case MHW_VDBOX_HCP_INTERNAL_BUFFER_DBLK_TILE_COL:
1232 bufferSize = heightInSb * dblkCsbSizeMultiplier * MHW_CACHELINE_SIZE;
1233 break;
1234 case MHW_VDBOX_HCP_INTERNAL_BUFFER_META_LINE:
1235 case MHW_VDBOX_HCP_INTERNAL_BUFFER_META_TILE_LINE:
1236 bufferSize = widthInSb * 5 * MHW_CACHELINE_SIZE;
1237 break;
1238 case MHW_VDBOX_HCP_INTERNAL_BUFFER_META_TILE_COL:
1239 bufferSize = heightInSb * 5 * MHW_CACHELINE_SIZE;
1240 break;
1241 case MHW_VDBOX_HCP_INTERNAL_BUFFER_CURR_MV_TEMPORAL:
1242 case MHW_VDBOX_HCP_INTERNAL_BUFFER_COLL_MV_TEMPORAL:
1243 bufferSize = widthInSb * heightInSb * 9 * MHW_CACHELINE_SIZE;
1244 break;
1245 case MHW_VDBOX_VP9_INTERNAL_BUFFER_SEGMENT_ID:
1246 bufferSize = widthInSb * heightInSb * MHW_CACHELINE_SIZE;
1247 break;
1248 case MHW_VDBOX_VP9_INTERNAL_BUFFER_HVD_LINE:
1249 case MHW_VDBOX_VP9_INTERNAL_BUFFER_HVD_TILE:
1250 bufferSize = widthInSb * MHW_CACHELINE_SIZE;
1251 break;
1252 //scalable mode specific buffers
1253 case MHW_VDBOX_HCP_INTERNAL_BUFFER_INTRA_PRED_UP_RIGHT_COL:
1254 case MHW_VDBOX_HCP_INTERNAL_BUFFER_INTRA_PRED_LFT_RECON_COL:
1255 bufferSize = intraPredMultiplier * heightInSb * MHW_CACHELINE_SIZE;
1256 break;
1257 case MHW_VDBOX_HCP_INTERNAL_BUFFER_CABAC_STREAMOUT:
1258 //From sas, cabac stream out buffer size =
1259 //(#LCU) in picture * (Worst case LCU_CU_TU_info) + 1 byte aligned per LCU + Bitstream Size * 3
1260 if ((chromaFormat == HCP_CHROMA_FORMAT_YUV420) && (maxBitDepth == 8))
1261 {
1262 bufferSize = widthInMinCb * heightInMinCb * MHW_HCP_WORST_CASE_CU_TU_INFO
1263 + widthInMinCb * heightInMinCb
1264 + maxFrameSize * 3;
1265 }
1266 else
1267 {
1268 bufferSize = widthInMinCb * heightInMinCb * MHW_HCP_WORST_CASE_CU_TU_INFO_REXT
1269 + widthInMinCb * heightInMinCb
1270 + maxFrameSize * 3;
1271 }
1272 bufferSize = MOS_ALIGN_CEIL(bufferSize, MHW_CACHELINE_SIZE);
1273 break;
1274 default:
1275 eStatus = MOS_STATUS_INVALID_PARAMETER;
1276 break;
1277 }
1278
1279 hcpBufSizeParam->dwBufferSize = bufferSize;
1280
1281 return eStatus;
1282 }
1283
IsHevcBufferReallocNeeded(MHW_VDBOX_HCP_INTERNAL_BUFFER_TYPE bufferType,PMHW_VDBOX_HCP_BUFFER_REALLOC_PARAMS reallocParam)1284 MOS_STATUS MhwVdboxHcpInterfaceG12::IsHevcBufferReallocNeeded(
1285 MHW_VDBOX_HCP_INTERNAL_BUFFER_TYPE bufferType,
1286 PMHW_VDBOX_HCP_BUFFER_REALLOC_PARAMS reallocParam)
1287 {
1288 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1289
1290 MHW_FUNCTION_ENTER;
1291
1292 MHW_MI_CHK_NULL(reallocParam);
1293
1294 bool realloc = false;
1295 uint32_t picWidth = reallocParam->dwPicWidth;
1296 uint32_t picHeight = reallocParam->dwPicHeight;
1297 uint32_t ctbLog2SizeY = reallocParam->dwCtbLog2SizeY;
1298 uint8_t maxBitDepth = reallocParam->ucMaxBitDepth;
1299 HCP_CHROMA_FORMAT_IDC chromaFormat = (HCP_CHROMA_FORMAT_IDC)reallocParam->ucChromaFormat;
1300 uint32_t picWidthAlloced = reallocParam->dwPicWidthAlloced;
1301 uint32_t picHeightAlloced = reallocParam->dwPicHeightAlloced;
1302 uint32_t ctbLog2SizeYMax = reallocParam->dwCtbLog2SizeYMax;
1303 uint32_t frameSize = reallocParam->dwFrameSize;
1304 uint32_t frameSizeAlloced = reallocParam->dwFrameSizeAlloced;
1305
1306 switch (bufferType)
1307 {
1308 case MHW_VDBOX_HCP_INTERNAL_BUFFER_DBLK_LINE:
1309 case MHW_VDBOX_HCP_INTERNAL_BUFFER_DBLK_TILE_LINE:
1310 realloc = (picWidth > picWidthAlloced || ctbLog2SizeY > ctbLog2SizeYMax);
1311 break;
1312 case MHW_VDBOX_HCP_INTERNAL_BUFFER_DBLK_TILE_COL:
1313 realloc = (picHeight > picHeightAlloced || ctbLog2SizeY > ctbLog2SizeYMax);
1314 break;
1315 case MHW_VDBOX_HCP_INTERNAL_BUFFER_META_LINE:
1316 case MHW_VDBOX_HCP_INTERNAL_BUFFER_META_TILE_LINE:
1317 if ((ctbLog2SizeYMax < 6 && ctbLog2SizeY == 6) || (picWidth > picWidthAlloced))
1318 {
1319 realloc = true;
1320 }
1321 break;
1322 case MHW_VDBOX_HCP_INTERNAL_BUFFER_MV_UP_RT_COL:
1323 case MHW_VDBOX_HCP_INTERNAL_BUFFER_META_TILE_COL:
1324 if ((ctbLog2SizeYMax < 6 && ctbLog2SizeY == 6) || (picHeight > picHeightAlloced))
1325 {
1326 realloc = true;
1327 }
1328 break;
1329 case MHW_VDBOX_HCP_INTERNAL_BUFFER_INTRA_PRED_UP_RIGHT_COL:
1330 case MHW_VDBOX_HCP_INTERNAL_BUFFER_INTRA_PRED_LFT_RECON_COL:
1331 if (maxBitDepth == 8 && chromaFormat == HCP_CHROMA_FORMAT_YUV420)
1332 {
1333 realloc = ((ctbLog2SizeYMax < 6 && ctbLog2SizeY == 6) || (picHeight > picHeightAlloced));
1334 }
1335 else
1336 {
1337 realloc = (picHeight > picHeightAlloced || ctbLog2SizeY > ctbLog2SizeYMax);
1338 }
1339 break;
1340 case MHW_VDBOX_HCP_INTERNAL_BUFFER_SAO_LINE:
1341 case MHW_VDBOX_HCP_INTERNAL_BUFFER_SAO_TILE_LINE:
1342 realloc = (picWidth > picWidthAlloced || ctbLog2SizeY > ctbLog2SizeYMax);
1343 break;
1344 case MHW_VDBOX_HCP_INTERNAL_BUFFER_SAO_TILE_COL:
1345 realloc = (picHeight > picHeightAlloced || ctbLog2SizeY > ctbLog2SizeYMax);
1346 break;
1347 case MHW_VDBOX_HCP_INTERNAL_BUFFER_CURR_MV_TEMPORAL:
1348 realloc = (picWidth > picWidthAlloced || picHeight > picHeightAlloced);
1349 break;
1350 case MHW_VDBOX_HCP_INTERNAL_BUFFER_CABAC_STREAMOUT:
1351 realloc = (frameSize > frameSizeAlloced);
1352 break;
1353 default:
1354 eStatus = MOS_STATUS_INVALID_PARAMETER;
1355 break;
1356 }
1357
1358 reallocParam->bNeedBiggerSize = realloc;
1359
1360 return eStatus;
1361 }
1362
IsVp9BufferReallocNeeded(MHW_VDBOX_HCP_INTERNAL_BUFFER_TYPE bufferType,PMHW_VDBOX_HCP_BUFFER_REALLOC_PARAMS reallocParam)1363 MOS_STATUS MhwVdboxHcpInterfaceG12::IsVp9BufferReallocNeeded(
1364 MHW_VDBOX_HCP_INTERNAL_BUFFER_TYPE bufferType,
1365 PMHW_VDBOX_HCP_BUFFER_REALLOC_PARAMS reallocParam)
1366 {
1367 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1368
1369 MHW_FUNCTION_ENTER;
1370
1371 uint32_t widthInSb, heightInSb, picWidthInSbAlloced, picHeightInSbAlloced;
1372 uint32_t frameSize, frameSizeAlloced;
1373 bool realloc = false;
1374
1375 MHW_MI_CHK_NULL(reallocParam);
1376
1377 widthInSb = reallocParam->dwPicWidth;
1378 heightInSb = reallocParam->dwPicHeight;
1379 picWidthInSbAlloced = reallocParam->dwPicWidthAlloced;
1380 picHeightInSbAlloced = reallocParam->dwPicHeightAlloced;
1381 frameSize = reallocParam->dwFrameSize;
1382 frameSizeAlloced = reallocParam->dwFrameSizeAlloced;
1383
1384 switch (bufferType)
1385 {
1386 case MHW_VDBOX_HCP_INTERNAL_BUFFER_META_LINE:
1387 case MHW_VDBOX_HCP_INTERNAL_BUFFER_META_TILE_LINE:
1388 case MHW_VDBOX_HCP_INTERNAL_BUFFER_DBLK_LINE:
1389 case MHW_VDBOX_HCP_INTERNAL_BUFFER_DBLK_TILE_LINE:
1390 case MHW_VDBOX_VP9_INTERNAL_BUFFER_HVD_LINE:
1391 case MHW_VDBOX_VP9_INTERNAL_BUFFER_HVD_TILE:
1392 realloc = (widthInSb > picWidthInSbAlloced);
1393 break;
1394 case MHW_VDBOX_HCP_INTERNAL_BUFFER_DBLK_TILE_COL:
1395 case MHW_VDBOX_HCP_INTERNAL_BUFFER_META_TILE_COL:
1396 case MHW_VDBOX_HCP_INTERNAL_BUFFER_INTRA_PRED_UP_RIGHT_COL:
1397 case MHW_VDBOX_HCP_INTERNAL_BUFFER_INTRA_PRED_LFT_RECON_COL:
1398 realloc = (heightInSb > picHeightInSbAlloced);
1399 break;
1400 case MHW_VDBOX_HCP_INTERNAL_BUFFER_CURR_MV_TEMPORAL:
1401 case MHW_VDBOX_HCP_INTERNAL_BUFFER_COLL_MV_TEMPORAL:
1402 case MHW_VDBOX_VP9_INTERNAL_BUFFER_SEGMENT_ID:
1403 realloc = (heightInSb > picHeightInSbAlloced || widthInSb > picWidthInSbAlloced);
1404 break;
1405 case MHW_VDBOX_HCP_INTERNAL_BUFFER_CABAC_STREAMOUT:
1406 realloc = (frameSize > frameSizeAlloced);
1407 break;
1408 default:
1409 eStatus = MOS_STATUS_INVALID_PARAMETER;
1410 break;
1411 }
1412
1413 reallocParam->bNeedBiggerSize = realloc;
1414
1415 return eStatus;
1416 }
1417
AddHcpPipeModeSelectCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VDBOX_PIPE_MODE_SELECT_PARAMS params)1418 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpPipeModeSelectCmd(
1419 PMOS_COMMAND_BUFFER cmdBuffer,
1420 PMHW_VDBOX_PIPE_MODE_SELECT_PARAMS params)
1421 {
1422 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1423 bool bTwoPassScalableEncode = false;
1424
1425 MHW_FUNCTION_ENTER;
1426
1427 MHW_MI_CHK_NULL(params);
1428 auto paramsG12 = dynamic_cast<PMHW_VDBOX_PIPE_MODE_SELECT_PARAMS_G12>(params);
1429 MHW_MI_CHK_NULL(paramsG12);
1430 mhw_vdbox_hcp_g12_X::HCP_PIPE_MODE_SELECT_CMD cmd;
1431
1432 // for Gen11+, we need to add MFX wait for both KIN and VRT before and after HCP Pipemode select...
1433 MHW_MI_CHK_STATUS(m_miInterface->AddMfxWaitCmd(cmdBuffer, nullptr, true));
1434
1435 // Secure scalable encode workloads requires special handling for Gen12
1436 bTwoPassScalableEncode = paramsG12->MultiEngineMode != MHW_VDBOX_HCP_MULTI_ENGINE_MODE_FE_LEGACY && !m_decodeInUse && !paramsG12->bTileBasedReplayMode;
1437 MHW_MI_CHK_STATUS(m_cpInterface->SetProtectionSettingsForHcpPipeModeSelect((uint32_t *)&cmd, bTwoPassScalableEncode));
1438
1439 cmd.DW1.AdvancedRateControlEnable = params->bAdvancedRateControlEnable;
1440 cmd.DW1.CodecStandardSelect = CodecHal_GetStandardFromMode(params->Mode) - CODECHAL_HCP_BASE;
1441 cmd.DW1.PakPipelineStreamoutEnable = params->bStreamOutEnabled || paramsG12->bBRCEnabled || params->pakPiplnStrmoutEnabled;
1442 cmd.DW1.DeblockerStreamoutEnable = params->bDeblockerStreamOutEnable;
1443 cmd.DW1.VdencMode = params->bVdencEnabled;
1444 cmd.DW1.RdoqEnabledFlag = params->bRdoqEnable;
1445 cmd.DW1.PakFrameLevelStreamoutEnable = params->bStreamOutEnabled || params->pakFrmLvlStrmoutEnable;
1446 cmd.DW1.PipeWorkingMode = paramsG12->PipeWorkMode;
1447 cmd.DW1.MultiEngineMode = paramsG12->MultiEngineMode;
1448 cmd.DW1.TileBasedEngine = paramsG12->bTileBasedReplayMode;
1449 cmd.DW1.Vp9DynamicScalingEnable = params->bDynamicScalingEnabled;
1450 cmd.DW6.PhaseIndicator = paramsG12->ucPhaseIndicator;
1451 cmd.DW6.HevcSeparateTileProgramming = paramsG12->bHEVCSeparateTileProgramming;
1452
1453 if (m_decodeInUse)
1454 {
1455 cmd.DW1.CodecSelect = cmd.CODEC_SELECT_DECODE;
1456 // Disable it by default. Re-enable it after validation is done
1457 cmd.DW2.MediaSoftResetCounterPer1000Clocks = cmd.MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS_DISABLE;
1458 #if (_DEBUG || _RELEASE_INTERNAL)
1459 if (m_osInterface->bSoftReset)
1460 {
1461 cmd.DW2.MediaSoftResetCounterPer1000Clocks = 500;
1462 }
1463 else
1464 {
1465 cmd.DW2.MediaSoftResetCounterPer1000Clocks = cmd.MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS_DISABLE;
1466 }
1467 #endif
1468 }
1469 else
1470 {
1471 cmd.DW1.CodecSelect = cmd.CODEC_SELECT_ENCODE;
1472 }
1473
1474 if (m_disableTlbPrefetch)
1475 {
1476 cmd.DW1.PrefetchDisable = 1;
1477 }
1478
1479 MHW_MI_CHK_STATUS(Mhw_AddCommandCmdOrBB(m_osInterface, cmdBuffer, params->pBatchBuffer, &cmd, sizeof(cmd)));
1480
1481 // for Gen11+, we need to add MFX wait for both KIN and VRT before and after HCP Pipemode select...
1482 MHW_MI_CHK_STATUS(m_miInterface->AddMfxWaitCmd(cmdBuffer, nullptr, true));
1483
1484 return eStatus;
1485 }
1486
AddHcpDecodeSurfaceStateCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VDBOX_SURFACE_PARAMS params)1487 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpDecodeSurfaceStateCmd(
1488 PMOS_COMMAND_BUFFER cmdBuffer,
1489 PMHW_VDBOX_SURFACE_PARAMS params)
1490 {
1491 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1492 uint32_t uvPlaneAlignment = m_uvPlaneAlignmentLegacy;
1493
1494 MHW_MI_CHK_NULL(params);
1495
1496 mhw_vdbox_hcp_g12_X::HCP_SURFACE_STATE_CMD *cmd =
1497 (mhw_vdbox_hcp_g12_X::HCP_SURFACE_STATE_CMD*)cmdBuffer->pCmdPtr;
1498
1499 MHW_MI_CHK_STATUS(MhwVdboxHcpInterfaceGeneric<mhw_vdbox_hcp_g12_X>::AddHcpDecodeSurfaceStateCmd(cmdBuffer, params));
1500
1501 if (params->ucBitDepthLumaMinus8 == 0 && params->ucBitDepthChromaMinus8 == 0)
1502 {
1503 if (params->ChromaType == HCP_CHROMA_FORMAT_YUV420 && params->psSurface->Format == Format_NV12)// 4:2:0 8bit surface
1504 {
1505 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_PLANAR4208;
1506 }
1507 else if (params->ChromaType == HCP_CHROMA_FORMAT_YUV420 && params->psSurface->Format == Format_P010)// 4:2:0 10bit surface
1508 {
1509 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_P010;
1510 }
1511 else if (params->ChromaType == HCP_CHROMA_FORMAT_YUV422 && params->psSurface->Format == Format_YUY2) // 4:2:2 8bit surface
1512 {
1513 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_YUY2FORMAT;
1514 }
1515 else if (params->ChromaType == HCP_CHROMA_FORMAT_YUV422 && params->psSurface->Format == Format_Y210) // 4:2:2 10bit surface
1516 {
1517 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_Y216Y210FORMAT;
1518 }
1519 else if (params->ChromaType == HCP_CHROMA_FORMAT_YUV444 && params->psSurface->Format == Format_AYUV) // 4:4:4 8bit surface
1520 {
1521 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_AYUV4444FORMAT;
1522 }
1523 else if (params->ChromaType == HCP_CHROMA_FORMAT_YUV444 && params->psSurface->Format == Format_Y410) // 4:4:4 10bit surface
1524 {
1525 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_Y410FORMAT;
1526 }
1527 else if (params->ChromaType == HCP_CHROMA_FORMAT_YUV420 && params->psSurface->Format == Format_P016) // 4:2:0 16bit surface
1528 {
1529 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_P016;
1530 }
1531 else if (params->ChromaType == HCP_CHROMA_FORMAT_YUV422 && params->psSurface->Format == Format_Y216) // 4:2:2 16bit surface
1532 {
1533 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_Y216Y210FORMAT;
1534 }
1535 else if (params->ChromaType == HCP_CHROMA_FORMAT_YUV444 && params->psSurface->Format == Format_Y416) // 4:4:4
1536 {
1537 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_Y416FORMAT;
1538 }
1539 else
1540 {
1541 return MOS_STATUS_INVALID_PARAMETER;
1542 }
1543 }
1544 else if ((params->ucBitDepthLumaMinus8 <= 2) && (params->ucBitDepthChromaMinus8 <= 2)) // only support bitdepth <= 10bit
1545 {
1546 if (params->ChromaType == HCP_CHROMA_FORMAT_YUV420 && params->psSurface->Format == Format_P010)// 4:2:0
1547 {
1548 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_P010;
1549 }
1550 else if (params->ChromaType == HCP_CHROMA_FORMAT_YUV420 && params->psSurface->Format == Format_P016) // 4:2:0
1551 {
1552 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_P016;
1553 }
1554 else if (params->ChromaType == HCP_CHROMA_FORMAT_YUV422 && params->psSurface->Format == Format_Y210) // 4:2:2
1555 {
1556 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_Y216Y210FORMAT;
1557 }
1558 else if (params->ChromaType == HCP_CHROMA_FORMAT_YUV422 && params->psSurface->Format == Format_Y216) // 4:2:2
1559 {
1560 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_Y216Y210FORMAT;
1561 }
1562 else if (params->ChromaType == HCP_CHROMA_FORMAT_YUV444 && params->psSurface->Format == Format_Y410) // 4:4:4
1563 {
1564 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_Y410FORMAT;
1565 }
1566 else if (params->ChromaType == HCP_CHROMA_FORMAT_YUV444 && params->psSurface->Format == Format_Y416) // 4:4:4
1567 {
1568 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_Y416FORMAT;
1569 }
1570 else
1571 {
1572 return MOS_STATUS_INVALID_PARAMETER;
1573 }
1574 }
1575 else //12bit
1576 {
1577 if (params->ChromaType == HCP_CHROMA_FORMAT_YUV420 && params->psSurface->Format == Format_P016) // 4:2:0
1578 {
1579 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_P016;
1580 }
1581 else if (params->ChromaType == HCP_CHROMA_FORMAT_YUV422 && params->psSurface->Format == Format_Y216) // 4:2:2
1582 {
1583 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_Y216Y210FORMAT;
1584 }
1585 else if (params->ChromaType == HCP_CHROMA_FORMAT_YUV444 && params->psSurface->Format == Format_Y416) // 4:4:4
1586 {
1587 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_Y416FORMAT;
1588 }
1589 else
1590 {
1591 return MOS_STATUS_INVALID_PARAMETER;
1592 }
1593 }
1594
1595 if (params->ucSurfaceStateId == CODECHAL_HCP_SRC_SURFACE_ID)
1596 {
1597 uvPlaneAlignment = params->dwUVPlaneAlignment ? params->dwUVPlaneAlignment : m_rawUVPlaneAlignment;
1598 }
1599 else
1600 {
1601 uvPlaneAlignment = params->dwUVPlaneAlignment ? params->dwUVPlaneAlignment : m_reconUVPlaneAlignment;
1602 }
1603
1604 cmd->DW2.YOffsetForUCbInPixel =
1605 MOS_ALIGN_CEIL((params->psSurface->UPlaneOffset.iSurfaceOffset - params->psSurface->dwOffset) / params->psSurface->dwPitch + params->psSurface->RenderOffset.YUV.U.YOffset, uvPlaneAlignment);
1606
1607 if ((params->ucBitDepthLumaMinus8 == 4) || (params->ucBitDepthChromaMinus8 == 4)) // 12 bit
1608 cmd->DW3.DefaultAlphaValue = 0xfff0;
1609 else
1610 cmd->DW3.DefaultAlphaValue = 0xffff;
1611
1612 if (params->ucSurfaceStateId != CODECHAL_HCP_DECODED_SURFACE_ID) //MMC is not need in HCP_SURFACE_STATE for non reference surfaces
1613 {
1614 cmd->DW4.MemoryCompressionEnable = MmcEnable(params->mmcState) ? ((~params->mmcSkipMask) & 0xff) : 0;
1615 cmd->DW4.CompressionType = MmcIsRc(params->mmcState) ? 0xff : 0;
1616 }
1617
1618 return eStatus;
1619 }
1620
AddHcpEncodeSurfaceStateCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VDBOX_SURFACE_PARAMS params)1621 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpEncodeSurfaceStateCmd(
1622 PMOS_COMMAND_BUFFER cmdBuffer,
1623 PMHW_VDBOX_SURFACE_PARAMS params)
1624 {
1625 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1626
1627 MHW_MI_CHK_NULL(params);
1628
1629 mhw_vdbox_hcp_g12_X::HCP_SURFACE_STATE_CMD *cmd =
1630 (mhw_vdbox_hcp_g12_X::HCP_SURFACE_STATE_CMD*)cmdBuffer->pCmdPtr;
1631
1632 MHW_MI_CHK_STATUS(MhwVdboxHcpInterfaceGeneric<mhw_vdbox_hcp_g12_X>::AddHcpEncodeSurfaceStateCmd(cmdBuffer, params));
1633
1634 bool surf10bit = (params->psSurface->Format == Format_P010) ||
1635 (params->psSurface->Format == Format_P210) ||
1636 (params->psSurface->Format == Format_Y210) ||
1637 (params->psSurface->Format == Format_Y410) ||
1638 (params->psSurface->Format == Format_R10G10B10A2) ||
1639 (params->psSurface->Format == Format_B10G10R10A2) ||
1640 (params->psSurface->Format == Format_P016) ||
1641 (params->psSurface->Format == Format_Y216);
1642
1643 if (params->ChromaType == HCP_CHROMA_FORMAT_YUV422)
1644 {
1645 if (params->ucBitDepthLumaMinus8 > 0)
1646 {
1647 if (params->ucSurfaceStateId == CODECHAL_HCP_SRC_SURFACE_ID)
1648 {
1649 cmd->DW2.SurfaceFormat = surf10bit ?
1650 cmd->SURFACE_FORMAT_Y216Y210FORMAT : cmd->SURFACE_FORMAT_YUY2FORMAT;
1651 }
1652 else
1653 {
1654 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_Y216VARIANT;
1655 }
1656 }
1657 else
1658 {
1659 cmd->DW2.SurfaceFormat = (params->ucSurfaceStateId == CODECHAL_HCP_SRC_SURFACE_ID) ?
1660 cmd->SURFACE_FORMAT_YUY2FORMAT : cmd->SURFACE_FORMAT_YUY2VARIANT;
1661 }
1662 }
1663 else if (params->ChromaType == HCP_CHROMA_FORMAT_YUV444)
1664 {
1665 if (params->ucBitDepthLumaMinus8 == 0)
1666 {
1667 cmd->DW2.SurfaceFormat = params->ucSurfaceStateId == CODECHAL_HCP_SRC_SURFACE_ID ?
1668 cmd->SURFACE_FORMAT_AYUV4444FORMAT : cmd->SURFACE_FORMAT_AYUV4444VARIANT;
1669 }
1670 else if (params->ucBitDepthLumaMinus8 <= 2)
1671 {
1672 if (params->ucSurfaceStateId == CODECHAL_HCP_SRC_SURFACE_ID)
1673 {
1674 cmd->DW2.SurfaceFormat = surf10bit ?
1675 cmd->SURFACE_FORMAT_Y410FORMAT : cmd->SURFACE_FORMAT_AYUV4444FORMAT;
1676 }
1677 else
1678 {
1679 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_Y416VARIANT;
1680 }
1681 }
1682 else
1683 {
1684 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_Y416FORMAT;
1685 }
1686 }
1687 else //params->ChromaType == HCP_CHROMA_FORMAT_YUV420
1688 {
1689 if (params->ucBitDepthLumaMinus8 > 0)
1690 {
1691 if (params->ucSurfaceStateId == CODECHAL_HCP_SRC_SURFACE_ID)
1692 {
1693 cmd->DW2.SurfaceFormat = surf10bit ?
1694 cmd->SURFACE_FORMAT_P010 : cmd->SURFACE_FORMAT_PLANAR4208;
1695 }
1696 else
1697 {
1698 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_P010VARIANT;
1699 }
1700 }
1701 else
1702 {
1703 cmd->DW2.SurfaceFormat = cmd->SURFACE_FORMAT_PLANAR4208;
1704 }
1705 }
1706
1707 cmd->DW2.YOffsetForUCbInPixel = cmd->DW3.YOffsetForVCr =
1708 (params->psSurface->UPlaneOffset.iSurfaceOffset - params->psSurface->dwOffset)/params->psSurface->dwPitch + params->psSurface->RenderOffset.YUV.U.YOffset;
1709
1710 //Set U/V offsets for Variant surfaces
1711 if (cmd->DW2.SurfaceFormat == cmd->SURFACE_FORMAT_Y416VARIANT ||
1712 cmd->DW2.SurfaceFormat == cmd->SURFACE_FORMAT_AYUV4444VARIANT)
1713 {
1714 cmd->DW2.YOffsetForUCbInPixel = params->dwReconSurfHeight;
1715 cmd->DW3.YOffsetForVCr = params->dwReconSurfHeight << 1;
1716 }
1717 else if (cmd->DW2.SurfaceFormat == cmd->SURFACE_FORMAT_Y216VARIANT ||
1718 cmd->DW2.SurfaceFormat == cmd->SURFACE_FORMAT_YUY2VARIANT)
1719 {
1720 cmd->DW2.YOffsetForUCbInPixel =
1721 cmd->DW3.YOffsetForVCr = params->dwReconSurfHeight;
1722 }
1723
1724 if (params->ucSurfaceStateId == CODECHAL_HCP_REF_SURFACE_ID && params->Mode == CODECHAL_ENCODE_MODE_HEVC)
1725 {
1726 cmd->DW4.MemoryCompressionEnable = params->refsMmcEnable ? ((~params->mmcSkipMask) & 0xff) : 0;
1727 cmd->DW4.CompressionType = params->refsMmcType;
1728 }
1729 else
1730 {
1731 cmd->DW4.MemoryCompressionEnable = MmcEnable(params->mmcState) ? ((~params->mmcSkipMask) & 0xff) : 0;
1732 cmd->DW4.CompressionType = MmcIsRc(params->mmcState) ? 0xff : 0;
1733 }
1734
1735 return eStatus;
1736 }
1737
AddHcpPipeBufAddrCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS params)1738 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpPipeBufAddrCmd(
1739 PMOS_COMMAND_BUFFER cmdBuffer,
1740 PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS params)
1741 {
1742 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1743
1744 MHW_FUNCTION_ENTER;
1745
1746 MHW_MI_CHK_NULL(m_osInterface);
1747 MHW_MI_CHK_NULL(cmdBuffer);
1748 MHW_MI_CHK_NULL(params);
1749
1750 MHW_RESOURCE_PARAMS resourceParams;
1751 MOS_SURFACE details;
1752 mhw_vdbox_hcp_g12_X::HCP_PIPE_BUF_ADDR_STATE_CMD cmd;
1753
1754 MOS_ZeroMemory(&resourceParams, sizeof(resourceParams));
1755
1756 // 1. MHW_VDBOX_HCP_GENERAL_STATE_SHIFT(6) may not work with DecodedPicture
1757 // since it needs to be 4k aligned
1758 resourceParams.dwLsbNum = MHW_VDBOX_HCP_GENERAL_STATE_SHIFT;
1759 resourceParams.HwCommandType = MOS_MFX_PIPE_BUF_ADDR;
1760
1761 //Decoded Picture
1762 cmd.DecodedPictureMemoryAddressAttributes.DW0.Value |= m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_PRE_DEBLOCKING_CODEC].Value;
1763 cmd.DecodedPictureMemoryAddressAttributes.DW0.BaseAddressMemoryCompressionEnable = MmcEnable(params->PreDeblockSurfMmcState) ? 1 : 0;
1764 cmd.DecodedPictureMemoryAddressAttributes.DW0.CompressionType = MmcIsRc(params->PreDeblockSurfMmcState) ? 1 : 0;
1765
1766 cmd.DecodedPictureMemoryAddressAttributes.DW0.BaseAddressTiledResourceMode = Mhw_ConvertToTRMode(params->psPreDeblockSurface->TileType);
1767
1768 resourceParams.presResource = &(params->psPreDeblockSurface->OsResource);
1769 resourceParams.dwOffset = params->psPreDeblockSurface->dwOffset;
1770 resourceParams.pdwCmd = (cmd.DecodedPicture.DW0_1.Value);
1771 resourceParams.dwLocationInCmd = 1;
1772 resourceParams.bIsWritable = true;
1773
1774 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
1775 m_osInterface,
1776 cmdBuffer,
1777 &resourceParams));
1778
1779 // Deblocking Filter Line Buffer
1780 if (m_hevcDfRowStoreCache.bEnabled)
1781 {
1782 cmd.DeblockingFilterLineBufferMemoryAddressAttributes.DW0.BaseAddressRowStoreScratchBufferCacheSelect = cmd.DeblockingFilterLineBufferMemoryAddressAttributes.BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1;
1783 cmd.DeblockingFilterLineBuffer.DW0_1.Graphicsaddress476 = m_hevcDfRowStoreCache.dwAddress;
1784 }
1785 else if (m_vp9DfRowStoreCache.bEnabled)
1786 {
1787 cmd.DeblockingFilterLineBufferMemoryAddressAttributes.DW0.BaseAddressRowStoreScratchBufferCacheSelect = cmd.DeblockingFilterLineBufferMemoryAddressAttributes.BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1;
1788 cmd.DeblockingFilterLineBuffer.DW0_1.Graphicsaddress476 = m_vp9DfRowStoreCache.dwAddress;
1789 }
1790 else if (params->presMfdDeblockingFilterRowStoreScratchBuffer != nullptr)
1791 {
1792 cmd.DeblockingFilterLineBufferMemoryAddressAttributes.DW0.Value |= m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_DEBLOCKINGFILTER_ROWSTORE_SCRATCH_BUFFER_CODEC].Value;
1793
1794 resourceParams.presResource = params->presMfdDeblockingFilterRowStoreScratchBuffer;
1795 resourceParams.dwOffset = 0;
1796 resourceParams.pdwCmd = (cmd.DeblockingFilterLineBuffer.DW0_1.Value);
1797 resourceParams.dwLocationInCmd = 4;
1798 resourceParams.bIsWritable = true;
1799
1800 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
1801 m_osInterface,
1802 cmdBuffer,
1803 &resourceParams));
1804 }
1805
1806 // Deblocking Filter Tile Line Buffer
1807 if (params->presDeblockingFilterTileRowStoreScratchBuffer != nullptr)
1808 {
1809 cmd.DeblockingFilterTileLineBufferMemoryAddressAttributes.DW0.Value |= m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_DEBLOCKINGFILTER_ROWSTORE_SCRATCH_BUFFER_CODEC].Value;
1810
1811 resourceParams.presResource = params->presDeblockingFilterTileRowStoreScratchBuffer;
1812 resourceParams.dwOffset = 0;
1813 resourceParams.pdwCmd = (cmd.DeblockingFilterTileLineBuffer.DW0_1.Value);
1814 resourceParams.dwLocationInCmd = 7;
1815 resourceParams.bIsWritable = true;
1816
1817 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
1818 m_osInterface,
1819 cmdBuffer,
1820 &resourceParams));
1821 }
1822
1823 // Deblocking Filter Tile Column Buffer
1824 if (params->presDeblockingFilterColumnRowStoreScratchBuffer != nullptr)
1825 {
1826 cmd.DeblockingFilterTileColumnBufferMemoryAddressAttributes.DW0.Value |= m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_DEBLOCKINGFILTER_ROWSTORE_SCRATCH_BUFFER_CODEC].Value;
1827
1828 resourceParams.presResource = params->presDeblockingFilterColumnRowStoreScratchBuffer;
1829 resourceParams.dwOffset = 0;
1830 resourceParams.pdwCmd = (cmd.DeblockingFilterTileColumnBuffer.DW0_1.Value);
1831 resourceParams.dwLocationInCmd = 10;
1832 resourceParams.bIsWritable = true;
1833
1834 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
1835 m_osInterface,
1836 cmdBuffer,
1837 &resourceParams));
1838 }
1839
1840 // Metadata Line Buffer
1841 if (m_hevcDatRowStoreCache.bEnabled)
1842 {
1843 cmd.MetadataLineBufferMemoryAddressAttributes.DW0.BaseAddressRowStoreScratchBufferCacheSelect = cmd.MetadataLineBufferMemoryAddressAttributes.BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1;
1844 cmd.MetadataLineBuffer.DW0_1.Graphicsaddress476 = m_hevcDatRowStoreCache.dwAddress;
1845 }
1846 else if (m_vp9DatRowStoreCache.bEnabled)
1847 {
1848 cmd.MetadataLineBufferMemoryAddressAttributes.DW0.BaseAddressRowStoreScratchBufferCacheSelect = cmd.MetadataLineBufferMemoryAddressAttributes.BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1;
1849 cmd.MetadataLineBuffer.DW0_1.Graphicsaddress476 = m_vp9DatRowStoreCache.dwAddress;
1850 }
1851 else if (params->presMetadataLineBuffer != nullptr)
1852 {
1853 cmd.MetadataLineBufferMemoryAddressAttributes.DW0.Value |= m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_HCP_MD_CODEC].Value;
1854
1855 resourceParams.presResource = params->presMetadataLineBuffer;
1856 resourceParams.dwOffset = 0;
1857 resourceParams.pdwCmd = (cmd.MetadataLineBuffer.DW0_1.Value);
1858 resourceParams.dwLocationInCmd = 13;
1859 resourceParams.bIsWritable = true;
1860
1861 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
1862 m_osInterface,
1863 cmdBuffer,
1864 &resourceParams));
1865 }
1866
1867 // Metadata Tile Line Buffer
1868 if (params->presMetadataTileLineBuffer != nullptr)
1869 {
1870 cmd.MetadataTileLineBufferMemoryAddressAttributes.DW0.Value |= m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_HCP_MD_CODEC].Value;
1871
1872 resourceParams.presResource = params->presMetadataTileLineBuffer;
1873 resourceParams.dwOffset = 0;
1874 resourceParams.pdwCmd = (cmd.MetadataTileLineBuffer.DW0_1.Value);
1875 resourceParams.dwLocationInCmd = 16;
1876 resourceParams.bIsWritable = true;
1877
1878 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
1879 m_osInterface,
1880 cmdBuffer,
1881 &resourceParams));
1882 }
1883
1884 // Metadata Tile Column Buffer
1885 if (params->presMetadataTileColumnBuffer != nullptr)
1886 {
1887 cmd.MetadataTileColumnBufferMemoryAddressAttributes.DW0.Value |= m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_HCP_MD_CODEC].Value;
1888
1889 resourceParams.presResource = params->presMetadataTileColumnBuffer;
1890 resourceParams.dwOffset = 0;
1891 resourceParams.pdwCmd = (cmd.MetadataTileColumnBuffer.DW0_1.Value);
1892 resourceParams.dwLocationInCmd = 19;
1893 resourceParams.bIsWritable = true;
1894
1895 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
1896 m_osInterface,
1897 cmdBuffer,
1898 &resourceParams));
1899 }
1900
1901 // SAO Line Buffer
1902 if (m_hevcSaoRowStoreCache.bEnabled)
1903 {
1904 cmd.SaoLineBufferMemoryAddressAttributes.DW0.BaseAddressRowStoreScratchBufferCacheSelect = cmd.SaoLineBufferMemoryAddressAttributes.BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1;
1905 cmd.SaoLineBuffer.DW0_1.Graphicsaddress476 = m_hevcSaoRowStoreCache.dwAddress;
1906 }
1907 else if (params->presSaoLineBuffer != nullptr)
1908 {
1909 cmd.SaoLineBufferMemoryAddressAttributes.DW0.Value |=
1910 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_HCP_SAO_CODEC].Value;
1911
1912 resourceParams.presResource = params->presSaoLineBuffer;
1913 resourceParams.dwOffset = 0;
1914 resourceParams.pdwCmd = (cmd.SaoLineBuffer.DW0_1.Value);
1915 resourceParams.dwLocationInCmd = 22;
1916 resourceParams.bIsWritable = true;
1917
1918 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
1919 m_osInterface,
1920 cmdBuffer,
1921 &resourceParams));
1922 }
1923
1924 // SAO Tile Line Buffer
1925 if (params->presSaoTileLineBuffer != nullptr)
1926 {
1927 cmd.SaoTileLineBufferMemoryAddressAttributes.DW0.Value |=
1928 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_HCP_SAO_CODEC].Value;
1929
1930 resourceParams.presResource = params->presSaoTileLineBuffer;
1931 resourceParams.dwOffset = 0;
1932 resourceParams.pdwCmd = (cmd.SaoTileLineBuffer.DW0_1.Value);
1933 resourceParams.dwLocationInCmd = 25;
1934 resourceParams.bIsWritable = true;
1935
1936 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
1937 m_osInterface,
1938 cmdBuffer,
1939 &resourceParams));
1940 }
1941
1942 // SAO Tile Column Buffer
1943 if (params->presSaoTileColumnBuffer != nullptr)
1944 {
1945 cmd.SaoTileColumnBufferMemoryAddressAttributes.DW0.Value |=
1946 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_HCP_SAO_CODEC].Value;
1947
1948 resourceParams.presResource = params->presSaoTileColumnBuffer;
1949 resourceParams.dwOffset = 0;
1950 resourceParams.pdwCmd = (cmd.SaoTileColumnBuffer.DW0_1.Value);
1951 resourceParams.dwLocationInCmd = 28;
1952 resourceParams.bIsWritable = true;
1953
1954 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
1955 m_osInterface,
1956 cmdBuffer,
1957 &resourceParams));
1958 }
1959
1960 // Current Motion Vector Temporal Buffer
1961 if (params->presCurMvTempBuffer != nullptr)
1962 {
1963 cmd.CurrentMotionVectorTemporalBufferMemoryAddressAttributes.DW0.Value |=
1964 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_HCP_MV_CODEC].Value;
1965
1966 resourceParams.presResource = params->presCurMvTempBuffer;
1967 resourceParams.dwOffset = 0;
1968 resourceParams.pdwCmd = (cmd.CurrentMotionVectorTemporalBuffer.DW0_1.Value);
1969 resourceParams.dwLocationInCmd = 31;
1970 resourceParams.bIsWritable = true;
1971
1972 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
1973 m_osInterface,
1974 cmdBuffer,
1975 &resourceParams));
1976 }
1977
1978 // Only one control DW53 for all references
1979 cmd.ReferencePictureBaseAddressMemoryAddressAttributes.DW0.Value |=
1980 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_REFERENCE_PICTURE_CODEC].Value;
1981
1982 bool firstRefPic = true;
1983 MOS_MEMCOMP_STATE mmcMode = MOS_MEMCOMP_DISABLED;
1984
1985 // NOTE: for both HEVC and VP9, set all the 8 ref pic addresses in HCP_PIPE_BUF_ADDR_STATE command to valid addresses for error concealment purpose
1986 for (uint32_t i = 0; i < CODECHAL_MAX_CUR_NUM_REF_FRAME_HEVC; i++)
1987 {
1988 // Reference Picture Buffer
1989 if (params->presReferences[i] != nullptr)
1990 {
1991 MOS_ZeroMemory(&details, sizeof(details));
1992 details.Format = Format_Invalid;
1993 MHW_MI_CHK_STATUS(m_osInterface->pfnGetResourceInfo(m_osInterface, params->presReferences[i], &details));
1994
1995 if (firstRefPic)
1996 {
1997 cmd.ReferencePictureBaseAddressMemoryAddressAttributes.DW0.BaseAddressTiledResourceMode = Mhw_ConvertToTRMode(details.TileType);
1998 firstRefPic = false;
1999 }
2000
2001 resourceParams.presResource = params->presReferences[i];
2002 resourceParams.pdwCmd = (cmd.ReferencePictureBaseAddressRefaddr07[i].DW0_1.Value);
2003 resourceParams.dwOffset = details.RenderOffset.YUV.Y.BaseOffset;
2004 resourceParams.dwLocationInCmd = (i * 2) + 37; // * 2 to account for QW rather than DW
2005 if (params->IBCRefIdxMask & (1 << i))
2006 {
2007 // Motion Compensation will use this picture to write and read IBC data
2008 resourceParams.bIsWritable = true;
2009 }
2010 else
2011 {
2012 resourceParams.bIsWritable = false;
2013 }
2014
2015 resourceParams.dwSharedMocsOffset = 53 - resourceParams.dwLocationInCmd; // Common Prodected Data bit is in DW53
2016
2017 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2018 m_osInterface,
2019 cmdBuffer,
2020 &resourceParams));
2021 }
2022 }
2023
2024 auto paramsG12 = dynamic_cast<PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS_G12>(params);
2025 MHW_CHK_NULL_RETURN(paramsG12);
2026 if (paramsG12->bSpecificReferencedMmcRequired)
2027 {
2028 cmd.ReferencePictureBaseAddressMemoryAddressAttributes.DW0.BaseAddressMemoryCompressionEnable = MmcEnable(paramsG12->ReferencesMmcState) ? 1 : 0;
2029 cmd.ReferencePictureBaseAddressMemoryAddressAttributes.DW0.CompressionType = MmcIsRc(paramsG12->ReferencesMmcState) ? 1 : 0;;
2030 }
2031 else
2032 {
2033 // Same MMC status for deblock and ref surfaces
2034 cmd.ReferencePictureBaseAddressMemoryAddressAttributes.DW0.BaseAddressMemoryCompressionEnable = cmd.DecodedPictureMemoryAddressAttributes.DW0.BaseAddressMemoryCompressionEnable;
2035 cmd.ReferencePictureBaseAddressMemoryAddressAttributes.DW0.CompressionType = cmd.DecodedPictureMemoryAddressAttributes.DW0.CompressionType;
2036 }
2037
2038 // Reset dwSharedMocsOffset
2039 resourceParams.dwSharedMocsOffset = 0;
2040
2041 // Original Uncompressed Picture Source, Encoder only
2042 if (params->psRawSurface != nullptr)
2043 {
2044 cmd.OriginalUncompressedPictureSourceMemoryAddressAttributes.DW0.Value |=
2045 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_ORIGINAL_UNCOMPRESSED_PICTURE_ENCODE].Value;
2046 cmd.OriginalUncompressedPictureSourceMemoryAddressAttributes.DW0.BaseAddressMemoryCompressionEnable = MmcEnable(params->RawSurfMmcState) ? 1 : 0;
2047 cmd.OriginalUncompressedPictureSourceMemoryAddressAttributes.DW0.CompressionType = MmcIsRc(params->RawSurfMmcState) ? 1 : 0;
2048
2049 cmd.OriginalUncompressedPictureSourceMemoryAddressAttributes.DW0.BaseAddressTiledResourceMode = Mhw_ConvertToTRMode(params->psRawSurface->TileType);
2050
2051 resourceParams.presResource = ¶ms->psRawSurface->OsResource;
2052 resourceParams.dwOffset = params->psRawSurface->dwOffset;
2053 resourceParams.pdwCmd = (cmd.OriginalUncompressedPictureSource.DW0_1.Value);
2054 resourceParams.dwLocationInCmd = 54;
2055 resourceParams.bIsWritable = false;
2056
2057 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2058 m_osInterface,
2059 cmdBuffer,
2060 &resourceParams));
2061 }
2062
2063 // StreamOut Data Destination, Decoder only
2064 if (params->presStreamOutBuffer != nullptr)
2065 {
2066 cmd.StreamoutDataDestinationMemoryAddressAttributes.DW0.Value |=
2067 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_STREAMOUT_DATA_CODEC].Value;
2068
2069 resourceParams.presResource = params->presStreamOutBuffer;
2070 resourceParams.dwOffset = 0;
2071 resourceParams.pdwCmd = (cmd.StreamoutDataDestination.DW0_1.Value);
2072 resourceParams.dwLocationInCmd = 57;
2073 resourceParams.bIsWritable = true;
2074
2075 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2076 m_osInterface,
2077 cmdBuffer,
2078 &resourceParams));
2079 }
2080
2081 // Pak Cu Level Streamout Data
2082 if (params->presPakCuLevelStreamoutBuffer != nullptr)
2083 {
2084 cmd.StreamoutDataDestinationMemoryAddressAttributes.DW0.Value |=
2085 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_STREAMOUT_DATA_CODEC].Value;
2086 resourceParams.presResource = params->presPakCuLevelStreamoutBuffer;
2087 resourceParams.dwOffset = 0;
2088 resourceParams.pdwCmd = (cmd.StreamoutDataDestination.DW0_1.Value);
2089 resourceParams.dwLocationInCmd = 57;
2090 resourceParams.bIsWritable = true;
2091
2092 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2093 m_osInterface,
2094 cmdBuffer,
2095 &resourceParams));
2096 }
2097
2098 // Decoded Picture Status / Error Buffer Base Address
2099 if (params->presLcuBaseAddressBuffer != nullptr)
2100 {
2101 cmd.DecodedPictureStatusErrorBufferBaseAddressMemoryAddressAttributes.DW0.Value |=
2102 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_HCP_STATUS_ERROR_CODEC].Value;
2103
2104 resourceParams.presResource = params->presLcuBaseAddressBuffer;
2105 resourceParams.dwOffset = params->dwLcuStreamOutOffset;
2106 resourceParams.pdwCmd = (cmd.DecodedPictureStatusErrorBufferBaseAddressOrEncodedSliceSizeStreamoutBaseAddress.DW0_1.Value);
2107 resourceParams.dwLocationInCmd = 60;
2108 resourceParams.bIsWritable = true;
2109
2110 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2111 m_osInterface,
2112 cmdBuffer,
2113 &resourceParams));
2114 }
2115
2116 // LCU ILDB StreamOut Buffer
2117 if (params->presLcuILDBStreamOutBuffer != nullptr)
2118 {
2119 cmd.LcuIldbStreamoutBufferMemoryAddressAttributes.DW0.Value |=
2120 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_HCP_LCU_ILDB_STREAMOUT_CODEC].Value;
2121
2122 resourceParams.presResource = params->presLcuILDBStreamOutBuffer;
2123 resourceParams.dwOffset = 0;
2124 resourceParams.pdwCmd = (cmd.LcuIldbStreamoutBuffer.DW0_1.Value);
2125 resourceParams.dwLocationInCmd = 63;
2126 resourceParams.bIsWritable = true;
2127
2128 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2129 m_osInterface,
2130 cmdBuffer,
2131 &resourceParams));
2132 }
2133
2134 cmd.CollocatedMotionVectorTemporalBuffer07MemoryAddressAttributes.DW0.Value |=
2135 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_HCP_MV_CODEC].Value;
2136
2137 for (uint32_t i = 0; i < CODECHAL_MAX_CUR_NUM_REF_FRAME_HEVC; i++)
2138 {
2139 // Collocated Motion vector Temporal Buffer
2140 if (params->presColMvTempBuffer[i] != nullptr)
2141 {
2142 resourceParams.presResource = params->presColMvTempBuffer[i];
2143 resourceParams.dwOffset = 0;
2144 resourceParams.pdwCmd = (cmd.CollocatedMotionVectorTemporalBuffer07[i].DW0_1.Value);
2145 resourceParams.dwLocationInCmd = (i * 2) + 66;
2146 resourceParams.bIsWritable = false;
2147
2148 resourceParams.dwSharedMocsOffset = 82 - resourceParams.dwLocationInCmd; // Common Prodected Data bit is in DW82
2149
2150 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2151 m_osInterface,
2152 cmdBuffer,
2153 &resourceParams));
2154 }
2155 }
2156
2157 // Reset dwSharedMocsOffset
2158 resourceParams.dwSharedMocsOffset = 0;
2159
2160 // VP9 Probability Buffer
2161 if (params->presVp9ProbBuffer != nullptr)
2162 {
2163 cmd.Vp9ProbabilityBufferReadWriteMemoryAddressAttributes.DW0.Value |=
2164 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_VP9_PROBABILITY_BUFFER_CODEC].Value;
2165
2166 resourceParams.presResource = params->presVp9ProbBuffer;
2167 resourceParams.dwOffset = 0;
2168 resourceParams.pdwCmd = (cmd.Vp9ProbabilityBufferReadWrite.DW0_1.Value);
2169 resourceParams.dwLocationInCmd = 83;
2170 resourceParams.bIsWritable = true;
2171
2172 resourceParams.dwSharedMocsOffset = 85 - resourceParams.dwLocationInCmd; // Common Prodected Data bit is in DW88
2173
2174 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2175 m_osInterface,
2176 cmdBuffer,
2177 &resourceParams));
2178 }
2179
2180 // Reset dwSharedMocsOffset
2181 resourceParams.dwSharedMocsOffset = 0;
2182
2183 // VP9 Segment Id Buffer
2184 if (params->presVp9SegmentIdBuffer != nullptr)
2185 {
2186 cmd.Vp9SegmentIdBufferReadWriteMemoryAddressAttributes.DW0.Value |=
2187 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_VP9_SEGMENT_ID_BUFFER_CODEC].Value;
2188
2189 resourceParams.presResource = params->presVp9SegmentIdBuffer;
2190 resourceParams.dwOffset = 0;
2191 resourceParams.pdwCmd = (cmd.DW86_87.Value);
2192 resourceParams.dwLocationInCmd = 86;
2193 resourceParams.bIsWritable = true;
2194
2195 resourceParams.dwSharedMocsOffset = 88 - resourceParams.dwLocationInCmd; // Common Prodected Data bit is in DW88
2196
2197 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2198 m_osInterface,
2199 cmdBuffer,
2200 &resourceParams));
2201 }
2202
2203 // Reset dwSharedMocsOffset
2204 resourceParams.dwSharedMocsOffset = 0;
2205
2206 // HVD Line Row Store Buffer
2207 if (m_vp9HvdRowStoreCache.bEnabled)
2208 {
2209 cmd.Vp9HvdLineRowstoreBufferReadWriteMemoryAddressAttributes.DW0.BaseAddressRowStoreScratchBufferCacheSelect = cmd.Vp9HvdLineRowstoreBufferReadWriteMemoryAddressAttributes.BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1;
2210 cmd.Vp9HvdLineRowstoreBufferReadWrite.DW0_1.Graphicsaddress476 = m_vp9HvdRowStoreCache.dwAddress;
2211 }
2212 else if (params->presHvdLineRowStoreBuffer != nullptr)
2213 {
2214 cmd.Vp9HvdLineRowstoreBufferReadWriteMemoryAddressAttributes.DW0.Value |=
2215 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_VP9_HVD_ROWSTORE_BUFFER_CODEC].Value;
2216
2217 resourceParams.presResource = params->presHvdLineRowStoreBuffer;
2218 resourceParams.dwOffset = 0;
2219 resourceParams.pdwCmd = (cmd.Vp9HvdLineRowstoreBufferReadWrite.DW0_1.Value);
2220 resourceParams.dwLocationInCmd = 89;
2221 resourceParams.bIsWritable = true;
2222
2223 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2224 m_osInterface,
2225 cmdBuffer,
2226 &resourceParams));
2227 }
2228
2229 // HVC Tile Row Store Buffer
2230 if (params->presHvdTileRowStoreBuffer != nullptr)
2231 {
2232 cmd.Vp9HvdTileRowstoreBufferReadWriteMemoryAddressAttributes.DW0.Value |=
2233 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_VP9_HVD_ROWSTORE_BUFFER_CODEC].Value;
2234
2235 resourceParams.presResource = params->presHvdTileRowStoreBuffer;
2236 resourceParams.dwOffset = 0;
2237 resourceParams.pdwCmd = (cmd.Vp9HvdTileRowstoreBufferReadWrite.DW0_1.Value);
2238 resourceParams.dwLocationInCmd = 92;
2239 resourceParams.bIsWritable = true;
2240
2241 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2242 m_osInterface,
2243 cmdBuffer,
2244 &resourceParams));
2245 }
2246
2247 // HEVC SAO row store buffer, HSAO
2248 if (m_hevcHSaoRowStoreCache.bEnabled)
2249 {
2250 cmd.SaoRowstoreBufferReadWriteMemoryAddressAttributes.DW0.BaseAddressRowStoreScratchBufferCacheSelect = cmd.SaoRowstoreBufferReadWriteMemoryAddressAttributes.BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1;
2251 cmd.DW95_96.SaoRowstoreBufferBaseAddress = (uint64_t)(m_hevcHSaoRowStoreCache.dwAddress) << 6;
2252 }
2253 else if (params->presSaoRowStoreBuffer != nullptr)
2254 {
2255 cmd.SaoRowstoreBufferReadWriteMemoryAddressAttributes.DW0.Value |=
2256 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_STREAMOUT_DATA_CODEC].Value;
2257
2258 resourceParams.presResource = params->presSaoRowStoreBuffer;
2259 resourceParams.dwOffset = 0;
2260 resourceParams.pdwCmd = (cmd.DW95_96.Value);
2261 resourceParams.dwLocationInCmd = 95;
2262 resourceParams.bIsWritable = true;
2263
2264 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2265 m_osInterface,
2266 cmdBuffer,
2267 &resourceParams));
2268 }
2269
2270 // Frame Statistics Streamout Data Destination Buffer
2271 if (params->presFrameStatStreamOutBuffer != nullptr)
2272 {
2273 cmd.FrameStatisticsStreamoutDataDestinationBufferAttributesReadWrite.DW0.Value |=
2274 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_STREAMOUT_DATA_CODEC].Value;
2275
2276 resourceParams.presResource = params->presFrameStatStreamOutBuffer;
2277 resourceParams.dwOffset = params->dwFrameStatStreamOutOffset;;
2278 resourceParams.pdwCmd = (cmd.FrameStatisticsStreamoutDataDestinationBufferBaseAddress.DW0_1.Value);
2279 resourceParams.dwLocationInCmd = 98;
2280 resourceParams.bIsWritable = true;
2281
2282 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2283 m_osInterface,
2284 cmdBuffer,
2285 &resourceParams));
2286 }
2287
2288 // SSE Source Pixel Row Store Buffer
2289 if (params->presSseSrcPixelRowStoreBuffer != nullptr)
2290 {
2291 cmd.SseSourcePixelRowstoreBufferAttributesReadWrite.DW0.Value |=
2292 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_SSE_SRC_PIXEL_ROW_STORE_BUFFER_CODEC].Value;
2293
2294 resourceParams.presResource = params->presSseSrcPixelRowStoreBuffer;
2295 resourceParams.dwOffset = 0;
2296 resourceParams.pdwCmd = (cmd.SseSourcePixelRowstoreBufferBaseAddress.DW0_1.Value);
2297 resourceParams.dwLocationInCmd = 101;
2298 resourceParams.bIsWritable = true;
2299
2300 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2301 m_osInterface,
2302 cmdBuffer,
2303 &resourceParams));
2304 }
2305
2306 // Gen12 new added buffer
2307 // Slice state stream out buffer
2308 if (paramsG12->presSliceStateStreamOutBuffer != nullptr)
2309 {
2310 cmd.HcpScalabilitySliceStateBufferAttributesReadWrite.DW0.Value |=
2311 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_SLICE_STATE_STREAM_OUT_BUFFER_CODEC].Value;
2312
2313 resourceParams.presResource = paramsG12->presSliceStateStreamOutBuffer;
2314 resourceParams.dwOffset = 0;
2315 resourceParams.pdwCmd = (cmd.HcpScalabilitySliceStateBufferBaseAddress.DW0_1.Value);
2316 resourceParams.dwLocationInCmd = 104;
2317 resourceParams.bIsWritable = true;
2318
2319 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2320 m_osInterface,
2321 cmdBuffer,
2322 &resourceParams));
2323 }
2324
2325 // CABAC Syntax stream out buffer
2326 if (paramsG12->presCABACSyntaxStreamOutBuffer != nullptr)
2327 {
2328 cmd.HcpScalabilityCabacDecodedSyntaxElementsBufferAttributesReadWrite.DW0.Value |=
2329 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_CABAC_SYNTAX_STREAM_OUT_BUFFER_CODEC].Value;
2330
2331 resourceParams.presResource = paramsG12->presCABACSyntaxStreamOutBuffer;
2332 resourceParams.dwOffset = 0;
2333 resourceParams.pdwCmd = (cmd.HcpScalabilityCabacDecodedSyntaxElementsBufferBaseAddress.DW0_1.Value);
2334 resourceParams.dwLocationInCmd = 107;
2335 resourceParams.bIsWritable = true;
2336
2337 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2338 m_osInterface,
2339 cmdBuffer,
2340 &resourceParams));
2341 }
2342
2343 // MV Upper Right Col Store
2344 if (paramsG12->presMvUpRightColStoreBuffer != nullptr)
2345 {
2346 cmd.MotionVectorUpperRightColumnStoreBufferAttributesReadWrite.DW0.Value |=
2347 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_PRED_COL_STORE_BUFFER_CODEC].Value;
2348
2349 resourceParams.presResource = paramsG12->presMvUpRightColStoreBuffer;
2350 resourceParams.dwOffset = 0;
2351 resourceParams.pdwCmd = (cmd.MotionVectorUpperRightColumnStoreBufferBaseAddress.DW0_1.Value);
2352 resourceParams.dwLocationInCmd = 110;
2353 resourceParams.bIsWritable = true;
2354
2355 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2356 m_osInterface,
2357 cmdBuffer,
2358 &resourceParams));
2359 }
2360
2361 // IntraPred Upper Right Col Store
2362 if (paramsG12->presIntraPredUpRightColStoreBuffer != nullptr)
2363 {
2364 cmd.IntraPredictionUpperRightColumnStoreBufferAttributesReadWrite.DW0.Value |=
2365 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_PRED_COL_STORE_BUFFER_CODEC].Value;
2366
2367 resourceParams.presResource = paramsG12->presIntraPredUpRightColStoreBuffer;
2368 resourceParams.dwOffset = 0;
2369 resourceParams.pdwCmd = (cmd.IntraPredictionUpperRightColumnStoreBufferBaseAddress.DW0_1.Value);
2370 resourceParams.dwLocationInCmd = 113;
2371 resourceParams.bIsWritable = true;
2372
2373 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2374 m_osInterface,
2375 cmdBuffer,
2376 &resourceParams));
2377 }
2378
2379 // IntraPred Left Recon Col Store
2380 if (paramsG12->presIntraPredLeftReconColStoreBuffer != nullptr)
2381 {
2382 cmd.IntraPredictionLeftReconColumnStoreBufferAttributesReadWrite.DW0.Value |=
2383 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_PRED_COL_STORE_BUFFER_CODEC].Value;
2384
2385 resourceParams.presResource = paramsG12->presIntraPredLeftReconColStoreBuffer;
2386 resourceParams.dwOffset = 0;
2387 resourceParams.pdwCmd = (cmd.IntraPredictionLeftReconColumnStoreBufferBaseAddress.DW0_1.Value);
2388 resourceParams.dwLocationInCmd = 116;
2389 resourceParams.bIsWritable = true;
2390
2391 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2392 m_osInterface,
2393 cmdBuffer,
2394 &resourceParams));
2395 }
2396
2397 // CABAC Syntax Stream Out Buffer Max Address
2398 if (paramsG12->presCABACSyntaxStreamOutMaxAddr != nullptr)
2399 {
2400 resourceParams.presResource = paramsG12->presCABACSyntaxStreamOutMaxAddr;
2401 resourceParams.dwOffset = 0;
2402 resourceParams.pdwCmd = (cmd.HcpScalabilityCabacDecodedSyntaxElementsBufferMaxAddress.DW0_1.Value);
2403 resourceParams.dwLocationInCmd = 119;
2404 resourceParams.bIsWritable = true;
2405
2406 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2407 m_osInterface,
2408 cmdBuffer,
2409 &resourceParams));
2410 }
2411
2412 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, sizeof(cmd)));
2413
2414 return eStatus;
2415 }
2416
AddHcpIndObjBaseAddrCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS params)2417 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpIndObjBaseAddrCmd(
2418 PMOS_COMMAND_BUFFER cmdBuffer,
2419 PMHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS params)
2420 {
2421 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
2422
2423 MHW_FUNCTION_ENTER;
2424
2425 MHW_MI_CHK_NULL(m_osInterface);
2426 MHW_MI_CHK_NULL(params);
2427
2428 MHW_RESOURCE_PARAMS resourceParams;
2429 mhw_vdbox_hcp_g12_X::HCP_IND_OBJ_BASE_ADDR_STATE_CMD cmd;
2430
2431 PMOS_CONTEXT pOsContext = m_osInterface->pOsContext;
2432 MHW_MI_CHK_NULL(pOsContext);
2433
2434 MOS_ZeroMemory(&resourceParams, sizeof(resourceParams));
2435 resourceParams.dwLsbNum = MHW_VDBOX_HCP_UPPER_BOUND_STATE_SHIFT;
2436 resourceParams.HwCommandType = MOS_MFX_INDIRECT_OBJ_BASE_ADDR;
2437
2438 // mode specific settings
2439 if (CodecHalIsDecodeModeVLD(params->Mode))
2440 {
2441 MHW_MI_CHK_NULL(params->presDataBuffer);
2442
2443 cmd.HcpIndirectBitstreamObjectMemoryAddressAttributes.DW0.Value |=
2444 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_MFX_INDIRECT_BITSTREAM_OBJECT_DECODE].Value;
2445
2446 resourceParams.presResource = params->presDataBuffer;
2447 resourceParams.dwOffset = params->dwDataOffset;
2448 resourceParams.pdwCmd = (cmd.HcpIndirectBitstreamObjectBaseAddress.DW0_1.Value);
2449 resourceParams.dwLocationInCmd = 1;
2450 resourceParams.dwSize = params->dwDataSize;
2451 resourceParams.bIsWritable = false;
2452
2453 // upper bound of the allocated resource will be set at 3 DW apart from address location
2454 resourceParams.dwUpperBoundLocationOffsetFromCmd = 3;
2455
2456 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2457 m_osInterface,
2458 cmdBuffer,
2459 &resourceParams));
2460
2461 if(HalOcaInterface::IsLargeResouceDumpSupported())
2462 {
2463 HalOcaInterface::OnIndirectState(*cmdBuffer, (MOS_CONTEXT_HANDLE)pOsContext, resourceParams.presResource, 0, true, 0);
2464 }
2465
2466 resourceParams.dwUpperBoundLocationOffsetFromCmd = 0;
2467 }
2468
2469 // following is for encoder
2470 if (!m_decodeInUse)
2471 {
2472 if (params->presMvObjectBuffer)
2473 {
2474 cmd.HcpIndirectCuObjectObjectMemoryAddressAttributes.DW0.Value |=
2475 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_MFX_INDIRECT_MV_OBJECT_CODEC].Value;
2476
2477 resourceParams.presResource = params->presMvObjectBuffer;
2478 resourceParams.dwOffset = params->dwMvObjectOffset;
2479 resourceParams.pdwCmd = (cmd.DW6_7.Value);
2480 resourceParams.dwLocationInCmd = 6;
2481 resourceParams.dwSize = MOS_ALIGN_CEIL(params->dwMvObjectSize, 0x1000);
2482 resourceParams.bIsWritable = false;
2483
2484 // no upper bound for indirect CU object
2485 resourceParams.dwUpperBoundLocationOffsetFromCmd = 0;
2486
2487 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2488 m_osInterface,
2489 cmdBuffer,
2490 &resourceParams));
2491 }
2492
2493 if (params->presPakBaseObjectBuffer)
2494 {
2495 cmd.HcpPakBseObjectAddressMemoryAddressAttributes.DW0.Value |=
2496 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_MFC_INDIRECT_PAKBASE_OBJECT_CODEC].Value;
2497
2498 resourceParams.presResource = params->presPakBaseObjectBuffer;
2499 resourceParams.dwOffset = params->presPakBaseObjectBuffer->dwResourceOffset;
2500 resourceParams.pdwCmd = (cmd.DW9_10.Value);
2501 resourceParams.dwLocationInCmd = 9;
2502 resourceParams.dwSize = MOS_ALIGN_FLOOR(params->dwPakBaseObjectSize, 0x1000);
2503 resourceParams.bIsWritable = true;
2504
2505 // upper bound of the allocated resource will be set at 3 DW apart from address location
2506 resourceParams.dwUpperBoundLocationOffsetFromCmd = 3;
2507
2508 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2509 m_osInterface,
2510 cmdBuffer,
2511 &resourceParams));
2512
2513 resourceParams.dwUpperBoundLocationOffsetFromCmd = 0;
2514 }
2515
2516 if (params->presCompressedHeaderBuffer)
2517 {
2518 cmd.HcpVp9PakCompressedHeaderSyntaxStreaminMemoryAddressAttributes.DW0.Value |=
2519 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_COMPRESSED_HEADER_BUFFER_CODEC].Value;
2520
2521 resourceParams.presResource = params->presCompressedHeaderBuffer;
2522 resourceParams.dwOffset = 0;
2523 resourceParams.pdwCmd = (cmd.DW14_15.Value);
2524 resourceParams.dwLocationInCmd = 14;
2525 resourceParams.dwSize = params->dwCompressedHeaderSize;
2526 resourceParams.bIsWritable = false;
2527
2528 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2529 m_osInterface,
2530 cmdBuffer,
2531 &resourceParams));
2532 }
2533
2534 if (params->presProbabilityCounterBuffer)
2535 {
2536 cmd.HcpVp9PakProbabilityCounterStreamoutMemoryAddressAttributes.DW0.Value |=
2537 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_VP9_PROBABILITY_COUNTER_BUFFER_CODEC].Value;
2538
2539 resourceParams.presResource = params->presProbabilityCounterBuffer;
2540 resourceParams.dwOffset = params->dwProbabilityCounterOffset;
2541 resourceParams.pdwCmd = (cmd.DW17_18.Value);
2542 resourceParams.dwLocationInCmd = 17;
2543 resourceParams.dwSize = params->dwProbabilityCounterSize;
2544 resourceParams.bIsWritable = true;
2545
2546 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2547 m_osInterface,
2548 cmdBuffer,
2549 &resourceParams));
2550 }
2551
2552 if (params->presProbabilityDeltaBuffer)
2553 {
2554 cmd.HcpVp9PakProbabilityDeltasStreaminMemoryAddressAttributes.DW0.Value |=
2555 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_PROBABILITY_DELTA_BUFFER_CODEC].Value;
2556
2557 resourceParams.presResource = params->presProbabilityDeltaBuffer;
2558 resourceParams.dwOffset = 0;
2559 resourceParams.pdwCmd = (cmd.DW20_21.Value);
2560 resourceParams.dwLocationInCmd = 20;
2561 resourceParams.dwSize = params->dwProbabilityDeltaSize;
2562 resourceParams.bIsWritable = false;
2563
2564 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2565 m_osInterface,
2566 cmdBuffer,
2567 &resourceParams));
2568 }
2569
2570 //Following 2 blocks try to program "cmd.DW23_24.Value"
2571 //So only one of presTileRecordBuffer and presPakTileSizeStasBuffer has to be used!
2572 if (params->presTileRecordBuffer)
2573 {
2574 cmd.HcpVp9PakTileRecordStreamoutMemoryAddressAttributes.DW0.Value |=
2575 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_TILE_RECORD_BUFFER_CODEC].Value;
2576
2577 resourceParams.presResource = params->presTileRecordBuffer;
2578 resourceParams.dwOffset = 0;
2579 resourceParams.pdwCmd = (cmd.DW23_24.Value);
2580 resourceParams.dwLocationInCmd = 23;
2581 resourceParams.dwSize = params->dwTileRecordSize;
2582 resourceParams.bIsWritable = true;
2583
2584 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2585 m_osInterface,
2586 cmdBuffer,
2587 &resourceParams));
2588
2589 }
2590 else if (params->presPakTileSizeStasBuffer)
2591 {
2592 cmd.HcpVp9PakTileRecordStreamoutMemoryAddressAttributes.DW0.Value |=
2593 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_TILE_SIZE_STAS_BUFFER_CODEC].Value;
2594
2595 resourceParams.presResource = params->presPakTileSizeStasBuffer;
2596 resourceParams.dwOffset = params->dwPakTileSizeRecordOffset;
2597 resourceParams.pdwCmd = (cmd.DW23_24.Value);
2598 resourceParams.dwLocationInCmd = 23;
2599 resourceParams.dwSize = params->dwPakTileSizeStasBufferSize;
2600 resourceParams.bIsWritable = WRITE_WA;
2601
2602 MHW_MI_CHK_STATUS(pfnAddResourceToCmd(
2603 m_osInterface,
2604 cmdBuffer,
2605 &resourceParams));
2606 }
2607
2608 }
2609
2610 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
2611
2612 return eStatus;
2613 }
2614
AddHcpDecodePicStateCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VDBOX_HEVC_PIC_STATE params)2615 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpDecodePicStateCmd(
2616 PMOS_COMMAND_BUFFER cmdBuffer,
2617 PMHW_VDBOX_HEVC_PIC_STATE params)
2618 {
2619 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
2620
2621 MHW_FUNCTION_ENTER;
2622
2623 MHW_MI_CHK_NULL(params);
2624 MHW_MI_CHK_NULL(params->pHevcPicParams);
2625
2626 auto paramsG12 = dynamic_cast<PMHW_VDBOX_HEVC_PIC_STATE_G12>(params);
2627 MHW_MI_CHK_NULL(paramsG12);
2628
2629 auto hevcPicParams = paramsG12->pHevcPicParams;
2630 auto hevcExtPicParams = paramsG12->pHevcExtPicParams;
2631 auto hevcSccPicParams = paramsG12->pHevcSccPicParams;
2632
2633 if (hevcExtPicParams && hevcExtPicParams->PicRangeExtensionFlags.fields.cabac_bypass_alignment_enabled_flag == 1)
2634 {
2635 MHW_ASSERTMESSAGE("HW decoder doesn't support HEVC High Throughput profile so far.");
2636 MHW_ASSERTMESSAGE("So cabac_bypass_alignment_enabled_flag cannot equal to 1.");
2637 return MOS_STATUS_INVALID_PARAMETER;
2638 }
2639
2640 mhw_vdbox_hcp_g12_X::HCP_PIC_STATE_CMD *cmd =
2641 (mhw_vdbox_hcp_g12_X::HCP_PIC_STATE_CMD*)cmdBuffer->pCmdPtr;
2642
2643 MHW_MI_CHK_STATUS(MhwVdboxHcpInterfaceGeneric<mhw_vdbox_hcp_g12_X>::AddHcpDecodePicStateCmd(cmdBuffer, params));
2644
2645 // RExt fields
2646 cmd->DW2.ChromaSubsampling = hevcPicParams->chroma_format_idc;
2647 cmd->DW3.Log2Maxtransformskipsize = 0x2;
2648 if (hevcExtPicParams)
2649 {
2650 cmd->DW3.Log2Maxtransformskipsize = hevcExtPicParams->log2_max_transform_skip_block_size_minus2 + 2;
2651 cmd->DW3.CrossComponentPredictionEnabledFlag = hevcExtPicParams->PicRangeExtensionFlags.fields.cross_component_prediction_enabled_flag;
2652 cmd->DW3.CabacBypassAlignmentEnabledFlag = hevcExtPicParams->PicRangeExtensionFlags.fields.cabac_bypass_alignment_enabled_flag;
2653 cmd->DW3.PersistentRiceAdaptationEnabledFlag = hevcExtPicParams->PicRangeExtensionFlags.fields.persistent_rice_adaptation_enabled_flag;
2654 cmd->DW3.IntraSmoothingDisabledFlag = hevcExtPicParams->PicRangeExtensionFlags.fields.intra_smoothing_disabled_flag;
2655 cmd->DW3.ExplicitRdpcmEnabledFlag = hevcExtPicParams->PicRangeExtensionFlags.fields.explicit_rdpcm_enabled_flag;
2656 cmd->DW3.ImplicitRdpcmEnabledFlag = hevcExtPicParams->PicRangeExtensionFlags.fields.implicit_rdpcm_enabled_flag;
2657 cmd->DW3.TransformSkipContextEnabledFlag = hevcExtPicParams->PicRangeExtensionFlags.fields.transform_skip_context_enabled_flag;
2658 cmd->DW3.TransformSkipRotationEnabledFlag = hevcExtPicParams->PicRangeExtensionFlags.fields.transform_skip_rotation_enabled_flag;
2659 cmd->DW3.HighPrecisionOffsetsEnableFlag = hevcExtPicParams->PicRangeExtensionFlags.fields.high_precision_offsets_enabled_flag;
2660 cmd->DW2.ChromaQpOffsetListEnabledFlag = hevcExtPicParams->PicRangeExtensionFlags.fields.chroma_qp_offset_list_enabled_flag;
2661 cmd->DW2.DiffCuChromaQpOffsetDepth = hevcExtPicParams->diff_cu_chroma_qp_offset_depth;
2662 cmd->DW2.ChromaQpOffsetListLenMinus1 = hevcExtPicParams->chroma_qp_offset_list_len_minus1;
2663 cmd->DW2.Log2SaoOffsetScaleLuma = hevcExtPicParams->log2_sao_offset_scale_luma;
2664 cmd->DW2.Log2SaoOffsetScaleChroma = hevcExtPicParams->log2_sao_offset_scale_chroma;
2665
2666 cmd->DW32.CbQpOffsetList0 = hevcExtPicParams->cb_qp_offset_list[0];
2667 cmd->DW32.CbQpOffsetList1 = hevcExtPicParams->cb_qp_offset_list[1];
2668 cmd->DW32.CbQpOffsetList2 = hevcExtPicParams->cb_qp_offset_list[2];
2669 cmd->DW32.CbQpOffsetList3 = hevcExtPicParams->cb_qp_offset_list[3];
2670 cmd->DW32.CbQpOffsetList4 = hevcExtPicParams->cb_qp_offset_list[4];
2671 cmd->DW32.CbQpOffsetList5 = hevcExtPicParams->cb_qp_offset_list[5];
2672 cmd->DW33.CrQpOffsetList0 = hevcExtPicParams->cr_qp_offset_list[0];
2673 cmd->DW33.CrQpOffsetList1 = hevcExtPicParams->cr_qp_offset_list[1];
2674 cmd->DW33.CrQpOffsetList2 = hevcExtPicParams->cr_qp_offset_list[2];
2675 cmd->DW33.CrQpOffsetList3 = hevcExtPicParams->cr_qp_offset_list[3];
2676 cmd->DW33.CrQpOffsetList4 = hevcExtPicParams->cr_qp_offset_list[4];
2677 cmd->DW33.CrQpOffsetList5 = hevcExtPicParams->cr_qp_offset_list[5];
2678 }
2679
2680 cmd->DW5.BitDepthChromaMinus8 = hevcPicParams->bit_depth_chroma_minus8;
2681 cmd->DW5.BitDepthLumaMinus8 = hevcPicParams->bit_depth_luma_minus8;
2682
2683 if (hevcSccPicParams)
2684 {
2685 // DWORD 34
2686 cmd->DW34.IbcMotionCompensationBufferReferenceIdc = paramsG12->ucRecNotFilteredID;
2687 cmd->DW34.PpsActCrQpOffsetPlus3 = hevcSccPicParams->pps_act_cr_qp_offset_plus3;
2688 cmd->DW34.PpsActCbQpOffsetPlus5 = hevcSccPicParams->pps_act_cb_qp_offset_plus5;
2689 cmd->DW34.PpsActYOffsetPlus5 = hevcSccPicParams->pps_act_y_qp_offset_plus5;
2690 cmd->DW34.PpsSliceActQpOffsetsPresentFlag = hevcSccPicParams->PicSCCExtensionFlags.fields.pps_slice_act_qp_offsets_present_flag;
2691 cmd->DW34.ResidualAdaptiveColourTransformEnabledFlag = hevcSccPicParams->PicSCCExtensionFlags.fields.residual_adaptive_colour_transform_enabled_flag;
2692 cmd->DW34.PpsCurrPicRefEnabledFlag = hevcSccPicParams->PicSCCExtensionFlags.fields.pps_curr_pic_ref_enabled_flag;
2693 cmd->DW34.MotionVectorResolutionControlIdc = hevcSccPicParams->PicSCCExtensionFlags.fields.motion_vector_resolution_control_idc;
2694 cmd->DW34.IntraBoundaryFilteringDisabledFlag = hevcSccPicParams->PicSCCExtensionFlags.fields.intra_boundary_filtering_disabled_flag;
2695 cmd->DW34.DeblockingFilterOverrideEnabledFlag = hevcPicParams->deblocking_filter_override_enabled_flag;
2696 cmd->DW34.PpsDeblockingFilterDisabledFlag = hevcPicParams->pps_deblocking_filter_disabled_flag;
2697
2698 // DWORD 35
2699 cmd->DW35.PaletteMaxSize = hevcSccPicParams->palette_max_size;
2700 cmd->DW35.DeltaPaletteMaxPredictorSize = hevcSccPicParams->delta_palette_max_predictor_size;
2701 cmd->DW35.IbcMotionVectorErrorHandlingDisable = 0;
2702 cmd->DW35.ChromaBitDepthEntryMinus8 = hevcPicParams->bit_depth_chroma_minus8;
2703 cmd->DW35.LumaBitDepthEntryMinus8 = hevcPicParams->bit_depth_luma_minus8;
2704 cmd->DW35.IbcConfiguration = hevcSccPicParams->PicSCCExtensionFlags.fields.pps_curr_pic_ref_enabled_flag ? 2 : 0;
2705 cmd->DW35.MonochromePaletteFlag = 0;
2706 cmd->DW35.PaletteModeEnabledFlag = hevcSccPicParams->PicSCCExtensionFlags.fields.palette_mode_enabled_flag;
2707 }
2708
2709 if (hevcPicParams && hevcPicParams->RequestCRC)
2710 {
2711 cmd->DW36.FrameCrcEnable = 1;
2712 cmd->DW36.FrameCrcType = 0;
2713 }
2714
2715 return eStatus;
2716 }
2717
AddHcpEncodePicStateCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VDBOX_HEVC_PIC_STATE params)2718 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpEncodePicStateCmd(
2719 PMOS_COMMAND_BUFFER cmdBuffer,
2720 PMHW_VDBOX_HEVC_PIC_STATE params)
2721 {
2722 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
2723
2724 MHW_FUNCTION_ENTER;
2725
2726 MHW_MI_CHK_NULL(params);
2727 MHW_MI_CHK_NULL(params->pHevcEncSeqParams);
2728 MHW_MI_CHK_NULL(params->pHevcEncPicParams);
2729
2730 auto paramsG12 = dynamic_cast<PMHW_VDBOX_HEVC_PIC_STATE_G12>(params);
2731 MHW_MI_CHK_NULL(paramsG12);
2732
2733 PMHW_BATCH_BUFFER batchBuffer = nullptr;
2734 mhw_vdbox_hcp_g12_X::HCP_PIC_STATE_CMD cmd;
2735
2736 auto hevcSeqParams = params->pHevcEncSeqParams;
2737 auto hevcPicParams = params->pHevcEncPicParams;
2738
2739 if (params->bBatchBufferInUse)
2740 {
2741 MHW_MI_CHK_NULL(params->pBatchBuffer);
2742 batchBuffer = params->pBatchBuffer;
2743 }
2744
2745 cmd.DW1.Framewidthinmincbminus1 = hevcSeqParams->wFrameWidthInMinCbMinus1;
2746 cmd.DW1.PakTransformSkipEnable = cmd.DW4.TransformSkipEnabledFlag = params->bTransformSkipEnable;
2747 cmd.DW1.Frameheightinmincbminus1 = hevcSeqParams->wFrameHeightInMinCbMinus1;
2748
2749 cmd.DW2.Mincusize = hevcSeqParams->log2_min_coding_block_size_minus3;
2750 cmd.DW2.CtbsizeLcusize = hevcSeqParams->log2_max_coding_block_size_minus3;
2751 cmd.DW2.Maxtusize = hevcSeqParams->log2_max_transform_block_size_minus2;
2752 cmd.DW2.Mintusize = hevcSeqParams->log2_min_transform_block_size_minus2;
2753 cmd.DW2.Minpcmsize = 0;
2754 cmd.DW2.Maxpcmsize = 0;
2755
2756 cmd.DW3.Colpicisi = 0;
2757 cmd.DW3.Curpicisi = 0;
2758
2759 cmd.DW4.SampleAdaptiveOffsetEnabledFlag = params->bSAOEnable;
2760 cmd.DW4.PcmEnabledFlag = 0; // Not supported in CNL
2761 cmd.DW4.CuQpDeltaEnabledFlag = hevcPicParams->cu_qp_delta_enabled_flag; // In VDENC mode, this field should always be set to 1.
2762 cmd.DW4.DiffCuQpDeltaDepthOrNamedAsMaxDqpDepth = hevcPicParams->diff_cu_qp_delta_depth;
2763 cmd.DW4.PcmLoopFilterDisableFlag = hevcSeqParams->pcm_loop_filter_disable_flag;
2764 cmd.DW4.ConstrainedIntraPredFlag = 0;
2765 cmd.DW4.Log2ParallelMergeLevelMinus2 = 0;
2766 cmd.DW4.SignDataHidingFlag = 0; // currently not supported in encoder
2767 cmd.DW4.LoopFilterAcrossTilesEnabledFlag = 0;
2768 cmd.DW4.EntropyCodingSyncEnabledFlag = 0; // not supported as per Dimas notes. PAK restriction
2769 cmd.DW4.TilesEnabledFlag = 0; // not supported in encoder
2770 cmd.DW4.WeightedPredFlag = hevcPicParams->weighted_pred_flag;
2771 cmd.DW4.WeightedBipredFlag = hevcPicParams->weighted_bipred_flag;
2772 cmd.DW4.Fieldpic = 0;
2773 cmd.DW4.Bottomfield = 0;
2774 cmd.DW4.AmpEnabledFlag = hevcSeqParams->amp_enabled_flag;
2775 cmd.DW4.TransquantBypassEnableFlag = hevcPicParams->transquant_bypass_enabled_flag;
2776 cmd.DW4.StrongIntraSmoothingEnableFlag = hevcSeqParams->strong_intra_smoothing_enable_flag;
2777 cmd.DW4.CuPacketStructure = 0; // output from HW VME, 1/2 CL per CU
2778 cmd.DW4.ConstrainedIntraPredFlag = hevcPicParams->constrained_intra_pred_flag;
2779
2780 cmd.DW5.PicCbQpOffset = hevcPicParams->pps_cb_qp_offset & 0x1f;
2781 cmd.DW5.PicCrQpOffset = hevcPicParams->pps_cr_qp_offset & 0x1f;
2782 cmd.DW5.MaxTransformHierarchyDepthIntraOrNamedAsTuMaxDepthIntra = hevcSeqParams->max_transform_hierarchy_depth_intra;
2783 cmd.DW5.MaxTransformHierarchyDepthInterOrNamedAsTuMaxDepthInter = hevcSeqParams->max_transform_hierarchy_depth_inter;
2784 cmd.DW5.PcmSampleBitDepthChromaMinus1 = hevcSeqParams->pcm_sample_bit_depth_chroma_minus1;
2785 cmd.DW5.PcmSampleBitDepthLumaMinus1 = hevcSeqParams->pcm_sample_bit_depth_luma_minus1;
2786 cmd.DW5.BitDepthChromaMinus8 = hevcSeqParams->bit_depth_chroma_minus8;
2787 cmd.DW5.BitDepthLumaMinus8 = hevcSeqParams->bit_depth_luma_minus8;
2788
2789 cmd.DW6.LcuMaxBitsizeAllowed = hevcPicParams->LcuMaxBitsizeAllowed;
2790 cmd.DW6.Nonfirstpassflag = 0; // needs to be updated for HEVC VDEnc
2791 cmd.DW6.LcumaxbitstatusenLcumaxsizereportmask = 0;
2792 cmd.DW6.FrameszoverstatusenFramebitratemaxreportmask = 0;
2793 cmd.DW6.FrameszunderstatusenFramebitrateminreportmask = 0;
2794 cmd.DW6.LoadSlicePointerFlag = 0; // must be set to 0 for encoder
2795
2796 cmd.DW19.RdoqEnable = params->bHevcRdoqEnabled;
2797 //only 420 format support SSE in DP encode
2798 cmd.DW19.SseEnable = params->bUseVDEnc || params->sseEnabledInVmeEncode;
2799 // only for VDEnc
2800 cmd.DW19.RhodomainRateControlEnable = params->bUseVDEnc || params->rhodomainRCEnable; // DW19[6]
2801 // RhoDomainFrameLevelQP: This QP is used for RhoDomain Frame level statistics.
2802 cmd.DW19.Rhodomainframelevelqp = cmd.DW19.RhodomainRateControlEnable ? hevcPicParams->QpY : 0; // DW19[13:8]
2803 cmd.DW19.FractionalQpAdjustmentEnable = params->bUseVDEnc; // DW19[17]
2804
2805 cmd.DW19.FirstSliceSegmentInPicFlag = 1;
2806 cmd.DW19.Nalunittypeflag = 0;
2807
2808 // For HEVC VDEnc Dynamic Slice Control
2809 if (hevcSeqParams->SliceSizeControl == 1)
2810 {
2811 cmd.DW19.PakDynamicSliceModeEnable = 1;
2812 cmd.DW19.SlicePicParameterSetId = hevcPicParams->slice_pic_parameter_set_id;
2813 cmd.DW19.Nalunittypeflag = (hevcPicParams->nal_unit_type >= HEVC_NAL_UT_BLA_W_LP) &&
2814 (hevcPicParams->nal_unit_type <= HEVC_NAL_UT_RSV_IRAP_VCL23);
2815 cmd.DW19.FirstSliceSegmentInPicFlag = 1;
2816 cmd.DW19.NoOutputOfPriorPicsFlag = hevcPicParams->no_output_of_prior_pics_flag;
2817
2818 cmd.DW21.SliceSizeThresholdInBytes = hevcPicParams->MaxSliceSizeInBytes; // HuC FW is expected to update this
2819 cmd.DW22.TargetSliceSizeInBytes = hevcPicParams->MaxSliceSizeInBytes;
2820 }
2821
2822 cmd.DW4.TilesEnabledFlag = hevcPicParams->tiles_enabled_flag;
2823 cmd.DW2.ChromaSubsampling = hevcSeqParams->chroma_format_idc;
2824 cmd.DW4.LoopFilterAcrossTilesEnabledFlag = hevcPicParams->loop_filter_across_tiles_flag;
2825
2826 // Disable HEVC RDOQ for Intra blocks
2827 cmd.DW20.Intratucountbasedrdoqdisable = params->bRDOQIntraTUDisable;
2828 //cmd.DW37.Rdoqintratuthreshold = params->wRDOQIntraTUThreshold;
2829
2830
2831 // new command for GEN12 to enable SCC
2832 // DW34
2833 cmd.DW34.IntraBoundaryFilteringDisabledFlag = hevcSeqParams->intra_boundary_filtering_disabled_flag;
2834 cmd.DW34.MotionVectorResolutionControlIdc = hevcSeqParams->motion_vector_resolution_control_idc;
2835 cmd.DW34.PpsCurrPicRefEnabledFlag = hevcPicParams->pps_curr_pic_ref_enabled_flag;
2836 cmd.DW34.IbcMotionCompensationBufferReferenceIdc = paramsG12->ucRecNotFilteredID;
2837
2838 // DW35
2839 // Enable both TBC and LBC by default, refine later
2840 cmd.DW35.IbcConfiguration = hevcPicParams->pps_curr_pic_ref_enabled_flag ?
2841 paramsG12->IBCControl :
2842 HCP_PIC_STATE_IBC_CONFIGURATION_IN_VDENC_MODE_UNNAMED0;
2843 // Enable palette mode
2844 cmd.DW35.PaletteModeEnabledFlag = hevcSeqParams->palette_mode_enabled_flag;
2845 cmd.DW35.MonochromePaletteFlag = 0; //Encoder does not support this
2846 cmd.DW35.PaletteMaxSize = hevcSeqParams->palette_mode_enabled_flag ? 64 : 0; // Encoder only supports default value
2847 cmd.DW35.DeltaPaletteMaxPredictorSize = hevcSeqParams->palette_mode_enabled_flag ? 32 : 0; // Encoder only supports default value
2848 cmd.DW35.LumaBitDepthEntryMinus8 = hevcSeqParams->bit_depth_luma_minus8;
2849 cmd.DW35.ChromaBitDepthEntryMinus8 = hevcSeqParams->bit_depth_chroma_minus8;
2850
2851 // Enable Partial Frame Update
2852 cmd.DW19.PartialFrameUpdateMode = paramsG12->PartialFrameUpdateEnable ? 1 : 0;
2853 cmd.DW19.TemporalMvPredDisable = !hevcSeqParams->sps_temporal_mvp_enable_flag;
2854 if (cmd.DW19.PartialFrameUpdateMode)
2855 {
2856 cmd.DW19.TemporalMvPredDisable = 1;
2857 }
2858 MHW_MI_CHK_STATUS(Mhw_AddCommandCmdOrBB(m_osInterface, cmdBuffer, batchBuffer, &cmd, sizeof(cmd)));
2859
2860 return eStatus;
2861 }
2862
AddHcpTileStateCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VDBOX_HEVC_TILE_STATE params)2863 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpTileStateCmd(
2864 PMOS_COMMAND_BUFFER cmdBuffer,
2865 PMHW_VDBOX_HEVC_TILE_STATE params)
2866 {
2867 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
2868
2869 MHW_FUNCTION_ENTER;
2870
2871 MHW_MI_CHK_NULL(m_osInterface);
2872 MHW_MI_CHK_NULL(params);
2873 MHW_MI_CHK_NULL(params->pTileColWidth);
2874 MHW_MI_CHK_NULL(params->pTileRowHeight);
2875
2876 mhw_vdbox_hcp_g12_X::HCP_TILE_STATE_CMD cmd;
2877
2878 auto hevcPicParams = params->pHevcPicParams;
2879
2880 MHW_CHK_COND(hevcPicParams->num_tile_rows_minus1 >= HEVC_NUM_MAX_TILE_ROW, "num_tile_rows_minus1 is out of range!");
2881 MHW_CHK_COND(hevcPicParams->num_tile_columns_minus1 >= HEVC_NUM_MAX_TILE_COLUMN, "num_tile_columns_minus1 is out of range!");
2882
2883 cmd.DW1.Numtilecolumnsminus1 = hevcPicParams->num_tile_columns_minus1;
2884 cmd.DW1.Numtilerowsminus1 = hevcPicParams->num_tile_rows_minus1;
2885
2886 uint32_t column = hevcPicParams->num_tile_columns_minus1 + 1;
2887 uint32_t lastDwEleNum = column % 4;
2888 uint32_t count = column / 4;
2889
2890 for (uint8_t i = 0; i < 5; i++)
2891 {
2892 cmd.CtbColumnPositionOfTileColumn[i].DW0.Value = 0;
2893 }
2894
2895 for (uint8_t i = 0; i < 6; i++)
2896 {
2897 cmd.CtbRowPositionOfTileRow[i].DW0.Value = 0;
2898 }
2899
2900 cmd.CtbColumnPositionMsb.DW0.Value = 0;
2901 cmd.CtbColumnPositionMsb.DW1.Value = 0;
2902 cmd.CtbRowPositionMsb.DW0.Value = 0;
2903 cmd.CtbRowPositionMsb.DW1.Value = 0;
2904
2905 uint32_t colCumulativeValue = 0;
2906 uint32_t rowCumulativeValue = 0;
2907
2908 // Column Position
2909 for (uint32_t i = 0; i < count; i++)
2910 {
2911 uint32_t &CtbColumnMsbValue = ((i << 3) >> 5) == 0 ? cmd.CtbColumnPositionMsb.DW0.Value : cmd.CtbColumnPositionMsb.DW1.Value;
2912
2913 cmd.CtbColumnPositionOfTileColumn[i].DW0.Ctbpos0I = colCumulativeValue & 0xFF;//lower 8bits
2914 CtbColumnMsbValue = CtbColumnMsbValue |
2915 (((colCumulativeValue >> 8) & 0x3) << ((i * 8) + 0));//MSB 2bits
2916 colCumulativeValue += params->pTileColWidth[4 * i];
2917
2918 cmd.CtbColumnPositionOfTileColumn[i].DW0.Ctbpos1I = colCumulativeValue & 0xFF;//lower 8bits
2919 CtbColumnMsbValue = CtbColumnMsbValue |
2920 (((colCumulativeValue >> 8) & 0x3) << ((i * 8) + 2));//MSB 2bits
2921 colCumulativeValue += params->pTileColWidth[4 * i + 1];
2922
2923 cmd.CtbColumnPositionOfTileColumn[i].DW0.Ctbpos2I = colCumulativeValue & 0xFF;//lower 8bits
2924 CtbColumnMsbValue = CtbColumnMsbValue |
2925 (((colCumulativeValue >> 8) & 0x3) << ((i * 8) + 4));//MSB 2bits
2926 colCumulativeValue += params->pTileColWidth[4 * i + 2];
2927
2928 cmd.CtbColumnPositionOfTileColumn[i].DW0.Ctbpos3I = colCumulativeValue & 0xFF;//lower 8bits
2929 CtbColumnMsbValue = CtbColumnMsbValue |
2930 (((colCumulativeValue >> 8) & 0x3) << ((i * 8) + 6));//MSB 2bits
2931 colCumulativeValue += params->pTileColWidth[4 * i + 3];
2932 }
2933
2934 if (lastDwEleNum)
2935 {
2936 uint32_t i = count;
2937 uint32_t &CtbColumnMsbValue = ((i << 3) >> 5) == 0 ? cmd.CtbColumnPositionMsb.DW0.Value : cmd.CtbColumnPositionMsb.DW1.Value;
2938
2939 if(i < 5)
2940 {
2941 cmd.CtbColumnPositionOfTileColumn[i].DW0.Ctbpos0I = colCumulativeValue & 0xFF;//lower 8bits
2942 CtbColumnMsbValue = CtbColumnMsbValue |
2943 (((colCumulativeValue >> 8) & 0x3) << ((i * 8) + 0));//MSB 2bits
2944
2945 if (lastDwEleNum > 1)
2946 {
2947 colCumulativeValue += params->pTileColWidth[4 * i];
2948 cmd.CtbColumnPositionOfTileColumn[i].DW0.Ctbpos1I = colCumulativeValue & 0xFF;//lower 8bits
2949 CtbColumnMsbValue = CtbColumnMsbValue |
2950 (((colCumulativeValue >> 8) & 0x3) << ((i * 8) + 2));//MSB 2bits
2951
2952 if (lastDwEleNum > 2)
2953 {
2954 colCumulativeValue += params->pTileColWidth[4 * i + 1];
2955 cmd.CtbColumnPositionOfTileColumn[i].DW0.Ctbpos2I = colCumulativeValue & 0xFF;//lower 8bits
2956 CtbColumnMsbValue = CtbColumnMsbValue |
2957 (((colCumulativeValue >> 8) & 0x3) << ((i * 8) + 4));//MSB 2bits
2958 }
2959 }
2960 }
2961 }
2962
2963 // Row Postion
2964 uint32_t row = hevcPicParams->num_tile_rows_minus1 + 1;
2965 lastDwEleNum = row % 4;
2966 count = row / 4;
2967
2968 for (uint32_t i = 0; i < count; i++)
2969 {
2970 uint32_t &CtbRowMsbValue = ((i << 3) >> 5) == 0 ? cmd.CtbRowPositionMsb.DW0.Value : cmd.CtbRowPositionMsb.DW1.Value;
2971
2972 cmd.CtbRowPositionOfTileRow[i].DW0.Ctbpos0I = rowCumulativeValue & 0xFF;//lower 8bits
2973 CtbRowMsbValue = CtbRowMsbValue |
2974 (((rowCumulativeValue >> 8) & 0x3) << ((i * 8) + 0));//MSB 2bits
2975 rowCumulativeValue += params->pTileRowHeight[4 * i];
2976
2977 cmd.CtbRowPositionOfTileRow[i].DW0.Ctbpos1I = rowCumulativeValue & 0xFF;//lower 8bits
2978 CtbRowMsbValue = CtbRowMsbValue |
2979 (((rowCumulativeValue >> 8) & 0x3) << ((i * 8) + 2));//MSB 2bits
2980 rowCumulativeValue += params->pTileRowHeight[4 * i + 1];
2981
2982 cmd.CtbRowPositionOfTileRow[i].DW0.Ctbpos2I = rowCumulativeValue & 0xFF;//lower 8bits
2983 CtbRowMsbValue = CtbRowMsbValue |
2984 (((rowCumulativeValue >> 8) & 0x3) << ((i * 8) + 4));//MSB 2bits
2985 rowCumulativeValue += params->pTileRowHeight[4 * i + 2];
2986
2987 cmd.CtbRowPositionOfTileRow[i].DW0.Ctbpos3I = rowCumulativeValue & 0xFF;//lower 8bits
2988 CtbRowMsbValue = CtbRowMsbValue |
2989 (((rowCumulativeValue >> 8) & 0x3) << ((i * 8) + 6));//MSB 2bits
2990 rowCumulativeValue += params->pTileRowHeight[4 * i + 3];
2991 }
2992
2993 if (lastDwEleNum)
2994 {
2995 uint32_t i = count;
2996 uint32_t &CtbRowMsbValue = ((i << 3) >> 5) == 0 ? cmd.CtbRowPositionMsb.DW0.Value : cmd.CtbRowPositionMsb.DW1.Value;
2997
2998 if(i < 6)
2999 {
3000 cmd.CtbRowPositionOfTileRow[i].DW0.Ctbpos0I = rowCumulativeValue & 0xFF;//lower 8bits
3001 CtbRowMsbValue = CtbRowMsbValue |
3002 (((rowCumulativeValue >> 8) & 0x3) << ((i * 8) + 0));//MSB 2bits
3003
3004 if (lastDwEleNum > 1)
3005 {
3006 rowCumulativeValue += params->pTileRowHeight[4 * i];
3007 cmd.CtbRowPositionOfTileRow[i].DW0.Ctbpos1I = rowCumulativeValue & 0xFF;//lower 8bits
3008 CtbRowMsbValue = CtbRowMsbValue |
3009 (((rowCumulativeValue >> 8) & 0x3) << ((i * 8) + 2));//MSB 2bits
3010
3011 if (lastDwEleNum > 2)
3012 {
3013 rowCumulativeValue += params->pTileRowHeight[4 * i + 1];
3014 cmd.CtbRowPositionOfTileRow[i].DW0.Ctbpos2I = rowCumulativeValue & 0xFF;//lower 8bits
3015 CtbRowMsbValue = CtbRowMsbValue |
3016 (((rowCumulativeValue >> 8) & 0x3) << ((i * 8) + 4));//MSB 2bits
3017 }
3018 }
3019 }
3020 }
3021
3022 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, sizeof(cmd)));
3023
3024 return eStatus;
3025 }
3026
AddHcpRefIdxStateCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_BATCH_BUFFER batchBuffer,PMHW_VDBOX_HEVC_REF_IDX_PARAMS params)3027 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpRefIdxStateCmd(
3028 PMOS_COMMAND_BUFFER cmdBuffer,
3029 PMHW_BATCH_BUFFER batchBuffer,
3030 PMHW_VDBOX_HEVC_REF_IDX_PARAMS params)
3031 {
3032 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3033
3034 MHW_FUNCTION_ENTER;
3035
3036 MHW_MI_CHK_NULL(params);
3037 mhw_vdbox_hcp_g12_X::HCP_REF_IDX_STATE_CMD *cmd = nullptr;
3038 if (cmdBuffer)
3039 {
3040 cmd = (mhw_vdbox_hcp_g12_X::HCP_REF_IDX_STATE_CMD*)cmdBuffer->pCmdPtr;
3041 }
3042
3043 MHW_MI_CHK_STATUS(MhwVdboxHcpInterfaceGeneric<mhw_vdbox_hcp_g12_X>::AddHcpRefIdxStateCmd(cmdBuffer, batchBuffer, params));
3044
3045 if (!m_decodeInUse)
3046 {
3047 // For SCC
3048 auto paramsG12 = dynamic_cast<PMHW_VDBOX_HEVC_REF_IDX_PARAMS_G12>(params);
3049 MHW_MI_CHK_NULL(paramsG12);
3050
3051 if (paramsG12->bIBCEnabled && (0 == params->ucList) && (cmd != nullptr))
3052 {
3053 MHW_ASSERT(paramsG12->ucRecNotFilteredID < CODECHAL_MAX_CUR_NUM_REF_FRAME_HEVC);
3054 cmd->DW1.NumRefIdxLRefpiclistnumActiveMinus1++;
3055
3056 cmd->Entries[params->ucNumRefForList].DW0.ListEntryLxReferencePictureFrameIdRefaddr07 = paramsG12->ucRecNotFilteredID;
3057 cmd->Entries[params->ucNumRefForList].DW0.ReferencePictureTbValue = 0;
3058 cmd->Entries[params->ucNumRefForList].DW0.Longtermreference = true;
3059 cmd->Entries[params->ucNumRefForList].DW0.FieldPicFlag = 0;
3060 cmd->Entries[params->ucNumRefForList].DW0.BottomFieldFlag = 0;
3061 }
3062 }
3063
3064 return eStatus;
3065 }
3066
AddHcpWeightOffsetStateCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_BATCH_BUFFER batchBuffer,PMHW_VDBOX_HEVC_WEIGHTOFFSET_PARAMS params)3067 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpWeightOffsetStateCmd(
3068 PMOS_COMMAND_BUFFER cmdBuffer,
3069 PMHW_BATCH_BUFFER batchBuffer,
3070 PMHW_VDBOX_HEVC_WEIGHTOFFSET_PARAMS params)
3071 {
3072 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3073
3074 MHW_FUNCTION_ENTER;
3075
3076 MHW_MI_CHK_NULL(params);
3077
3078 mhw_vdbox_hcp_g12_X::HCP_WEIGHTOFFSET_STATE_CMD cmd;
3079
3080 uint8_t i = 0;
3081 uint8_t refIdx = 0;
3082
3083 cmd.DW1.Refpiclistnum = i = params->ucList;
3084
3085 // Luma
3086 for (refIdx = 0; refIdx < CODEC_MAX_NUM_REF_FRAME_HEVC; refIdx++)
3087 {
3088 cmd.Lumaoffsets[refIdx].DW0.DeltaLumaWeightLxI = params->LumaWeights[i][refIdx];
3089 cmd.Lumaoffsets[refIdx].DW0.LumaOffsetLxI = (char)(params->LumaOffsets[i][refIdx] & 0xFF);//lower 8bits
3090 cmd.Lumaoffsets[refIdx].DW0.LumaOffsetLxIMsbyte = (char)((params->LumaOffsets[i][refIdx] >> 8) & 0xFF);//MSB 8bits
3091 }
3092
3093 // Chroma
3094 for (refIdx = 0; refIdx < CODEC_MAX_NUM_REF_FRAME_HEVC; refIdx++)
3095 {
3096 //Cb
3097 cmd.Chromaoffsets[refIdx].DW0.DeltaChromaWeightLxI0 = params->ChromaWeights[i][refIdx][0];
3098 cmd.Chromaoffsets[refIdx].DW0.ChromaoffsetlxI0 = (char)(params->ChromaOffsets[i][refIdx][0] & 0xFF);//lower 8bits
3099
3100 //Cr
3101 cmd.Chromaoffsets[refIdx].DW0.DeltaChromaWeightLxI1 = params->ChromaWeights[i][refIdx][1];
3102 cmd.Chromaoffsets[refIdx].DW0.ChromaoffsetlxI1 = (char)(params->ChromaOffsets[i][refIdx][1] & 0xFF);//lower 8bits
3103 }
3104
3105 for (refIdx = 0; refIdx < CODEC_MAX_NUM_REF_FRAME_HEVC - 1; refIdx += 2)//MSB 8bits
3106 {
3107 cmd.Chromaoffsetsext[refIdx >> 1].DW0.ChromaoffsetlxI0Msbyte = (char)((params->ChromaOffsets[i][refIdx][0] >> 8) & 0xFF);
3108 cmd.Chromaoffsetsext[refIdx >> 1].DW0.ChromaoffsetlxI10Msbyte = (char)((params->ChromaOffsets[i][refIdx + 1][0] >> 8) & 0xFF);
3109 cmd.Chromaoffsetsext[refIdx >> 1].DW0.ChromaoffsetlxI1Msbyte = (char)((params->ChromaOffsets[i][refIdx][1] >> 8) & 0xFF);
3110 cmd.Chromaoffsetsext[refIdx >> 1].DW0.ChromaoffsetlxI11Msbyte = (char)((params->ChromaOffsets[i][refIdx + 1][1] >> 8) & 0xFF);
3111 }
3112
3113 //last one
3114 cmd.Chromaoffsetsext[refIdx >> 1].DW0.ChromaoffsetlxI0Msbyte = (char)((params->ChromaOffsets[i][refIdx][0] >> 8) & 0xFF);//MSB 8bits
3115 cmd.Chromaoffsetsext[refIdx >> 1].DW0.ChromaoffsetlxI1Msbyte = (char)((params->ChromaOffsets[i][refIdx][1] >> 8) & 0xFF);//MSB 8bits
3116
3117 if (cmdBuffer == nullptr && batchBuffer == nullptr)
3118 {
3119 MHW_ASSERTMESSAGE("There was no valid buffer to add the HW command to.");
3120 }
3121
3122 MHW_MI_CHK_STATUS(Mhw_AddCommandCmdOrBB(m_osInterface, cmdBuffer, batchBuffer, &cmd, sizeof(cmd)));
3123
3124 return eStatus;
3125 }
3126
AddHcpFqmStateCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VDBOX_QM_PARAMS params)3127 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpFqmStateCmd(
3128 PMOS_COMMAND_BUFFER cmdBuffer,
3129 PMHW_VDBOX_QM_PARAMS params)
3130 {
3131 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3132
3133 MHW_FUNCTION_ENTER;
3134
3135 MHW_MI_CHK_NULL(m_osInterface);
3136 MHW_MI_CHK_NULL(cmdBuffer);
3137 MHW_MI_CHK_NULL(params);
3138
3139 mhw_vdbox_hcp_g12_X::HCP_FQM_STATE_CMD cmd;
3140
3141 if (params->Standard == CODECHAL_HEVC)
3142 {
3143 MHW_MI_CHK_NULL(params->pHevcIqMatrix);
3144
3145 auto iqMatrix = params->pHevcIqMatrix;
3146 uint16_t *fqMatrix = (uint16_t*)cmd.Quantizermatrix;
3147
3148 /* 4x4 */
3149 for (uint8_t i = 0; i < 32; i++)
3150 {
3151 cmd.Quantizermatrix[i] = 0;
3152 }
3153 for (uint8_t intraInter = 0; intraInter <= 1; intraInter++)
3154 {
3155 cmd.DW1.IntraInter = intraInter;
3156 cmd.DW1.Sizeid = 0;
3157 cmd.DW1.ColorComponent = 0;
3158
3159 for (uint8_t i = 0; i < 16; i++)
3160 {
3161 fqMatrix[i] =
3162 GetReciprocalScalingValue(iqMatrix->List4x4[3 * intraInter][i]);
3163 }
3164
3165 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
3166 }
3167
3168 /* 8x8, 16x16 and 32x32 */
3169 for (uint8_t i = 0; i < 32; i++)
3170 {
3171 cmd.Quantizermatrix[i] = 0;
3172 }
3173 for (uint8_t intraInter = 0; intraInter <= 1; intraInter++)
3174 {
3175 cmd.DW1.IntraInter = intraInter;
3176 cmd.DW1.Sizeid = 1;
3177 cmd.DW1.ColorComponent = 0;
3178
3179 for (uint8_t i = 0; i < 64; i++)
3180 {
3181 fqMatrix[i] =
3182 GetReciprocalScalingValue(iqMatrix->List8x8[3 * intraInter][i]);
3183 }
3184
3185 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
3186 }
3187
3188 /* 16x16 DC */
3189 for (uint8_t i = 0; i < 32; i++)
3190 {
3191 cmd.Quantizermatrix[i] = 0;
3192 }
3193 for (uint8_t intraInter = 0; intraInter <= 1; intraInter++)
3194 {
3195 cmd.DW1.IntraInter = intraInter;
3196 cmd.DW1.Sizeid = 2;
3197 cmd.DW1.ColorComponent = 0;
3198 cmd.DW1.FqmDcValue1Dc = GetReciprocalScalingValue(iqMatrix->ListDC16x16[3 * intraInter]);
3199
3200 for (uint8_t i = 0; i < 64; i++)
3201 {
3202 fqMatrix[i] =
3203 GetReciprocalScalingValue(iqMatrix->List16x16[3 * intraInter][i]);
3204 }
3205
3206 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
3207 }
3208
3209 /* 32x32 DC */
3210 for (uint8_t i = 0; i < 32; i++)
3211 {
3212 cmd.Quantizermatrix[i] = 0;
3213 }
3214 for (uint8_t intraInter = 0; intraInter <= 1; intraInter++)
3215 {
3216 cmd.DW1.IntraInter = intraInter;
3217 cmd.DW1.Sizeid = 3;
3218 cmd.DW1.ColorComponent = 0;
3219 cmd.DW1.FqmDcValue1Dc = GetReciprocalScalingValue(iqMatrix->ListDC32x32[intraInter]);
3220
3221 for (uint8_t i = 0; i < 64; i++)
3222 {
3223 fqMatrix[i] =
3224 GetReciprocalScalingValue(iqMatrix->List32x32[intraInter][i]);
3225 }
3226
3227 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
3228 }
3229 }
3230 else
3231 {
3232 eStatus = MOS_STATUS_INVALID_PARAMETER;
3233 }
3234
3235 return eStatus;
3236 }
3237
AddHcpDecodeSliceStateCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VDBOX_HEVC_SLICE_STATE hevcSliceState)3238 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpDecodeSliceStateCmd(
3239 PMOS_COMMAND_BUFFER cmdBuffer,
3240 PMHW_VDBOX_HEVC_SLICE_STATE hevcSliceState)
3241 {
3242 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3243
3244 MHW_FUNCTION_ENTER;
3245 MHW_MI_CHK_NULL(hevcSliceState);
3246
3247 auto hevcSliceStateG12 = dynamic_cast<PMHW_VDBOX_HEVC_SLICE_STATE_G12>(hevcSliceState);
3248 MHW_MI_CHK_NULL(hevcSliceStateG12);
3249
3250 MHW_MI_CHK_NULL(hevcSliceStateG12->pHevcPicParams);
3251 MHW_MI_CHK_NULL(hevcSliceStateG12->pHevcSliceParams);
3252
3253 auto hevcSliceParams = hevcSliceStateG12->pHevcSliceParams;
3254 auto hevcExtSliceParams = hevcSliceStateG12->pHevcExtSliceParams;
3255 auto hevcPicParams = hevcSliceStateG12->pHevcPicParams;
3256 auto hevcExtPicParams = hevcSliceStateG12->pHevcExtPicParam;
3257 auto hevcSccPicParams = hevcSliceStateG12->pHevcSccPicParam;
3258
3259 uint32_t ctbSize = 1 << (hevcPicParams->log2_diff_max_min_luma_coding_block_size +
3260 hevcPicParams->log2_min_luma_coding_block_size_minus3 + 3);
3261 uint32_t widthInPix = (1 << (hevcPicParams->log2_min_luma_coding_block_size_minus3 + 3)) *
3262 (hevcPicParams->PicWidthInMinCbsY);
3263 uint32_t widthInCtb = MOS_ROUNDUP_DIVIDE(widthInPix, ctbSize);
3264
3265 mhw_vdbox_hcp_g12_X::HCP_SLICE_STATE_CMD *cmd =
3266 (mhw_vdbox_hcp_g12_X::HCP_SLICE_STATE_CMD*)cmdBuffer->pCmdPtr;
3267
3268 MHW_MI_CHK_STATUS(MhwVdboxHcpInterfaceGeneric<mhw_vdbox_hcp_g12_X>::AddHcpDecodeSliceStateCmd(cmdBuffer, hevcSliceStateG12));
3269
3270 int32_t sliceQP = hevcSliceParams->slice_qp_delta + hevcPicParams->init_qp_minus26 + 26;
3271 cmd->DW3.SliceqpSignFlag = (sliceQP >= 0) ? 0 : 1;
3272 cmd->DW3.Sliceqp = ABS(sliceQP);
3273
3274 if (hevcSliceStateG12->bTileInSlice)
3275 {
3276 cmd->DW1.SlicestartctbxOrSliceStartLcuXEncoder = hevcSliceStateG12->u16TileCtbX;
3277 cmd->DW1.SlicestartctbyOrSliceStartLcuYEncoder = hevcSliceStateG12->u16TileCtbY;
3278 if (hevcSliceState->bLastSlice)
3279 {
3280 cmd->DW2.NextslicestartctbxOrNextSliceStartLcuXEncoder = 0;
3281 cmd->DW2.NextslicestartctbyOrNextSliceStartLcuYEncoder = 0;
3282 }
3283 else
3284 {
3285 cmd->DW2.NextslicestartctbxOrNextSliceStartLcuXEncoder = hevcSliceStateG12->u16NextTileCtbX;
3286 cmd->DW2.NextslicestartctbyOrNextSliceStartLcuYEncoder = hevcSliceStateG12->u16NextTileCtbY;
3287 }
3288 }
3289 else
3290 {
3291 cmd->DW1.SlicestartctbxOrSliceStartLcuXEncoder = hevcSliceParams->slice_segment_address % widthInCtb;
3292 cmd->DW1.SlicestartctbyOrSliceStartLcuYEncoder = hevcSliceParams->slice_segment_address / widthInCtb;
3293 }
3294
3295 if (hevcExtPicParams && hevcExtSliceParams)
3296 {
3297 // DW3[23]
3298 if (hevcExtPicParams->PicRangeExtensionFlags.fields.chroma_qp_offset_list_enabled_flag)
3299 {
3300 cmd->DW3.CuChromaQpOffsetEnabledFlag = hevcExtSliceParams->cu_chroma_qp_offset_enabled_flag;
3301 }
3302 }
3303
3304 // DW3[24:25]
3305 cmd->DW3.Lastsliceoftile = hevcSliceStateG12->bLastSliceInTile;
3306 cmd->DW3.Lastsliceoftilecolumn = hevcSliceStateG12->bLastSliceInTileColumn;
3307
3308 if (hevcSliceStateG12->bTileInSlice)
3309 {
3310 cmd->DW5.Sliceheaderlength = hevcSliceStateG12->u16SliceHeaderLength;
3311 cmd->DW7.DependentSliceDueToTileSplit = hevcSliceStateG12->bIsNotFirstTile;
3312 }
3313 else
3314 {
3315 cmd->DW5.Sliceheaderlength = hevcSliceParams->ByteOffsetToSliceData;
3316 }
3317
3318 // Rounding control is not used for decode
3319 cmd->DW6.Value = 0;
3320
3321 if ((hevcSliceState->dwSliceIndex == 0) || !cmd->DW3.DependentSliceFlag)
3322 {
3323 cmd->DW11.Originalslicestartctbx = hevcSliceParams->slice_segment_address % widthInCtb;
3324 cmd->DW11.Originalslicestartctby = hevcSliceParams->slice_segment_address / widthInCtb;
3325 }
3326 else
3327 {
3328 cmd->DW11.Originalslicestartctbx = hevcSliceStateG12->u16OrigCtbX;
3329 cmd->DW11.Originalslicestartctby = hevcSliceStateG12->u16OrigCtbY;
3330 }
3331
3332 if (hevcSccPicParams && hevcExtSliceParams)
3333 {
3334 if (hevcSccPicParams->PicSCCExtensionFlags.fields.pps_slice_act_qp_offsets_present_flag)
3335 {
3336 // DW12
3337 cmd->DW12.SliceActYQpOffset = hevcExtSliceParams->slice_act_y_qp_offset;
3338 cmd->DW12.SliceActCbQpOffset = hevcExtSliceParams->slice_act_cb_qp_offset;
3339 cmd->DW12.SliceActCrQpOffset = hevcExtSliceParams->slice_act_cr_qp_offset;
3340 }
3341
3342 cmd->DW12.UseIntegerMvFlag = hevcExtSliceParams->use_integer_mv_flag;
3343 }
3344
3345 return eStatus;
3346 }
3347
AddHcpEncodeSliceStateCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VDBOX_HEVC_SLICE_STATE hevcSliceState)3348 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpEncodeSliceStateCmd(
3349 PMOS_COMMAND_BUFFER cmdBuffer,
3350 PMHW_VDBOX_HEVC_SLICE_STATE hevcSliceState)
3351 {
3352 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3353
3354 MHW_FUNCTION_ENTER;
3355
3356 MHW_MI_CHK_NULL(hevcSliceState);
3357 MHW_MI_CHK_NULL(hevcSliceState->pEncodeHevcSliceParams);
3358 MHW_MI_CHK_NULL(hevcSliceState->pEncodeHevcPicParams);
3359 MHW_MI_CHK_NULL(hevcSliceState->pEncodeHevcSeqParams);
3360
3361 mhw_vdbox_hcp_g12_X::HCP_SLICE_STATE_CMD cmd;
3362 MOS_COMMAND_BUFFER constructedCmdBuf;
3363
3364 auto hevcSliceParams = hevcSliceState->pEncodeHevcSliceParams;
3365 auto hevcPicParams = hevcSliceState->pEncodeHevcPicParams;
3366 auto hevcSeqParams = hevcSliceState->pEncodeHevcSeqParams;
3367
3368 uint32_t ctbSize = 1 << (hevcSeqParams->log2_max_coding_block_size_minus3 + 3);
3369 uint32_t widthInPix = (1 << (hevcSeqParams->log2_min_coding_block_size_minus3 + 3)) *
3370 (hevcSeqParams->wFrameWidthInMinCbMinus1 + 1);
3371 uint32_t widthInCtb = (widthInPix / ctbSize) +
3372 ((widthInPix % ctbSize) ? 1 : 0); // round up
3373
3374 uint32_t ctbAddr = hevcSliceParams->slice_segment_address;
3375 cmd.DW1.SlicestartctbxOrSliceStartLcuXEncoder = ctbAddr % widthInCtb;
3376 cmd.DW1.SlicestartctbyOrSliceStartLcuYEncoder = ctbAddr / widthInCtb;
3377
3378 if (hevcSliceState->bLastSlice)
3379 {
3380 cmd.DW2.NextslicestartctbxOrNextSliceStartLcuXEncoder = 0;
3381 cmd.DW2.NextslicestartctbyOrNextSliceStartLcuYEncoder = 0;
3382 }
3383 else
3384 {
3385 ctbAddr = hevcSliceParams->slice_segment_address + hevcSliceParams->NumLCUsInSlice;
3386 cmd.DW2.NextslicestartctbxOrNextSliceStartLcuXEncoder = ctbAddr % widthInCtb;
3387 cmd.DW2.NextslicestartctbyOrNextSliceStartLcuYEncoder = ctbAddr / widthInCtb;
3388 }
3389
3390 cmd.DW3.SliceType = hevcSliceParams->slice_type;
3391 cmd.DW3.Lastsliceofpic = hevcSliceState->bLastSlice;
3392 cmd.DW3.SliceqpSignFlag = ((hevcSliceParams->slice_qp_delta + hevcPicParams->QpY) >= 0)
3393 ? 0 : 1; //8 bit will have 0 as sign bit adn 10 bit might have 1 as sign bit depending on Qp
3394 cmd.DW3.DependentSliceFlag = 0; // Not supported on encoder
3395 cmd.DW3.SliceTemporalMvpEnableFlag = hevcSliceParams->slice_temporal_mvp_enable_flag;
3396 if (hevcPicParams->CodingType == I_TYPE)
3397 {
3398 cmd.DW3.SliceTemporalMvpEnableFlag = 0;
3399 }
3400 cmd.DW3.Sliceqp = abs(hevcSliceParams->slice_qp_delta + hevcPicParams->QpY);
3401 cmd.DW3.SliceCbQpOffset = hevcSliceParams->slice_cb_qp_offset;
3402 cmd.DW3.SliceCrQpOffset = hevcSliceParams->slice_cr_qp_offset;
3403
3404 cmd.DW3.Intrareffetchdisable = hevcSliceState->bIntraRefFetchDisable;
3405
3406 cmd.DW4.SliceHeaderDisableDeblockingFilterFlag = hevcSliceState->DeblockingFilterDisable;//hevcSliceParams->slice_deblocking_filter_disable_flag;
3407 cmd.DW4.SliceTcOffsetDiv2OrFinalTcOffsetDiv2Encoder = hevcSliceState->TcOffsetDiv2;//hevcSliceParams->tc_offset_div2;
3408 cmd.DW4.SliceBetaOffsetDiv2OrFinalBetaOffsetDiv2Encoder = hevcSliceState->BetaOffsetDiv2;//hevcSliceParams->beta_offset_div2;
3409 cmd.DW4.SliceLoopFilterAcrossSlicesEnabledFlag = 0;
3410 cmd.DW4.SliceSaoChromaFlag = hevcSliceState->bSaoChromaFlag;
3411 cmd.DW4.SliceSaoLumaFlag = hevcSliceState->bSaoLumaFlag;
3412 cmd.DW4.MvdL1ZeroFlag = 0; // Decoder only - set to 0 for encoder
3413 cmd.DW4.Islowdelay = hevcSliceState->bIsLowDelay;
3414 cmd.DW4.CollocatedFromL0Flag = hevcSliceParams->collocated_from_l0_flag;
3415 cmd.DW4.Chromalog2Weightdenom = (hevcPicParams->weighted_pred_flag || hevcPicParams->weighted_bipred_flag) ?
3416 (hevcPicParams->bEnableGPUWeightedPrediction ? 6 : hevcSliceParams->luma_log2_weight_denom + hevcSliceParams->delta_chroma_log2_weight_denom) : 0;
3417 cmd.DW4.LumaLog2WeightDenom = (hevcPicParams->weighted_pred_flag || hevcPicParams->weighted_bipred_flag) ?
3418 (hevcPicParams->bEnableGPUWeightedPrediction ? 6 : hevcSliceParams->luma_log2_weight_denom) : 0;
3419 cmd.DW4.CabacInitFlag = hevcSliceParams->cabac_init_flag;
3420 cmd.DW4.Maxmergeidx = hevcSliceParams->MaxNumMergeCand - 1;
3421
3422 if (cmd.DW3.SliceTemporalMvpEnableFlag)
3423 {
3424 if (cmd.DW3.SliceType == cmd.SLICE_TYPE_I_SLICE)
3425 {
3426 cmd.DW4.Collocatedrefidx = 0;
3427 }
3428 else
3429 {
3430 // need to check with Ce for DDI issues
3431 uint8_t collocatedFromL0Flag = cmd.DW4.CollocatedFromL0Flag;
3432
3433 uint8_t collocatedRefIndex = hevcPicParams->CollocatedRefPicIndex;
3434 MHW_ASSERT(collocatedRefIndex < CODEC_MAX_NUM_REF_FRAME_HEVC);
3435
3436 uint8_t collocatedFrameIdx = hevcSliceState->pRefIdxMapping[collocatedRefIndex];
3437 MHW_ASSERT(collocatedRefIndex < CODEC_MAX_NUM_REF_FRAME_HEVC);
3438
3439 cmd.DW4.Collocatedrefidx = collocatedFrameIdx;
3440 }
3441 }
3442 else
3443 {
3444 cmd.DW4.Collocatedrefidx = 0;
3445 }
3446
3447 cmd.DW5.Sliceheaderlength = 0; // Decoder only, setting to 0 for Encoder
3448
3449 // For VDENC, cabac zero word insertion is handled by HUC kernel
3450 cmd.DW7.Cabaczerowordinsertionenable = hevcSliceState->bVdencInUse ? 0 : 1;
3451 cmd.DW7.Emulationbytesliceinsertenable = 1;
3452 cmd.DW7.TailInsertionEnable = hevcSliceState->bVdencInUse ? 0 :
3453 ((hevcPicParams->bLastPicInSeq || hevcPicParams->bLastPicInStream) && hevcSliceState->bLastSlice);
3454 cmd.DW7.SlicedataEnable = 1;
3455 cmd.DW7.HeaderInsertionEnable = 1;
3456
3457 cmd.DW8.IndirectPakBseDataStartOffsetWrite = hevcSliceState->dwHeaderBytesInserted;
3458
3459 // Transform skip related parameters
3460 if (hevcSliceState->EncodeHevcTransformSkipParams.Transformskip_enabled)
3461 {
3462 cmd.DW9.TransformskipLambda = hevcSliceState->EncodeHevcTransformSkipParams.Transformskip_lambda;
3463 cmd.DW10.TransformskipNumzerocoeffsFactor0 = hevcSliceState->EncodeHevcTransformSkipParams.Transformskip_Numzerocoeffs_Factor0;
3464 cmd.DW10.TransformskipNumnonzerocoeffsFactor0 = hevcSliceState->EncodeHevcTransformSkipParams.Transformskip_Numnonzerocoeffs_Factor0;
3465 cmd.DW10.TransformskipNumzerocoeffsFactor1 = hevcSliceState->EncodeHevcTransformSkipParams.Transformskip_Numzerocoeffs_Factor1;
3466 cmd.DW10.TransformskipNumnonzerocoeffsFactor1 = hevcSliceState->EncodeHevcTransformSkipParams.Transformskip_Numnonzerocoeffs_Factor1;
3467 }
3468
3469 if (hevcSliceState->bLastSlice)
3470 {
3471 cmd.DW2.NextslicestartctbxOrNextSliceStartLcuXEncoder = 0;
3472 cmd.DW2.NextslicestartctbyOrNextSliceStartLcuYEncoder = 0;
3473 }
3474 else
3475 {
3476 if(hevcPicParams->tiles_enabled_flag)
3477 {
3478 // when tile is enabled, need to consider if slice is within one tile
3479 cmd.DW2.NextslicestartctbxOrNextSliceStartLcuXEncoder = hevcSliceParams[1].slice_segment_address % widthInCtb;
3480 cmd.DW2.NextslicestartctbyOrNextSliceStartLcuYEncoder = hevcSliceParams[1].slice_segment_address / widthInCtb;
3481 }
3482 else
3483 {
3484 ctbAddr = hevcSliceParams->slice_segment_address + hevcSliceParams->NumLCUsInSlice;
3485 cmd.DW2.NextslicestartctbxOrNextSliceStartLcuXEncoder = ctbAddr % widthInCtb;
3486 cmd.DW2.NextslicestartctbyOrNextSliceStartLcuYEncoder = ctbAddr / widthInCtb;
3487 }
3488 }
3489
3490
3491 cmd.DW4.SliceLoopFilterAcrossSlicesEnabledFlag = hevcPicParams->loop_filter_across_slices_flag;
3492 cmd.DW3.Lastsliceoftile = hevcSliceState->bLastSliceInTile;
3493 cmd.DW3.Lastsliceoftilecolumn = hevcSliceState->bLastSliceInTileColumn;
3494
3495 if (hevcSliceState->bVdencInUse)
3496 {
3497 // Currently setting to defaults used in prototype
3498 cmd.DW6.Roundinter = 4;
3499 cmd.DW6.Roundintra = 10;
3500 }
3501 else
3502 {
3503 cmd.DW6.Roundinter = hevcSliceState->RoundingInter;
3504 cmd.DW6.Roundintra = hevcSliceState->RoundingIntra;
3505 }
3506
3507 MHW_MI_CHK_STATUS(Mhw_AddCommandCmdOrBB(m_osInterface, cmdBuffer, hevcSliceState->pBatchBufferForPakSlices, &cmd, sizeof(cmd)));
3508
3509 return eStatus;
3510 }
3511
AddHcpPakInsertObject(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VDBOX_PAK_INSERT_PARAMS params)3512 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpPakInsertObject(
3513 PMOS_COMMAND_BUFFER cmdBuffer,
3514 PMHW_VDBOX_PAK_INSERT_PARAMS params)
3515 {
3516 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3517
3518 MHW_FUNCTION_ENTER;
3519
3520 MHW_MI_CHK_NULL(params);
3521
3522 mhw_vdbox_hcp_g12_X::HCP_PAK_INSERT_OBJECT_CMD cmd;
3523
3524 uint32_t dwordsUsed = cmd.dwSize;
3525
3526 if (params->bLastPicInSeq && params->bLastPicInStream)
3527 {
3528 uint32_t dwPadding[3];
3529
3530 dwordsUsed += sizeof(dwPadding) / sizeof(dwPadding[0]);
3531
3532 cmd.DW0.DwordLength = OP_LENGTH(dwordsUsed);
3533 cmd.DW1.Headerlengthexcludefrmsize = 0;
3534 cmd.DW1.EndofsliceflagLastdstdatainsertcommandflag = 1;
3535 cmd.DW1.LastheaderflagLastsrcheaderdatainsertcommandflag = 1;
3536 cmd.DW1.EmulationflagEmulationbytebitsinsertenable = 0;
3537 cmd.DW1.SkipemulbytecntSkipEmulationByteCount = 0;
3538 cmd.DW1.DatabitsinlastdwSrcdataendingbitinclusion50 = 16;
3539 cmd.DW1.DatabyteoffsetSrcdatastartingbyteoffset10 = 0;
3540 cmd.DW1.IndirectPayloadEnable = 0;
3541
3542 MHW_MI_CHK_STATUS(Mhw_AddCommandCmdOrBB(m_osInterface, cmdBuffer, params->pBatchBufferForPakSlices, &cmd, cmd.byteSize));
3543
3544 dwPadding[0] = (uint32_t)((1 << 16) | ((HEVC_NAL_UT_EOS << 1) << 24));
3545 dwPadding[1] = (1L | (1L << 24));
3546 dwPadding[2] = (HEVC_NAL_UT_EOB << 1) | (1L << 8);
3547 MHW_MI_CHK_STATUS(Mhw_AddCommandCmdOrBB(m_osInterface, cmdBuffer, params->pBatchBufferForPakSlices, &dwPadding[0], sizeof(dwPadding)));
3548 }
3549 else
3550 if (params->bLastPicInSeq || params->bLastPicInStream)
3551 {
3552 uint32_t dwLastPicInSeqData[2], dwLastPicInStreamData[2];
3553
3554 dwordsUsed += params->bLastPicInSeq * 2 + params->bLastPicInStream * 2;
3555
3556 cmd.DW0.DwordLength = OP_LENGTH(dwordsUsed);
3557 cmd.DW1.Headerlengthexcludefrmsize = 0;
3558 cmd.DW1.EndofsliceflagLastdstdatainsertcommandflag = 1;
3559 cmd.DW1.LastheaderflagLastsrcheaderdatainsertcommandflag = 1;
3560 cmd.DW1.EmulationflagEmulationbytebitsinsertenable = 0;
3561 cmd.DW1.SkipemulbytecntSkipEmulationByteCount = 0;
3562 cmd.DW1.DatabitsinlastdwSrcdataendingbitinclusion50 = 8;
3563 cmd.DW1.DatabyteoffsetSrcdatastartingbyteoffset10 = 0;
3564 cmd.DW1.IndirectPayloadEnable = 0;
3565
3566 MHW_MI_CHK_STATUS(Mhw_AddCommandCmdOrBB(m_osInterface, cmdBuffer, params->pBatchBufferForPakSlices, &cmd, cmd.byteSize));
3567
3568 if (params->bLastPicInSeq)
3569 {
3570 dwLastPicInSeqData[0] = (uint32_t)((1 << 16) | ((HEVC_NAL_UT_EOS << 1) << 24));
3571 dwLastPicInSeqData[1] = 1; // nuh_temporal_id_plus1
3572 MHW_MI_CHK_STATUS(Mhw_AddCommandCmdOrBB(m_osInterface, cmdBuffer, params->pBatchBufferForPakSlices, &dwLastPicInSeqData[0], sizeof(dwLastPicInSeqData)));
3573 }
3574
3575 if (params->bLastPicInStream)
3576 {
3577 dwLastPicInStreamData[0] = (uint32_t)((1 << 16) | ((HEVC_NAL_UT_EOB << 1) << 24));
3578 dwLastPicInStreamData[1] = 1; // nuh_temporal_id_plus1
3579 MHW_MI_CHK_STATUS(Mhw_AddCommandCmdOrBB(m_osInterface, cmdBuffer, params->pBatchBufferForPakSlices, &dwLastPicInStreamData[0], sizeof(dwLastPicInStreamData)));
3580 }
3581 }
3582 else
3583 {
3584 uint32_t byteSize = (params->dwBitSize + 7) >> 3;
3585 uint32_t dataBitsInLastDw = params->dwBitSize % 32;
3586 if (dataBitsInLastDw == 0)
3587 {
3588 dataBitsInLastDw = 32;
3589 }
3590
3591 dwordsUsed += (MOS_ALIGN_CEIL(byteSize, sizeof(uint32_t))) / sizeof(uint32_t);
3592 cmd.DW0.DwordLength = OP_LENGTH(dwordsUsed);
3593 cmd.DW1.Headerlengthexcludefrmsize = 0;
3594 cmd.DW1.EndofsliceflagLastdstdatainsertcommandflag = params->bEndOfSlice;
3595 cmd.DW1.LastheaderflagLastsrcheaderdatainsertcommandflag = params->bLastHeader;
3596 cmd.DW1.EmulationflagEmulationbytebitsinsertenable = params->bEmulationByteBitsInsert;
3597 cmd.DW1.SkipemulbytecntSkipEmulationByteCount = params->uiSkipEmulationCheckCount;
3598 cmd.DW1.SliceHeaderIndicator = params->bResetBitstreamStartingPos;
3599 cmd.DW1.DatabitsinlastdwSrcdataendingbitinclusion50 = dataBitsInLastDw;
3600 cmd.DW1.DatabyteoffsetSrcdatastartingbyteoffset10 = 0;
3601 cmd.DW1.IndirectPayloadEnable = 0;
3602
3603 MHW_MI_CHK_STATUS(Mhw_AddCommandCmdOrBB(m_osInterface, cmdBuffer, params->pBatchBufferForPakSlices, &cmd, cmd.byteSize));
3604
3605 if (byteSize)
3606 {
3607 MHW_MI_CHK_NULL(params->pBsBuffer);
3608 MHW_MI_CHK_NULL(params->pBsBuffer->pBase);
3609 uint8_t *data = (uint8_t*)(params->pBsBuffer->pBase + params->dwOffset);
3610 MHW_MI_CHK_STATUS(Mhw_AddCommandCmdOrBB(m_osInterface, cmdBuffer, params->pBatchBufferForPakSlices, data, byteSize));
3611 }
3612 }
3613
3614 return eStatus;
3615 }
3616
AddHcpVp9PicStateCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_BATCH_BUFFER batchBuffer,PMHW_VDBOX_VP9_PIC_STATE params)3617 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpVp9PicStateCmd(
3618 PMOS_COMMAND_BUFFER cmdBuffer,
3619 PMHW_BATCH_BUFFER batchBuffer,
3620 PMHW_VDBOX_VP9_PIC_STATE params)
3621 {
3622 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3623
3624 MHW_MI_CHK_NULL(params);
3625 MHW_MI_CHK_NULL(params->pVp9PicParams);
3626
3627 mhw_vdbox_hcp_g12_X::HCP_VP9_PIC_STATE_CMD cmd;
3628 auto vp9PicParams = params->pVp9PicParams;
3629 auto vp9RefList = params->ppVp9RefList;
3630
3631 cmd.DW0.DwordLength = mhw_vdbox_hcp_g12_X::GetOpLength(12); //VP9_PIC_STATE command is common for both Decoder and Encoder. Decoder uses only 12 DWORDS of the generated 33 DWORDS
3632
3633 uint32_t curFrameWidth = vp9PicParams->FrameWidthMinus1 + 1;
3634 uint32_t curFrameHeight = vp9PicParams->FrameHeightMinus1 + 1;
3635 bool isScaling = (curFrameWidth == params->dwPrevFrmWidth) && (curFrameHeight == params->dwPrevFrmHeight) ? false : true;
3636
3637 cmd.DW1.FrameWidthInPixelsMinus1 = MOS_ALIGN_CEIL(curFrameWidth, CODEC_VP9_MIN_BLOCK_WIDTH) - 1;
3638 cmd.DW1.FrameHeightInPixelsMinus1 = MOS_ALIGN_CEIL(curFrameHeight, CODEC_VP9_MIN_BLOCK_WIDTH) - 1;
3639
3640 cmd.DW2.FrameType = vp9PicParams->PicFlags.fields.frame_type;
3641 cmd.DW2.AdaptProbabilitiesFlag = !vp9PicParams->PicFlags.fields.error_resilient_mode && !vp9PicParams->PicFlags.fields.frame_parallel_decoding_mode;
3642 cmd.DW2.IntraonlyFlag = vp9PicParams->PicFlags.fields.intra_only;
3643 cmd.DW2.RefreshFrameContext = vp9PicParams->PicFlags.fields.refresh_frame_context;
3644 cmd.DW2.ErrorResilientMode = vp9PicParams->PicFlags.fields.error_resilient_mode;
3645 cmd.DW2.FrameParallelDecodingMode = vp9PicParams->PicFlags.fields.frame_parallel_decoding_mode;
3646 cmd.DW2.FilterLevel = vp9PicParams->filter_level;
3647 cmd.DW2.SharpnessLevel = vp9PicParams->sharpness_level;
3648 cmd.DW2.SegmentationEnabled = vp9PicParams->PicFlags.fields.segmentation_enabled;
3649 cmd.DW2.SegmentationUpdateMap = cmd.DW2.SegmentationEnabled && vp9PicParams->PicFlags.fields.segmentation_update_map;
3650 cmd.DW2.LosslessMode = vp9PicParams->PicFlags.fields.LosslessFlag;
3651 cmd.DW2.SegmentIdStreamoutEnable = cmd.DW2.SegmentationUpdateMap;
3652
3653 uint8_t segmentIDStreaminEnable = 0;
3654 if (vp9PicParams->PicFlags.fields.intra_only ||
3655 (vp9PicParams->PicFlags.fields.frame_type == CODEC_VP9_KEY_FRAME)) {
3656 segmentIDStreaminEnable = 1;
3657 } else if (vp9PicParams->PicFlags.fields.segmentation_enabled) {
3658 if (!vp9PicParams->PicFlags.fields.segmentation_update_map)
3659 segmentIDStreaminEnable = 1;
3660 else if (vp9PicParams->PicFlags.fields.segmentation_temporal_update)
3661 segmentIDStreaminEnable = 1;
3662 }
3663 if (vp9PicParams->PicFlags.fields.error_resilient_mode) {
3664 segmentIDStreaminEnable = 1;
3665 }
3666 // Resolution change will reset the segment ID buffer
3667 if (isScaling)
3668 {
3669 segmentIDStreaminEnable = 1;
3670 }
3671
3672 cmd.DW2.SegmentIdStreaminEnable = segmentIDStreaminEnable;
3673
3674 cmd.DW3.Log2TileRow = vp9PicParams->log2_tile_rows; // No need to minus 1 here.
3675 cmd.DW3.Log2TileColumn = vp9PicParams->log2_tile_columns; // No need to minus 1 here.
3676 if (vp9PicParams->subsampling_x == 1 && vp9PicParams->subsampling_y == 1)
3677 {
3678 //4:2:0
3679 cmd.DW3.ChromaSamplingFormat = 0;
3680 }
3681 else if (vp9PicParams->subsampling_x == 1 && vp9PicParams->subsampling_y == 0)
3682 {
3683 //4:2:2
3684 cmd.DW3.ChromaSamplingFormat = 1;
3685 }
3686 else if (vp9PicParams->subsampling_x == 0 && vp9PicParams->subsampling_y == 0)
3687 {
3688 //4:4:4
3689 cmd.DW3.ChromaSamplingFormat = 2;
3690 }
3691 cmd.DW3.Bitdepthminus8 = vp9PicParams->BitDepthMinus8;
3692 cmd.DW3.ProfileLevel = vp9PicParams->profile;
3693
3694 cmd.DW10.UncompressedHeaderLengthInBytes70 = vp9PicParams->UncompressedHeaderLengthInBytes;
3695 cmd.DW10.FirstPartitionSizeInBytes150 = vp9PicParams->FirstPartitionSize;
3696
3697 if (vp9PicParams->PicFlags.fields.frame_type && !vp9PicParams->PicFlags.fields.intra_only)
3698 {
3699 PCODEC_PICTURE refFrameList = &(vp9PicParams->RefFrameList[0]);
3700
3701 uint8_t lastRefPicIndex = refFrameList[vp9PicParams->PicFlags.fields.LastRefIdx].FrameIdx;
3702 uint32_t lastRefFrameWidth = vp9RefList[lastRefPicIndex]->dwFrameWidth;
3703 uint32_t lastRefFrameHeight = vp9RefList[lastRefPicIndex]->dwFrameHeight;
3704
3705 uint8_t goldenRefPicIndex = refFrameList[vp9PicParams->PicFlags.fields.GoldenRefIdx].FrameIdx;
3706 uint32_t goldenRefFrameWidth = vp9RefList[goldenRefPicIndex]->dwFrameWidth;
3707 uint32_t goldenRefFrameHeight = vp9RefList[goldenRefPicIndex]->dwFrameHeight;
3708
3709 uint8_t altRefPicIndex = refFrameList[vp9PicParams->PicFlags.fields.AltRefIdx].FrameIdx;
3710 uint32_t altRefFrameWidth = vp9RefList[altRefPicIndex]->dwFrameWidth;
3711 uint32_t altRefFrameHeight = vp9RefList[altRefPicIndex]->dwFrameHeight;
3712
3713 cmd.DW2.AllowHiPrecisionMv = vp9PicParams->PicFlags.fields.allow_high_precision_mv;
3714 cmd.DW2.McompFilterType = vp9PicParams->PicFlags.fields.mcomp_filter_type;
3715 cmd.DW2.SegmentationTemporalUpdate = cmd.DW2.SegmentationUpdateMap && vp9PicParams->PicFlags.fields.segmentation_temporal_update;
3716
3717 cmd.DW2.RefFrameSignBias02 = vp9PicParams->PicFlags.fields.LastRefSignBias |
3718 (vp9PicParams->PicFlags.fields.GoldenRefSignBias << 1) |
3719 (vp9PicParams->PicFlags.fields.AltRefSignBias << 2);
3720
3721 cmd.DW2.LastFrameType = !params->PrevFrameParams.fields.KeyFrame;
3722
3723 // Reset UsePrevInFindMvReferences to zero if last picture has a different size,
3724 // Current picture is error-resilient mode, Last picture was intra_only or keyframe,
3725 // Last picture was not a displayed picture.
3726 cmd.DW2.UsePrevInFindMvReferences =
3727 !(vp9PicParams->PicFlags.fields.error_resilient_mode ||
3728 params->PrevFrameParams.fields.KeyFrame ||
3729 params->PrevFrameParams.fields.IntraOnly ||
3730 !params->PrevFrameParams.fields.Display);
3731 // Reset UsePrevInFindMvReferences in case of resolution change on inter frames
3732 if (isScaling) {
3733 cmd.DW2.UsePrevInFindMvReferences = 0;
3734 }
3735
3736 cmd.DW4.HorizontalScaleFactorForLast = (lastRefFrameWidth * m_vp9ScalingFactor) / curFrameWidth;
3737 cmd.DW4.VerticalScaleFactorForLast = (lastRefFrameHeight * m_vp9ScalingFactor) / curFrameHeight;
3738
3739 cmd.DW5.HorizontalScaleFactorForGolden = (goldenRefFrameWidth * m_vp9ScalingFactor) / curFrameWidth;
3740 cmd.DW5.VerticalScaleFactorForGolden = (goldenRefFrameHeight * m_vp9ScalingFactor) / curFrameHeight;
3741
3742 cmd.DW6.HorizontalScaleFactorForAltref = (altRefFrameWidth * m_vp9ScalingFactor) / curFrameWidth;
3743 cmd.DW6.VerticalScaleFactorForAltref = (altRefFrameHeight * m_vp9ScalingFactor) / curFrameHeight;
3744
3745 cmd.DW7.LastFrameWidthInPixelsMinus1 = lastRefFrameWidth - 1;
3746 cmd.DW7.LastFrameHieghtInPixelsMinus1 = lastRefFrameHeight - 1;
3747
3748 cmd.DW8.GoldenFrameWidthInPixelsMinus1 = goldenRefFrameWidth - 1;
3749 cmd.DW8.GoldenFrameHieghtInPixelsMinus1 = goldenRefFrameHeight - 1;
3750
3751 cmd.DW9.AltrefFrameWidthInPixelsMinus1 = altRefFrameWidth - 1;
3752 cmd.DW9.AltrefFrameHieghtInPixelsMinus1 = altRefFrameHeight - 1;
3753 }
3754
3755 MHW_MI_CHK_STATUS(Mhw_AddCommandCmdOrBB(m_osInterface, cmdBuffer, batchBuffer, &cmd, cmd.byteSize));
3756
3757 return eStatus;
3758 }
3759
AddHcpVp9PicStateEncCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_BATCH_BUFFER batchBuffer,PMHW_VDBOX_VP9_ENCODE_PIC_STATE params)3760 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpVp9PicStateEncCmd(
3761 PMOS_COMMAND_BUFFER cmdBuffer,
3762 PMHW_BATCH_BUFFER batchBuffer,
3763 PMHW_VDBOX_VP9_ENCODE_PIC_STATE params)
3764 {
3765 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3766
3767 MHW_FUNCTION_ENTER;
3768
3769 MHW_MI_CHK_NULL(params);
3770 MHW_MI_CHK_NULL(params->pVp9PicParams);
3771 MHW_MI_CHK_NULL(params->pVp9SeqParams);
3772 MHW_MI_CHK_NULL(params->ppVp9RefList);
3773
3774 mhw_vdbox_hcp_g12_X::HCP_VP9_PIC_STATE_CMD cmd;
3775
3776 auto vp9PicParams = params->pVp9PicParams;
3777 auto vp9RefList = params->ppVp9RefList;
3778 auto vp9SeqParams = params->pVp9SeqParams;
3779
3780 cmd.DW1.FrameWidthInPixelsMinus1 = MOS_ALIGN_CEIL(vp9PicParams->SrcFrameWidthMinus1 + 1, CODEC_VP9_MIN_BLOCK_WIDTH) - 1;
3781 cmd.DW1.FrameHeightInPixelsMinus1 = MOS_ALIGN_CEIL(vp9PicParams->SrcFrameHeightMinus1 + 1, CODEC_VP9_MIN_BLOCK_WIDTH) - 1;
3782
3783 cmd.DW2.FrameType = vp9PicParams->PicFlags.fields.frame_type;
3784 cmd.DW2.AdaptProbabilitiesFlag = !vp9PicParams->PicFlags.fields.error_resilient_mode && !vp9PicParams->PicFlags.fields.frame_parallel_decoding_mode;
3785 cmd.DW2.IntraonlyFlag = vp9PicParams->PicFlags.fields.intra_only;
3786 cmd.DW2.AllowHiPrecisionMv = vp9PicParams->PicFlags.fields.allow_high_precision_mv;
3787 cmd.DW2.McompFilterType = vp9PicParams->PicFlags.fields.mcomp_filter_type;
3788
3789 cmd.DW2.RefFrameSignBias02 = vp9PicParams->RefFlags.fields.LastRefSignBias |
3790 (vp9PicParams->RefFlags.fields.GoldenRefSignBias << 1) |
3791 (vp9PicParams->RefFlags.fields.AltRefSignBias << 2);
3792
3793 cmd.DW2.HybridPredictionMode = vp9PicParams->PicFlags.fields.comp_prediction_mode == 2;
3794 cmd.DW2.SelectableTxMode = params->ucTxMode == 4;
3795 cmd.DW2.RefreshFrameContext = vp9PicParams->PicFlags.fields.refresh_frame_context;
3796 cmd.DW2.ErrorResilientMode = vp9PicParams->PicFlags.fields.error_resilient_mode;
3797 cmd.DW2.FrameParallelDecodingMode = vp9PicParams->PicFlags.fields.frame_parallel_decoding_mode;
3798 cmd.DW2.FilterLevel = vp9PicParams->filter_level;
3799 cmd.DW2.SharpnessLevel = vp9PicParams->sharpness_level;
3800 cmd.DW2.SegmentationEnabled = vp9PicParams->PicFlags.fields.segmentation_enabled;
3801 cmd.DW2.SegmentationUpdateMap = vp9PicParams->PicFlags.fields.segmentation_update_map;
3802 cmd.DW2.SegmentationTemporalUpdate = vp9PicParams->PicFlags.fields.segmentation_temporal_update;
3803 cmd.DW2.LosslessMode = vp9PicParams->PicFlags.fields.LosslessFlag;
3804
3805 cmd.DW3.Log2TileColumn = vp9PicParams->log2_tile_columns;
3806 cmd.DW3.Log2TileRow = vp9PicParams->log2_tile_rows;
3807 cmd.DW3.SseEnable = params->bSSEEnable;
3808 // Gen 11 REXT inputs for chroma formats and bit depth
3809 cmd.DW3.ChromaSamplingFormat = vp9SeqParams->SeqFlags.fields.EncodedFormat;
3810 switch (vp9SeqParams->SeqFlags.fields.EncodedBitDepth)
3811 {
3812 case VP9_ENCODED_BIT_DEPTH_8:
3813 cmd.DW3.Bitdepthminus8 = 0;
3814 break;
3815 case VP9_ENCODED_BIT_DEPTH_10:
3816 cmd.DW3.Bitdepthminus8 = 2;
3817 break;
3818 default:
3819 cmd.DW3.Bitdepthminus8 = 0;
3820 break;
3821 }
3822
3823 if (vp9PicParams->PicFlags.fields.frame_type && !vp9PicParams->PicFlags.fields.intra_only)
3824 {
3825 uint32_t curFrameWidth = vp9PicParams->SrcFrameWidthMinus1 + 1;
3826 uint32_t curFrameHeight = vp9PicParams->SrcFrameHeightMinus1 + 1;
3827
3828 PCODEC_PICTURE refFrameList = &(vp9PicParams->RefFrameList[0]);
3829
3830 cmd.DW2.LastFrameType = !params->PrevFrameParams.fields.KeyFrame;
3831
3832 cmd.DW2.UsePrevInFindMvReferences = vp9PicParams->PicFlags.fields.error_resilient_mode ||
3833 params->PrevFrameParams.fields.KeyFrame ||
3834 params->PrevFrameParams.fields.IntraOnly ||
3835 !params->PrevFrameParams.fields.Display ||
3836 (curFrameWidth != params->dwPrevFrmWidth) ||
3837 (curFrameHeight != params->dwPrevFrmHeight) ? 0 : 1;
3838
3839 if ((vp9PicParams->RefFlags.fields.ref_frame_ctrl_l0 & 0x01) || (vp9PicParams->RefFlags.fields.ref_frame_ctrl_l1 & 0x01))
3840 {
3841 MHW_ASSERT(!CodecHal_PictureIsInvalid(refFrameList[vp9PicParams->RefFlags.fields.LastRefIdx]));
3842
3843 uint8_t lastRefPicIndex = refFrameList[vp9PicParams->RefFlags.fields.LastRefIdx].FrameIdx;
3844 uint32_t lastRefFrameWidth = 0;
3845 uint32_t lastRefFrameHeight = 0;
3846 if (!params->bUseDysRefSurface)
3847 {
3848 lastRefFrameWidth = vp9RefList[lastRefPicIndex]->dwFrameWidth;
3849 lastRefFrameHeight = vp9RefList[lastRefPicIndex]->dwFrameHeight;
3850 }
3851 else
3852 {
3853 lastRefFrameWidth = curFrameWidth;
3854 lastRefFrameHeight = curFrameHeight;
3855 }
3856
3857 cmd.DW4.HorizontalScaleFactorForLast = (lastRefFrameWidth * m_vp9ScalingFactor) / curFrameWidth;
3858 cmd.DW4.VerticalScaleFactorForLast = (lastRefFrameHeight * m_vp9ScalingFactor) / curFrameHeight;
3859
3860 cmd.DW7.LastFrameWidthInPixelsMinus1 = lastRefFrameWidth - 1;
3861 cmd.DW7.LastFrameHieghtInPixelsMinus1 = lastRefFrameHeight - 1;
3862 }
3863
3864 if ((vp9PicParams->RefFlags.fields.ref_frame_ctrl_l0 & 0x02) || (vp9PicParams->RefFlags.fields.ref_frame_ctrl_l1 & 0x02))
3865 {
3866 MHW_ASSERT(!CodecHal_PictureIsInvalid(refFrameList[vp9PicParams->RefFlags.fields.GoldenRefIdx]));
3867
3868 uint8_t goldenRefPicIndex = refFrameList[vp9PicParams->RefFlags.fields.GoldenRefIdx].FrameIdx;
3869 uint32_t goldenRefFrameWidth = 0;
3870 uint32_t goldenRefFrameHeight = 0;
3871 if (!params->bUseDysRefSurface)
3872 {
3873 goldenRefFrameWidth = vp9RefList[goldenRefPicIndex]->dwFrameWidth;
3874 goldenRefFrameHeight = vp9RefList[goldenRefPicIndex]->dwFrameHeight;
3875 }
3876 else
3877 {
3878 goldenRefFrameWidth = curFrameWidth;
3879 goldenRefFrameHeight = curFrameHeight;
3880 }
3881
3882 cmd.DW5.HorizontalScaleFactorForGolden = (goldenRefFrameWidth * m_vp9ScalingFactor) / curFrameWidth;
3883 cmd.DW5.VerticalScaleFactorForGolden = (goldenRefFrameHeight * m_vp9ScalingFactor) / curFrameHeight;
3884
3885 cmd.DW8.GoldenFrameWidthInPixelsMinus1 = goldenRefFrameWidth - 1;
3886 cmd.DW8.GoldenFrameHieghtInPixelsMinus1 = goldenRefFrameHeight - 1;
3887 }
3888
3889 if ((vp9PicParams->RefFlags.fields.ref_frame_ctrl_l0 & 0x04) || (vp9PicParams->RefFlags.fields.ref_frame_ctrl_l1 & 0x04))
3890 {
3891 MHW_ASSERT(!CodecHal_PictureIsInvalid(refFrameList[vp9PicParams->RefFlags.fields.AltRefIdx]));
3892
3893 uint8_t altRefPicIndex = refFrameList[vp9PicParams->RefFlags.fields.AltRefIdx].FrameIdx;
3894 uint32_t altRefFrameWidth = 0;
3895 uint32_t altRefFrameHeight = 0;
3896 if (!params->bUseDysRefSurface)
3897 {
3898 altRefFrameWidth = vp9RefList[altRefPicIndex]->dwFrameWidth;
3899 altRefFrameHeight = vp9RefList[altRefPicIndex]->dwFrameHeight;
3900 }
3901 else
3902 {
3903 altRefFrameWidth = curFrameWidth;
3904 altRefFrameHeight = curFrameHeight;
3905 }
3906
3907 cmd.DW6.HorizontalScaleFactorForAltref = (altRefFrameWidth * m_vp9ScalingFactor) / curFrameWidth;
3908 cmd.DW6.VerticalScaleFactorForAltref = (altRefFrameHeight * m_vp9ScalingFactor) / curFrameHeight;
3909
3910 cmd.DW9.AltrefFrameWidthInPixelsMinus1 = altRefFrameWidth - 1;
3911 cmd.DW9.AltrefFrameHieghtInPixelsMinus1 = altRefFrameHeight - 1;
3912 }
3913 }
3914
3915 cmd.DW13.BaseQIndexSameAsLumaAc = vp9PicParams->LumaACQIndex;
3916 cmd.DW13.HeaderInsertionEnable = 1;
3917
3918 cmd.DW14.ChromaacQindexdelta = Convert2SignMagnitude(vp9PicParams->ChromaACQIndexDelta, 5);
3919 cmd.DW14.ChromadcQindexdelta = Convert2SignMagnitude(vp9PicParams->ChromaDCQIndexDelta, 5);
3920 cmd.DW14.LumaDcQIndexDelta = Convert2SignMagnitude(vp9PicParams->LumaDCQIndexDelta, 5);
3921
3922 cmd.DW15.LfRefDelta0 = Convert2SignMagnitude(vp9PicParams->LFRefDelta[0], 7);
3923 cmd.DW15.LfRefDelta1 = Convert2SignMagnitude(vp9PicParams->LFRefDelta[1], 7);
3924 cmd.DW15.LfRefDelta2 = Convert2SignMagnitude(vp9PicParams->LFRefDelta[2], 7);
3925 cmd.DW15.LfRefDelta3 = Convert2SignMagnitude(vp9PicParams->LFRefDelta[3], 7);
3926
3927 cmd.DW16.LfModeDelta0 = Convert2SignMagnitude(vp9PicParams->LFModeDelta[0], 7);
3928 cmd.DW16.LfModeDelta1 = Convert2SignMagnitude(vp9PicParams->LFModeDelta[1], 7);
3929
3930 cmd.DW17.Bitoffsetforlfrefdelta = vp9PicParams->BitOffsetForLFRefDelta;
3931 cmd.DW17.Bitoffsetforlfmodedelta = vp9PicParams->BitOffsetForLFModeDelta;
3932 cmd.DW18.Bitoffsetforlflevel = vp9PicParams->BitOffsetForLFLevel;
3933 cmd.DW18.Bitoffsetforqindex = vp9PicParams->BitOffsetForQIndex;
3934 cmd.DW32.Bitoffsetforfirstpartitionsize = vp9PicParams->BitOffsetForFirstPartitionSize;
3935
3936 cmd.DW19.VdencPakOnlyPass = params->bVdencPakOnlyPassFlag;
3937
3938 MHW_MI_CHK_STATUS(Mhw_AddCommandCmdOrBB(m_osInterface, cmdBuffer, batchBuffer, &cmd, sizeof(cmd)));
3939
3940 return eStatus;
3941 }
3942
AddHcpVp9SegmentStateCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_BATCH_BUFFER batchBuffer,PMHW_VDBOX_VP9_SEGMENT_STATE params)3943 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpVp9SegmentStateCmd(
3944 PMOS_COMMAND_BUFFER cmdBuffer,
3945 PMHW_BATCH_BUFFER batchBuffer,
3946 PMHW_VDBOX_VP9_SEGMENT_STATE params)
3947 {
3948 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3949
3950 MHW_MI_CHK_NULL(params);
3951
3952 mhw_vdbox_hcp_g12_X::HCP_VP9_SEGMENT_STATE_CMD cmd;
3953
3954 cmd.DW1.SegmentId = params->ucCurrentSegmentId;
3955
3956 if (!m_decodeInUse)
3957 {
3958 CODEC_VP9_ENCODE_SEG_PARAMS vp9SegData;
3959
3960 vp9SegData = params->pVp9EncodeSegmentParams->SegData[params->ucCurrentSegmentId];
3961
3962 cmd.DW2.SegmentSkipped = vp9SegData.SegmentFlags.fields.SegmentSkipped;
3963 cmd.DW2.SegmentReference = vp9SegData.SegmentFlags.fields.SegmentReference;
3964 cmd.DW2.SegmentReferenceEnabled = vp9SegData.SegmentFlags.fields.SegmentReferenceEnabled;
3965
3966 cmd.DW7.SegmentLfLevelDeltaEncodeModeOnly = Convert2SignMagnitude(vp9SegData.SegmentLFLevelDelta, 7);
3967 cmd.DW7.SegmentQindexDeltaEncodeModeOnly = Convert2SignMagnitude(vp9SegData.SegmentQIndexDelta, 9);
3968 }
3969 else
3970 {
3971 CODEC_VP9_SEG_PARAMS vp9SegData;
3972
3973 vp9SegData = params->pVp9SegmentParams->SegData[params->ucCurrentSegmentId];
3974
3975 cmd.DW2.SegmentSkipped = vp9SegData.SegmentFlags.fields.SegmentReferenceSkipped;
3976 cmd.DW2.SegmentReference = vp9SegData.SegmentFlags.fields.SegmentReference;
3977 cmd.DW2.SegmentReferenceEnabled = vp9SegData.SegmentFlags.fields.SegmentReferenceEnabled;
3978
3979 cmd.DW3.Filterlevelref0Mode0 = vp9SegData.FilterLevel[0][0];
3980 cmd.DW3.Filterlevelref0Mode1 = vp9SegData.FilterLevel[0][1];
3981 cmd.DW3.Filterlevelref1Mode0 = vp9SegData.FilterLevel[1][0];
3982 cmd.DW3.Filterlevelref1Mode1 = vp9SegData.FilterLevel[1][1];
3983
3984 cmd.DW4.Filterlevelref2Mode0 = vp9SegData.FilterLevel[2][0];
3985 cmd.DW4.Filterlevelref2Mode1 = vp9SegData.FilterLevel[2][1];
3986 cmd.DW4.Filterlevelref3Mode0 = vp9SegData.FilterLevel[3][0];
3987 cmd.DW4.Filterlevelref3Mode1 = vp9SegData.FilterLevel[3][1];
3988
3989 cmd.DW5.LumaDcQuantScaleDecodeModeOnly = vp9SegData.LumaDCQuantScale;
3990 cmd.DW5.LumaAcQuantScaleDecodeModeOnly = vp9SegData.LumaACQuantScale;
3991
3992 cmd.DW6.ChromaDcQuantScaleDecodeModeOnly = vp9SegData.ChromaDCQuantScale;
3993 cmd.DW6.ChromaAcQuantScaleDecodeModeOnly = vp9SegData.ChromaACQuantScale;
3994 }
3995
3996 MHW_MI_CHK_STATUS(Mhw_AddCommandCmdOrBB(m_osInterface, cmdBuffer, batchBuffer, &cmd, cmd.byteSize));
3997
3998 return eStatus;
3999 }
4000
AddHcpHevcVp9RdoqStateCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VDBOX_HEVC_PIC_STATE params)4001 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpHevcVp9RdoqStateCmd(
4002 PMOS_COMMAND_BUFFER cmdBuffer,
4003 PMHW_VDBOX_HEVC_PIC_STATE params)
4004 {
4005 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4006
4007 MHW_MI_CHK_NULL(m_osInterface);
4008 MHW_MI_CHK_NULL(params);
4009 MHW_MI_CHK_NULL(params->pHevcEncSeqParams);
4010
4011 mhw_vdbox_hcp_g12_X::HEVC_VP9_RDOQ_STATE_CMD cmd;
4012 uint16_t lambdaTab[2][2][76];
4013
4014 MHW_MI_CHK_NULL(params->pHevcEncPicParams);
4015
4016 if (params->pHevcEncSeqParams->bit_depth_luma_minus8 < 8)
4017 {
4018 uint32_t sliceTypeIdx = (params->pHevcEncPicParams->CodingType == I_TYPE) ? 0 : 1;
4019
4020 //Intra lambda
4021 MOS_ZeroMemory(lambdaTab, sizeof(lambdaTab));
4022 if (params->pHevcEncSeqParams->bit_depth_luma_minus8 == 0)
4023 {
4024 MHW_MI_CHK_STATUS(MOS_SecureMemcpy(
4025 lambdaTab[0][0],
4026 sizeof(RDOQLamdas8bits[sliceTypeIdx][0][0]),
4027 RDOQLamdas8bits[sliceTypeIdx][0][0],
4028 sizeof(RDOQLamdas8bits[sliceTypeIdx][0][0])));
4029 MHW_MI_CHK_STATUS(MOS_SecureMemcpy(
4030 lambdaTab[0][1],
4031 sizeof(RDOQLamdas8bits[sliceTypeIdx][0][1]),
4032 RDOQLamdas8bits[sliceTypeIdx][0][1],
4033 sizeof(RDOQLamdas8bits[sliceTypeIdx][0][1])));
4034 MHW_MI_CHK_STATUS(MOS_SecureMemcpy(
4035 lambdaTab[1][0],
4036 sizeof(RDOQLamdas8bits[sliceTypeIdx][1][0]),
4037 RDOQLamdas8bits[sliceTypeIdx][1][0],
4038 sizeof(RDOQLamdas8bits[sliceTypeIdx][1][0])));
4039 MHW_MI_CHK_STATUS(MOS_SecureMemcpy(
4040 lambdaTab[1][1],
4041 sizeof(RDOQLamdas8bits[sliceTypeIdx][1][1]),
4042 RDOQLamdas8bits[sliceTypeIdx][1][1],
4043 sizeof(RDOQLamdas8bits[sliceTypeIdx][1][1])));
4044 }
4045 else if (params->pHevcEncSeqParams->bit_depth_luma_minus8 == 2)
4046 {
4047 MHW_MI_CHK_STATUS(MOS_SecureMemcpy(
4048 lambdaTab[0][0],
4049 sizeof(RDOQLamdas10bits[sliceTypeIdx][0][0]),
4050 RDOQLamdas10bits[sliceTypeIdx][0][0],
4051 sizeof(RDOQLamdas10bits[sliceTypeIdx][0][0])));
4052 MHW_MI_CHK_STATUS(MOS_SecureMemcpy(
4053 lambdaTab[0][1],
4054 sizeof(RDOQLamdas10bits[sliceTypeIdx][0][1]),
4055 RDOQLamdas10bits[sliceTypeIdx][0][1],
4056 sizeof(RDOQLamdas10bits[sliceTypeIdx][0][1])));
4057 MHW_MI_CHK_STATUS(MOS_SecureMemcpy(
4058 lambdaTab[1][0],
4059 sizeof(RDOQLamdas10bits[sliceTypeIdx][1][0]),
4060 RDOQLamdas10bits[sliceTypeIdx][1][0],
4061 sizeof(RDOQLamdas10bits[sliceTypeIdx][1][0])));
4062 MHW_MI_CHK_STATUS(MOS_SecureMemcpy(
4063 lambdaTab[1][1],
4064 sizeof(RDOQLamdas10bits[sliceTypeIdx][1][1]),
4065 RDOQLamdas10bits[sliceTypeIdx][1][1],
4066 sizeof(RDOQLamdas10bits[sliceTypeIdx][1][1])));
4067 }
4068 else if (params->pHevcEncSeqParams->bit_depth_luma_minus8 == 4)
4069 {
4070 MHW_MI_CHK_STATUS(MOS_SecureMemcpy(
4071 lambdaTab[0][0],
4072 sizeof(RDOQLamdas12bits[sliceTypeIdx][0][0]),
4073 RDOQLamdas12bits[sliceTypeIdx][0][0],
4074 sizeof(RDOQLamdas12bits[sliceTypeIdx][0][0])));
4075 MHW_MI_CHK_STATUS(MOS_SecureMemcpy(
4076 lambdaTab[0][1],
4077 sizeof(RDOQLamdas12bits[sliceTypeIdx][0][1]),
4078 RDOQLamdas12bits[sliceTypeIdx][0][1],
4079 sizeof(RDOQLamdas12bits[sliceTypeIdx][0][1])));
4080 MHW_MI_CHK_STATUS(MOS_SecureMemcpy(
4081 lambdaTab[1][0],
4082 sizeof(RDOQLamdas12bits[sliceTypeIdx][1][0]),
4083 RDOQLamdas12bits[sliceTypeIdx][1][0],
4084 sizeof(RDOQLamdas12bits[sliceTypeIdx][1][0])));
4085 MHW_MI_CHK_STATUS(MOS_SecureMemcpy(
4086 lambdaTab[1][1],
4087 sizeof(RDOQLamdas12bits[sliceTypeIdx][1][1]),
4088 RDOQLamdas12bits[sliceTypeIdx][1][1],
4089 sizeof(RDOQLamdas12bits[sliceTypeIdx][1][1])));
4090 }
4091 }
4092 else
4093 {
4094 int32_t shiftQP = 12;
4095 #if INTRACONF
4096 double lambdaScale = 1.8; //Intra
4097 #else
4098 double lambdaScale = 1.0 - 0.35; //LD or RA
4099 #endif
4100 double qpTemp = 0;
4101 double lambdaDouble = 0;
4102 uint32_t lambda = 0;
4103 double qpFactor = 0.55;
4104
4105 MOS_ZeroMemory(lambdaTab, sizeof(lambdaTab));
4106
4107 int32_t bitdepthLumaQpScaleLuma = 6 * params->pHevcEncSeqParams->bit_depth_luma_minus8;
4108 int32_t bitdepthLumaQpScaleChroma = 6 * params->pHevcEncSeqParams->bit_depth_chroma_minus8;
4109
4110 //Intra lambda
4111 qpFactor = 0.25*lambdaScale;
4112 for (uint8_t qp = 0; qp < 52 + bitdepthLumaQpScaleLuma; qp++)
4113 {
4114 qpTemp = (double)qp - bitdepthLumaQpScaleLuma - shiftQP;
4115 lambdaDouble = qpFactor * pow(2.0, qpTemp / 3.0);
4116 lambdaDouble = lambdaDouble * 16 + 0.5;
4117 lambdaDouble = (lambdaDouble > 65535) ? 65535 : lambdaDouble;
4118 lambda = (uint32_t)floor(lambdaDouble);
4119 lambdaTab[0][0][qp] = (uint16_t)lambda;
4120 }
4121 for (uint8_t qp = 0; qp < 52 + bitdepthLumaQpScaleChroma; qp++)
4122 {
4123 qpTemp = (double)qp - bitdepthLumaQpScaleChroma - shiftQP;
4124 lambdaDouble = qpFactor * pow(2.0, qpTemp / 3.0);
4125 lambdaDouble = lambdaDouble * 16 + 0.5;
4126 lambdaDouble = (lambdaDouble > 65535) ? 65535 : lambdaDouble;
4127 lambda = (uint32_t)floor(lambdaDouble);
4128 lambdaTab[0][1][qp] = (uint16_t)lambda;
4129 }
4130
4131 ////Inter lambda
4132 qpFactor = 0.55;
4133 for (uint8_t qp = 0; qp < 52 + bitdepthLumaQpScaleLuma; qp++)
4134 {
4135 qpTemp = (double)qp - bitdepthLumaQpScaleLuma - shiftQP;
4136 lambdaDouble = qpFactor * pow(2.0, qpTemp / 3.0);
4137 lambdaDouble *= MOS_MAX(1.00, MOS_MIN(1.6, 1.0 + 0.6 / 12.0*(qpTemp - 10.0)));
4138 lambdaDouble = lambdaDouble * 16 + 0.5;
4139 lambda = (uint32_t)floor(lambdaDouble);
4140 lambdaDouble = (lambdaDouble > 65535) ? 65535 : lambdaDouble;
4141 lambda = CodecHal_Clip3(0, 0xffff, lambda);
4142 lambdaTab[1][0][qp] = (uint16_t)lambda;
4143 }
4144 for (uint8_t qp = 0; qp < 52 + bitdepthLumaQpScaleChroma; qp++)
4145 {
4146 qpTemp = (double)qp - bitdepthLumaQpScaleChroma - shiftQP;
4147 lambdaDouble = qpFactor * pow(2.0, qpTemp / 3.0);
4148 lambdaDouble *= MOS_MAX(0.95, MOS_MIN(1.20, 0.25 / 12.0*(qpTemp - 10.0) + 0.95));
4149 lambdaDouble = lambdaDouble * 16 + 0.5;
4150 lambda = (uint32_t)floor(lambdaDouble);
4151 lambdaDouble = (lambdaDouble > 65535) ? 65535 : lambdaDouble;
4152 lambda = CodecHal_Clip3(0, 0xffff, lambda);
4153 lambdaTab[1][1][qp] = (uint16_t)lambda;
4154 }
4155 }
4156
4157 for (uint8_t i = 0; i < 32; i++)
4158 {
4159 cmd.Intralumalambda[i].DW0.Lambdavalue0 = lambdaTab[0][0][i * 2];
4160 cmd.Intralumalambda[i].DW0.Lambdavalue1 = lambdaTab[0][0][i * 2 + 1];
4161
4162 cmd.Intrachromalambda[i].DW0.Lambdavalue0 = lambdaTab[0][1][i * 2];
4163 cmd.Intrachromalambda[i].DW0.Lambdavalue1 = lambdaTab[0][1][i * 2 + 1];
4164
4165 cmd.Interlumalambda[i].DW0.Lambdavalue0 = lambdaTab[1][0][i * 2];
4166 cmd.Interlumalambda[i].DW0.Lambdavalue1 = lambdaTab[1][0][i * 2 + 1];
4167
4168 cmd.Interchromalambda[i].DW0.Lambdavalue0 = lambdaTab[1][1][i * 2];
4169 cmd.Interchromalambda[i].DW0.Lambdavalue1 = lambdaTab[1][1][i * 2 + 1];
4170 }
4171
4172 for (uint8_t i = 0; i < 6; i++)
4173 {
4174 cmd.Intralumalambda12bit[i].DW0.Lambdavalue0 = lambdaTab[0][0][i * 2 + 64];
4175 cmd.Intralumalambda12bit[i].DW0.Lambdavalue1 = lambdaTab[0][0][i * 2 + 1 + 64];
4176
4177 cmd.Intrachromalambda12bit[i].DW0.Lambdavalue0 = lambdaTab[0][1][i * 2 + 64];
4178 cmd.Intrachromalambda12bit[i].DW0.Lambdavalue1 = lambdaTab[0][1][i * 2 + 1 + 64];
4179
4180 cmd.Interlumalambda12bit[i].DW0.Lambdavalue0 = lambdaTab[1][0][i * 2 + 64];
4181 cmd.Interlumalambda12bit[i].DW0.Lambdavalue1 = lambdaTab[1][0][i * 2 + 1 + 64];
4182
4183 cmd.Interchromalambda12bit[i].DW0.Lambdavalue0 = lambdaTab[1][1][i * 2 + 64];
4184 cmd.Interchromalambda12bit[i].DW0.Lambdavalue1 = lambdaTab[1][1][i * 2 + 1 + 64];
4185 }
4186
4187 if (m_hevcRDOQPerfDisabled)
4188 {
4189 cmd.DW1.DisableHtqPerformanceFix0 = true;
4190 cmd.DW1.DisableHtqPerformanceFix1 = true;
4191 }
4192
4193 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, sizeof(cmd)));
4194
4195 return eStatus;
4196 }
4197
AddHcpDecodeTileCodingCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 params)4198 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpDecodeTileCodingCmd(
4199 PMOS_COMMAND_BUFFER cmdBuffer,
4200 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 params)
4201 {
4202 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4203
4204 MHW_FUNCTION_ENTER;
4205
4206 MHW_MI_CHK_NULL(m_osInterface);
4207 MHW_MI_CHK_NULL(params);
4208
4209 mhw_vdbox_hcp_g12_X::HCP_TILE_CODING_CMD cmd;
4210 MEDIA_SYSTEM_INFO *gtSystemInfo = m_osInterface->pfnGetGtSystemInfo(m_osInterface);
4211 uint8_t numVdbox = (uint8_t)gtSystemInfo->VDBoxInfo.NumberOfVDBoxEnabled;
4212
4213 MHW_ASSERT(params->ucNumDecodePipes <= numVdbox);
4214 MHW_ASSERT(params->ucPipeIdx < params->ucNumDecodePipes);
4215
4216 cmd.DW1.NumberOfActiveBePipes = params->ucNumDecodePipes;
4217 cmd.DW1.NumOfTileColumnsInAFrame = params->ucNumDecodePipes;
4218 cmd.DW2.TileRowPosition = params->TileStartLCUY;
4219 cmd.DW2.TileColumnPosition = params->TileStartLCUX;
4220 cmd.DW2.Islasttileofcolumn = params->IsLastTileofColumn;
4221 cmd.DW2.Islasttileofrow = params->IsLastTileofRow;
4222 cmd.DW3.Tileheightinmincbminus1 = params->TileHeightInMinCbMinus1;
4223 cmd.DW3.Tilewidthinmincbminus1 = params->TileWidthInMinCbMinus1;
4224
4225 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, sizeof(cmd)));
4226
4227 return eStatus;
4228 }
4229
AddHcpEncodeTileCodingCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 params)4230 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpEncodeTileCodingCmd(
4231 PMOS_COMMAND_BUFFER cmdBuffer,
4232 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 params)
4233 {
4234 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4235
4236 MHW_FUNCTION_ENTER;
4237
4238 mhw_vdbox_hcp_g12_X::HCP_TILE_CODING_CMD cmd;
4239
4240 MHW_CHK_NULL(m_osInterface);
4241 MHW_CHK_NULL(params);
4242
4243 cmd.DW1.NumberOfActiveBePipes = params->NumberOfActiveBePipes;
4244 cmd.DW1.NumOfTileColumnsInAFrame = params->NumOfTileColumnsInFrame; // This field is not used by HW. This field should be same as "Number of Active BE Pipes".
4245 cmd.DW1.TileRowStoreSelect = params->TileRowStoreSelect;
4246 cmd.DW1.TileColumnStoreSelect = params->TileColumnStoreSelect;
4247
4248 cmd.DW2.TileColumnPosition = params->TileStartLCUX;
4249 cmd.DW2.TileRowPosition = params->TileStartLCUY;
4250 cmd.DW2.Islasttileofcolumn = params->IsLastTileofColumn;
4251 cmd.DW2.Islasttileofrow = params->IsLastTileofRow;
4252 cmd.DW3.Tileheightinmincbminus1 = params->TileHeightInMinCbMinus1;
4253 cmd.DW3.Tilewidthinmincbminus1 = params->TileWidthInMinCbMinus1;
4254
4255 cmd.DW8.CuRecordOffset = params->CuRecordOffset;
4256 cmd.DW4.BitstreamByteOffset = params->BitstreamByteOffset;
4257 cmd.DW5.PakFrameStatisticsOffset = params->PakTileStatisticsOffset;
4258 cmd.DW6.CuLevelStreamoutOffset = params->CuLevelStreamoutOffset;
4259 cmd.DW7.SliceSizeStreamoutOffset = params->SliceSizeStreamoutOffset;
4260 cmd.DW9.SseRowstoreOffset = params->SseRowstoreOffset;
4261 cmd.DW10.SaoRowstoreOffset = params->SaoRowstoreOffset;
4262 cmd.DW11.TileSizeStreamoutOffset = params->TileSizeStreamoutOffset;
4263 cmd.DW12.Vp9ProbabilityCounterStreamoutOffset = params->Vp9ProbabilityCounterStreamoutOffset;
4264
4265 // for Tile Replay
4266 cmd.DW2.NonFirstPassTile = params->bTileReplayEnable && (!params->IsFirstPass);
4267 // By default enable bit stream offset when tile replay is enabled with multiple pipes;
4268 // for single pipe case, by default set to 1, simulation currently can not support 0 for single pipe;
4269 // To be followed and clarified
4270 cmd.DW4.BitstreamByteOffsetEnable = params->bTileReplayEnable;
4271 if (params->presHcpSyncBuffer) // this buffer is not used in HEVC/VP9 decode or encode
4272 {
4273 PMOS_INTERFACE osInterface;
4274 MHW_RESOURCE_PARAMS resourceParams;
4275
4276 osInterface = m_osInterface;
4277
4278 cmd.HcpScalabilitySynchronizeBufferAttributes.DW0.Value |=
4279 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_HCP_SAO_CODEC].Value;
4280
4281 MOS_ZeroMemory(&resourceParams, sizeof(resourceParams));
4282 resourceParams.dwLsbNum = MHW_VDBOX_HCP_GENERAL_STATE_SHIFT;
4283 resourceParams.HwCommandType = MOS_MFX_PIPE_BUF_ADDR;
4284 resourceParams.presResource = params->presHcpSyncBuffer;
4285 resourceParams.dwOffset = 0;
4286 resourceParams.pdwCmd = (cmd.HcpScalabilitySynchronizeBufferBaseAddress.DW0_1.Value);
4287 resourceParams.dwLocationInCmd = 13;
4288 resourceParams.bIsWritable = true;
4289
4290 MHW_CHK_STATUS(pfnAddResourceToCmd(
4291 osInterface,
4292 cmdBuffer,
4293 &resourceParams));
4294 }
4295
4296 MHW_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, sizeof(cmd)));
4297
4298 finish:
4299 return eStatus;
4300 }
4301
AddHcpHevcPicBrcBuffer(PMOS_RESOURCE hcpImgStates,PMHW_VDBOX_HEVC_PIC_STATE hevcPicState)4302 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpHevcPicBrcBuffer(
4303 PMOS_RESOURCE hcpImgStates,
4304 PMHW_VDBOX_HEVC_PIC_STATE hevcPicState)
4305 {
4306 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4307
4308 MHW_FUNCTION_ENTER;
4309
4310 MHW_MI_CHK_NULL(hcpImgStates);
4311
4312 MOS_COMMAND_BUFFER constructedCmdBuf;
4313 mhw_vdbox_hcp_g12_X::HCP_PIC_STATE_CMD cmd;
4314 uint32_t* insertion = nullptr;
4315 MOS_LOCK_PARAMS lockFlags;
4316 m_brcNumPakPasses = hevcPicState->brcNumPakPasses;
4317
4318 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
4319 lockFlags.WriteOnly = 1;
4320 uint8_t *data = (uint8_t*)m_osInterface->pfnLockResource(m_osInterface, hcpImgStates, &lockFlags);
4321 MHW_MI_CHK_NULL(data);
4322
4323 constructedCmdBuf.pCmdBase = (uint32_t *)data;
4324 constructedCmdBuf.pCmdPtr = (uint32_t *)data;
4325 constructedCmdBuf.iOffset = 0;
4326 constructedCmdBuf.iRemaining = BRC_IMG_STATE_SIZE_PER_PASS_G11 * (m_brcNumPakPasses);
4327
4328 MHW_MI_CHK_STATUS(AddHcpPicStateCmd(&constructedCmdBuf, hevcPicState));
4329
4330 cmd = *(mhw_vdbox_hcp_g12_X::HCP_PIC_STATE_CMD *)data;
4331
4332 for (uint32_t i = 0; i < m_brcNumPakPasses; i++)
4333 {
4334 if (i == 0)
4335 {
4336 cmd.DW6.Nonfirstpassflag = false;
4337 }
4338 else
4339 {
4340 cmd.DW6.Nonfirstpassflag = true;
4341 }
4342
4343 cmd.DW6.FrameszoverstatusenFramebitratemaxreportmask = true;
4344 cmd.DW6.FrameszunderstatusenFramebitrateminreportmask = true;
4345 cmd.DW6.LcumaxbitstatusenLcumaxsizereportmask = false; // BRC update kernel does not consider if there is any LCU whose size is too big
4346
4347 *(mhw_vdbox_hcp_g12_X::HCP_PIC_STATE_CMD *)data = cmd;
4348
4349 /* add batch buffer end insertion flag */
4350 insertion = (uint32_t*)(data + mhw_vdbox_hcp_g12_X::HCP_PIC_STATE_CMD::byteSize);
4351 *insertion = 0x05000000;
4352
4353 data += BRC_IMG_STATE_SIZE_PER_PASS_G11;
4354 }
4355
4356 MHW_MI_CHK_STATUS(m_osInterface->pfnUnlockResource(m_osInterface, hcpImgStates));
4357
4358 return eStatus;
4359 }
4360
AddHcpPaletteInitializerStateCmd(PMOS_COMMAND_BUFFER cmdBuffer,PCODEC_HEVC_SCC_PIC_PARAMS params)4361 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpPaletteInitializerStateCmd(
4362 PMOS_COMMAND_BUFFER cmdBuffer,
4363 PCODEC_HEVC_SCC_PIC_PARAMS params)
4364 {
4365 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4366
4367 MHW_MI_CHK_NULL(m_osInterface);
4368 MHW_MI_CHK_NULL(params);
4369
4370 mhw_vdbox_hcp_g12_X::HCP_PALETTE_INITIALIZER_STATE_CMD cmd;
4371 uint32_t yentryIdx = 0;
4372 uint32_t yentry = 0, cbEntry = 0, crEntry = 0;
4373
4374 cmd.DW1.ActivePaletteInitializerTableEntries = params->PredictorPaletteSize;
4375
4376 for (uint32_t i = 0; i < m_HevcSccPaletteSize; i += 3)
4377 {
4378 // First 64 color entries
4379 yentryIdx = i * 2 / 3;
4380 cmd.First64ColorEntries[i] = params->PredictorPaletteEntries[0][yentryIdx]; // Y
4381 cbEntry = (uint32_t)params->PredictorPaletteEntries[1][yentryIdx];
4382 cmd.First64ColorEntries[i] |= (cbEntry << 16); // Cb
4383
4384 cmd.First64ColorEntries[i + 1] = params->PredictorPaletteEntries[2][yentryIdx]; // Cr
4385 yentry = (uint32_t)params->PredictorPaletteEntries[0][yentryIdx + 1];
4386 cmd.First64ColorEntries[i + 1] |= (yentry << 16); // Y
4387
4388 cmd.First64ColorEntries[i + 2] = params->PredictorPaletteEntries[1][yentryIdx + 1]; // Cb
4389 crEntry = (uint32_t)params->PredictorPaletteEntries[2][yentryIdx + 1];
4390 cmd.First64ColorEntries[i + 2] |= (crEntry << 16); // Cr
4391
4392 // Second 64 color entries
4393 yentryIdx += 64;
4394 cmd.Second64ColorEntries[i] = params->PredictorPaletteEntries[0][yentryIdx]; // Y
4395 cbEntry = (uint32_t)params->PredictorPaletteEntries[1][yentryIdx];
4396 cmd.Second64ColorEntries[i] |= (cbEntry << 16); // Cb
4397
4398 cmd.Second64ColorEntries[i + 1] = params->PredictorPaletteEntries[2][yentryIdx]; // Cr
4399 yentry = (uint32_t)params->PredictorPaletteEntries[0][yentryIdx + 1];
4400 cmd.Second64ColorEntries[i + 1] |= (yentry << 16); // Y
4401
4402 cmd.Second64ColorEntries[i + 2] = params->PredictorPaletteEntries[1][yentryIdx + 1]; // Cb
4403 crEntry = (uint32_t)params->PredictorPaletteEntries[2][yentryIdx + 1];
4404 cmd.Second64ColorEntries[i + 2] |= (crEntry << 16); // Cr
4405 }
4406
4407 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, sizeof(cmd)));
4408
4409 return eStatus;
4410 }
4411
GetOsResLaceOrAceOrRgbHistogramBufferSize(uint32_t width,uint32_t height,uint32_t * size)4412 MOS_STATUS MhwVdboxHcpInterfaceG12::GetOsResLaceOrAceOrRgbHistogramBufferSize(
4413 uint32_t width,
4414 uint32_t height,
4415 uint32_t *size)
4416 {
4417 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4418
4419 *size = m_veboxRgbHistogramSize;
4420 *size += m_veboxRgbAceHistogramSizeReserved;
4421
4422 uint32_t dwSizeLace = MOS_ROUNDUP_DIVIDE(height, 64) *
4423 MOS_ROUNDUP_DIVIDE(width, 64) *
4424 m_veboxLaceHistogram256BinPerBlock;
4425
4426 uint32_t dwSizeNoLace = m_veboxAceHistogramSizePerFramePerSlice *
4427 m_veboxNumFramePreviousCurrent *
4428 m_veboxMaxSlices;
4429
4430 *size += MOS_MAX(dwSizeLace, dwSizeNoLace);
4431
4432 return eStatus;
4433 }
4434
GetOsResStatisticsOutputBufferSize(uint32_t width,uint32_t height,uint32_t * size)4435 MOS_STATUS MhwVdboxHcpInterfaceG12::GetOsResStatisticsOutputBufferSize(
4436 uint32_t width,
4437 uint32_t height,
4438 uint32_t *size)
4439 {
4440 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4441
4442 width = MOS_ALIGN_CEIL(width, 64);
4443 height = MOS_ROUNDUP_DIVIDE(height, 4) + MOS_ROUNDUP_DIVIDE(m_veboxStatisticsSize * sizeof(uint32_t), width);
4444 *size = width * height;
4445
4446 return eStatus;
4447 }
4448
AddHcpTileCodingCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 params)4449 MOS_STATUS MhwVdboxHcpInterfaceG12::AddHcpTileCodingCmd(
4450 PMOS_COMMAND_BUFFER cmdBuffer,
4451 PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 params)
4452 {
4453 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4454
4455 MHW_FUNCTION_ENTER;
4456
4457 if (m_decodeInUse)
4458 {
4459 MHW_MI_CHK_STATUS(AddHcpDecodeTileCodingCmd(cmdBuffer, params));
4460 }
4461 else
4462 {
4463 MHW_MI_CHK_STATUS(AddHcpEncodeTileCodingCmd(cmdBuffer, params));
4464 }
4465
4466 return eStatus;
4467 }