1 /* 2 * Copyright (c) 2017-2021, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 //! \file mhw_vdbox_huc_generic.h 24 //! \brief MHW interface for constructing HUC commands for the Vdbox engine 25 //! \details Impelements shared Vdbox HUC command construction functions across all platforms as templates 26 //! 27 28 #ifndef _MHW_VDBOX_HUC_GENERIC_H_ 29 #define _MHW_VDBOX_HUC_GENERIC_H_ 30 31 #include "mhw_vdbox_huc_interface.h" 32 #include "mhw_cp_interface.h" 33 34 //! MHW Vdbox Huc generic interface 35 /*! 36 This class defines the shared Huc command construction functions across all platforms as templates 37 */ 38 template <class THucCmds, class TMiCmds> 39 class MhwVdboxHucInterfaceGeneric : public MhwVdboxHucInterface 40 { 41 protected: 42 //! 43 //! \enum CommandsNumberOfAddresses 44 //! \brief Commands number of addresses 45 //! 46 enum CommandsNumberOfAddresses 47 { 48 MI_STORE_DATA_IMM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 49 MI_FLUSH_DW_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 50 MI_CONDITIONAL_BATCH_BUFFER_END_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 51 MI_STORE_REGISTER_MEM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 52 MI_COPY_MEM_MEM_CMD_NUMBER_OF_ADDRESSES = 2, // 4 DW for 2 address fields 53 54 VD_PIPELINE_FLUSH_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for 0 address fields 55 56 HUC_PIPE_MODE_SELECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 57 HUC_IMEM_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 58 HUC_DMEM_STATE_CMD_NUMBER_OF_ADDRESSES = 2, // 3 DW for 2 address fields 59 HUC_VIRTUAL_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 16, // 32 DW for 16 address fields 60 HUC_IND_OBJ_BASE_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 4, // 8 DW for 4 address fields 61 HUC_STREAM_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 62 HUC_START_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 63 }; 64 65 //! 66 //! \brief Constructor 67 //! MhwVdboxHucInterfaceGeneric(PMOS_INTERFACE osInterface,MhwMiInterface * miInterface,MhwCpInterface * cpInterface)68 MhwVdboxHucInterfaceGeneric( 69 PMOS_INTERFACE osInterface, 70 MhwMiInterface *miInterface, 71 MhwCpInterface *cpInterface) : 72 MhwVdboxHucInterface(osInterface, miInterface, cpInterface) 73 { 74 MHW_FUNCTION_ENTER; 75 } 76 77 //! 78 //! \brief Destructor 79 //! ~MhwVdboxHucInterfaceGeneric()80 virtual ~MhwVdboxHucInterfaceGeneric() {} 81 82 protected: GetHucStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)83 MOS_STATUS GetHucStateCommandSize( 84 uint32_t mode, 85 uint32_t *commandsSize, 86 uint32_t *patchListSize, 87 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params) 88 { 89 MHW_FUNCTION_ENTER; 90 91 uint32_t maxSize = 0; 92 uint32_t patchListMaxSize = 0; 93 uint32_t standard = CodecHal_GetStandardFromMode(mode); 94 uint32_t numSlices = 1; 95 uint32_t numStoreDataImm = 1; 96 uint32_t numStoreReg = 3; 97 98 MHW_MI_CHK_NULL(commandsSize); 99 MHW_MI_CHK_NULL(patchListSize); 100 MHW_MI_CHK_NULL(params); 101 102 if(params->uNumStoreDataImm) 103 { 104 numStoreDataImm = params->uNumStoreDataImm; 105 } 106 if(params->uNumStoreReg) 107 { 108 numStoreReg = params->uNumStoreReg; 109 } 110 111 if (mode == CODECHAL_DECODE_MODE_HEVCVLD && params->bShortFormat) 112 { 113 numSlices = CODECHAL_HEVC_MAX_NUM_SLICES_LVL_6; 114 numStoreDataImm = 2; 115 numStoreReg = 2; 116 117 maxSize += 118 2 * TMiCmds::MI_CONDITIONAL_BATCH_BUFFER_END_CMD::byteSize; 119 120 patchListMaxSize += 121 2 * PATCH_LIST_COMMAND(MI_CONDITIONAL_BATCH_BUFFER_END_CMD); 122 } 123 else if (standard == CODECHAL_CENC) 124 { 125 numStoreDataImm = 3; 126 numStoreReg = 3; 127 128 maxSize += 129 TMiCmds::MI_FLUSH_DW_CMD::byteSize * 2 + 130 TMiCmds::MI_BATCH_BUFFER_END_CMD::byteSize; 131 132 patchListMaxSize += 133 PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD) * 2; 134 135 } 136 else if (mode == CODECHAL_ENCODE_MODE_VP9) 137 { 138 // for huc status 2 register and semaphore signal and reset 139 numStoreDataImm = 3; 140 141 maxSize += 142 TMiCmds::MI_BATCH_BUFFER_END_CMD::byteSize + 143 TMiCmds::MI_FLUSH_DW_CMD::byteSize; 144 145 patchListMaxSize += 146 PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD); 147 } 148 else if (mode == CODECHAL_ENCODE_MODE_AVC) 149 { 150 numStoreDataImm = 2; 151 numStoreReg = 4; 152 153 maxSize += 154 2 * TMiCmds::MI_CONDITIONAL_BATCH_BUFFER_END_CMD::byteSize; 155 156 patchListMaxSize += 157 2 * PATCH_LIST_COMMAND(MI_CONDITIONAL_BATCH_BUFFER_END_CMD); 158 } 159 160 maxSize += 161 THucCmds::HUC_PIPE_MODE_SELECT_CMD::byteSize + 162 THucCmds::HUC_IMEM_STATE_CMD::byteSize + 163 THucCmds::HUC_DMEM_STATE_CMD::byteSize + 164 THucCmds::HUC_VIRTUAL_ADDR_STATE_CMD::byteSize + 165 THucCmds::HUC_IND_OBJ_BASE_ADDR_STATE_CMD::byteSize + 166 numSlices * THucCmds::HUC_STREAM_OBJECT_CMD::byteSize + 167 numSlices * THucCmds::HUC_START_CMD::byteSize + 168 numStoreDataImm * TMiCmds::MI_STORE_DATA_IMM_CMD::byteSize + 169 numStoreReg * TMiCmds::MI_STORE_REGISTER_MEM_CMD::byteSize; 170 171 if(params->uNumMfxWait) 172 { 173 maxSize += 174 params->uNumMfxWait * TMiCmds::MFX_WAIT_CMD::byteSize; 175 } 176 177 patchListMaxSize += 178 PATCH_LIST_COMMAND(HUC_PIPE_MODE_SELECT_CMD) + 179 PATCH_LIST_COMMAND(HUC_IMEM_STATE_CMD) + 180 PATCH_LIST_COMMAND(HUC_DMEM_STATE_CMD) + 181 PATCH_LIST_COMMAND(HUC_VIRTUAL_ADDR_STATE_CMD) + 182 PATCH_LIST_COMMAND(HUC_IND_OBJ_BASE_ADDR_STATE_CMD) + 183 numSlices * PATCH_LIST_COMMAND(HUC_STREAM_OBJECT_CMD) + 184 numSlices * PATCH_LIST_COMMAND(HUC_START_CMD) + 185 numStoreDataImm * PATCH_LIST_COMMAND(MI_STORE_DATA_IMM_CMD) + 186 numStoreReg * PATCH_LIST_COMMAND(MI_STORE_REGISTER_MEM_CMD); 187 188 if(params->uNumAddConBBEnd) 189 { 190 maxSize += 191 params->uNumAddConBBEnd * TMiCmds::MI_CONDITIONAL_BATCH_BUFFER_END_CMD::byteSize; 192 193 patchListMaxSize += 194 params->uNumAddConBBEnd * PATCH_LIST_COMMAND(MI_CONDITIONAL_BATCH_BUFFER_END_CMD); 195 } 196 if(params->uNumMiCopy) 197 { 198 maxSize += 199 params->uNumMiCopy * TMiCmds::MI_COPY_MEM_MEM_CMD::byteSize; 200 201 patchListMaxSize += 202 params->uNumMiCopy * PATCH_LIST_COMMAND(MI_COPY_MEM_MEM_CMD); 203 } 204 if(params->uNumMiFlush) 205 { 206 maxSize += 207 params->uNumMiFlush * TMiCmds::MI_FLUSH_DW_CMD::byteSize; 208 209 patchListMaxSize += 210 params->uNumMiFlush * PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD); 211 } 212 213 if (params->bHucDummyStream || params->bPerformHucStreamOut) 214 { 215 uint32_t dummyTimes = params->bPerformHucStreamOut ? 2: 1; 216 for (uint32_t i = 0; i < dummyTimes; i++) 217 { 218 maxSize += 219 THucCmds::HUC_PIPE_MODE_SELECT_CMD::byteSize + 220 THucCmds::HUC_IMEM_STATE_CMD::byteSize + 221 THucCmds::HUC_DMEM_STATE_CMD::byteSize + 222 THucCmds::HUC_VIRTUAL_ADDR_STATE_CMD::byteSize + 223 THucCmds::HUC_IND_OBJ_BASE_ADDR_STATE_CMD::byteSize + 224 THucCmds::HUC_STREAM_OBJECT_CMD::byteSize + 225 THucCmds::HUC_START_CMD::byteSize + 226 TMiCmds::MI_FLUSH_DW_CMD::byteSize; 227 228 patchListMaxSize += 229 PATCH_LIST_COMMAND(HUC_PIPE_MODE_SELECT_CMD) + 230 PATCH_LIST_COMMAND(HUC_IMEM_STATE_CMD) + 231 PATCH_LIST_COMMAND(HUC_DMEM_STATE_CMD) + 232 PATCH_LIST_COMMAND(HUC_VIRTUAL_ADDR_STATE_CMD) + 233 PATCH_LIST_COMMAND(HUC_IND_OBJ_BASE_ADDR_STATE_CMD) + 234 PATCH_LIST_COMMAND(HUC_STREAM_OBJECT_CMD) + 235 PATCH_LIST_COMMAND(HUC_START_CMD) + 236 PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD); 237 } 238 if (params->bPerformHucStreamOut) 239 { 240 maxSize += 241 THucCmds::HUC_PIPE_MODE_SELECT_CMD::byteSize + 242 THucCmds::HUC_IND_OBJ_BASE_ADDR_STATE_CMD::byteSize + 243 THucCmds::HUC_STREAM_OBJECT_CMD::byteSize + 244 4 * TMiCmds::MI_FLUSH_DW_CMD::byteSize; 245 246 patchListMaxSize += 247 PATCH_LIST_COMMAND(HUC_PIPE_MODE_SELECT_CMD) + 248 PATCH_LIST_COMMAND(HUC_IND_OBJ_BASE_ADDR_STATE_CMD) + 249 PATCH_LIST_COMMAND(HUC_STREAM_OBJECT_CMD) + 250 4 * PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD); 251 } 252 } 253 254 *commandsSize = maxSize; 255 *patchListSize = patchListMaxSize; 256 257 return MOS_STATUS_SUCCESS; 258 } 259 GetHucPrimitiveCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize)260 MOS_STATUS GetHucPrimitiveCommandSize( 261 uint32_t mode, 262 uint32_t *commandsSize, 263 uint32_t *patchListSize) 264 { 265 MOS_STATUS eStatus = MOS_STATUS_SUCCESS; 266 267 MHW_FUNCTION_ENTER; 268 269 uint32_t maxSize = 0; 270 uint32_t patchListMaxSize = 0; 271 272 // Hal will handling the multiplication of cmd size instead of MHW 273 274 *commandsSize = maxSize; 275 *patchListSize = patchListMaxSize; 276 277 return eStatus; 278 } 279 AddHucPipeModeSelectCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_VDBOX_PIPE_MODE_SELECT_PARAMS * params)280 MOS_STATUS AddHucPipeModeSelectCmd( 281 MOS_COMMAND_BUFFER *cmdBuffer, 282 MHW_VDBOX_PIPE_MODE_SELECT_PARAMS *params) 283 { 284 MHW_MI_CHK_NULL(m_osInterface); 285 MHW_MI_CHK_NULL(cmdBuffer); 286 MHW_MI_CHK_NULL(params); 287 288 typename THucCmds::HUC_PIPE_MODE_SELECT_CMD cmd; 289 290 if (!params->disableProtectionSetting) 291 { 292 MHW_MI_CHK_STATUS(m_cpInterface->SetProtectionSettingsForHucPipeModeSelect((uint32_t*)&cmd)); 293 } 294 295 cmd.DW1.IndirectStreamOutEnable = params->bStreamOutEnabled; 296 cmd.DW2.MediaSoftResetCounterPer1000Clocks = params->dwMediaSoftResetCounterValue; 297 298 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize)); 299 300 return MOS_STATUS_SUCCESS; 301 } 302 AddHucImemStateCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_VDBOX_HUC_IMEM_STATE_PARAMS * params)303 MOS_STATUS AddHucImemStateCmd( 304 MOS_COMMAND_BUFFER *cmdBuffer, 305 MHW_VDBOX_HUC_IMEM_STATE_PARAMS *params) 306 { 307 MHW_MI_CHK_NULL(m_osInterface); 308 MHW_MI_CHK_NULL(cmdBuffer); 309 MHW_MI_CHK_NULL(params); 310 311 typename THucCmds::HUC_IMEM_STATE_CMD cmd; 312 313 cmd.DW4.HucFirmwareDescriptor = params->dwKernelDescriptor; 314 315 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize)); 316 317 return MOS_STATUS_SUCCESS; 318 } 319 AddHucDmemStateCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_VDBOX_HUC_DMEM_STATE_PARAMS * params)320 MOS_STATUS AddHucDmemStateCmd( 321 MOS_COMMAND_BUFFER *cmdBuffer, 322 MHW_VDBOX_HUC_DMEM_STATE_PARAMS *params) 323 { 324 MHW_MI_CHK_NULL(m_osInterface); 325 MHW_MI_CHK_NULL(cmdBuffer); 326 MHW_MI_CHK_NULL(params); 327 328 MHW_RESOURCE_PARAMS resourceParams; 329 MOS_ZeroMemory(&resourceParams, sizeof(resourceParams)); 330 resourceParams.dwLsbNum = MHW_VDBOX_HUC_GENERAL_STATE_SHIFT; 331 resourceParams.HwCommandType = MOS_HUC_DMEM; 332 333 typename THucCmds::HUC_DMEM_STATE_CMD cmd; 334 335 if (params->presHucDataSource) 336 { 337 cmd.HucDataSourceAttributes.DW0.Value |= m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_SURFACE_UNCACHED].Value; 338 resourceParams.presResource = params->presHucDataSource; 339 resourceParams.dwOffset = 0; 340 resourceParams.pdwCmd = (cmd.HucDataSourceBaseAddress.DW0_1.Value); 341 resourceParams.dwLocationInCmd = 1; 342 resourceParams.bIsWritable = false; 343 344 MHW_MI_CHK_STATUS(AddResourceToCmd( 345 m_osInterface, 346 cmdBuffer, 347 &resourceParams)); 348 349 // set HuC data destination address 350 cmd.DW4.HucDataDestinationBaseAddress = params->dwDmemOffset >> MHW_VDBOX_HUC_GENERAL_STATE_SHIFT; 351 352 // set data length 353 cmd.DW5.HucDataLength = params->dwDataLength >> MHW_VDBOX_HUC_GENERAL_STATE_SHIFT; 354 } 355 356 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize)); 357 358 return MOS_STATUS_SUCCESS; 359 } 360 AddHucVirtualAddrStateCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS * params)361 MOS_STATUS AddHucVirtualAddrStateCmd( 362 MOS_COMMAND_BUFFER *cmdBuffer, 363 MHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS *params) 364 { 365 MHW_MI_CHK_NULL(m_osInterface); 366 MHW_MI_CHK_NULL(cmdBuffer); 367 MHW_MI_CHK_NULL(params); 368 369 MHW_RESOURCE_PARAMS resourceParams; 370 371 // set up surface 0~15 372 MOS_ZeroMemory(&resourceParams, sizeof(resourceParams)); 373 resourceParams.dwLsbNum = MHW_VDBOX_HUC_UPPER_BOUND_STATE_SHIFT; 374 resourceParams.HwCommandType = MOS_HUC_VIRTUAL_ADDR; 375 376 typename THucCmds::HUC_VIRTUAL_ADDR_STATE_CMD cmd; 377 378 for (int i = 0; i < 16; i++) 379 { 380 if (params->regionParams[i].presRegion) 381 { 382 cmd.HucVirtualAddressRegion[i].HucSurfaceVirtualaddrregion015.DW0.Value |= 383 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_HUC_VIRTUAL_ADDR_REGION_BUFFER_CODEC].Value; 384 resourceParams.presResource = params->regionParams[i].presRegion; 385 resourceParams.dwOffset = params->regionParams[i].dwOffset; 386 resourceParams.bIsWritable = params->regionParams[i].isWritable; 387 resourceParams.pdwCmd = cmd.HucVirtualAddressRegion[i].HucSurfaceBaseAddressVirtualaddrregion015.DW0_1.Value; 388 resourceParams.dwLocationInCmd = 1 + (i * 3); 389 390 MHW_MI_CHK_STATUS(AddResourceToCmd( 391 m_osInterface, 392 cmdBuffer, 393 &resourceParams)); 394 } 395 } 396 397 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize)); 398 399 return MOS_STATUS_SUCCESS; 400 } 401 AddHucIndObjBaseAddrStateCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS * params)402 MOS_STATUS AddHucIndObjBaseAddrStateCmd( 403 MOS_COMMAND_BUFFER *cmdBuffer, 404 MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS *params) 405 { 406 MHW_MI_CHK_NULL(m_osInterface); 407 MHW_MI_CHK_NULL(cmdBuffer); 408 MHW_MI_CHK_NULL(params); 409 410 MHW_RESOURCE_PARAMS resourceParams; 411 412 // base address of the bit-stream buffer 413 MOS_ZeroMemory(&resourceParams, sizeof(resourceParams)); 414 resourceParams.dwLsbNum = MHW_VDBOX_HUC_UPPER_BOUND_STATE_SHIFT; 415 resourceParams.dwUpperBoundLocationOffsetFromCmd = 3; 416 resourceParams.HwCommandType = MOS_HUC_IND_OBJ_BASE_ADDR; 417 418 typename THucCmds::HUC_IND_OBJ_BASE_ADDR_STATE_CMD cmd; 419 420 if (params->presDataBuffer) 421 { 422 cmd.HucIndirectStreamInObjectbaseAttributes.DW0.Value |= m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_SURFACE_UNCACHED].Value; 423 resourceParams.presResource = params->presDataBuffer; 424 resourceParams.dwOffset = params->dwDataOffset; 425 resourceParams.pdwCmd = cmd.HucIndirectStreamInObjectbaseAddress.DW0_1.Value; 426 resourceParams.dwLocationInCmd = 1; 427 resourceParams.bIsWritable = false; 428 resourceParams.dwSize = params->dwDataSize; 429 430 MHW_MI_CHK_STATUS(AddResourceToCmd( 431 m_osInterface, 432 cmdBuffer, 433 &resourceParams)); 434 } 435 436 if (params->presStreamOutObjectBuffer) 437 { 438 // base address of the stream out buffer 439 cmd.HucIndirectStreamOutObjectbaseAttributes.DW0.Value |= m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_SURFACE_UNCACHED].Value; 440 resourceParams.presResource = params->presStreamOutObjectBuffer; 441 resourceParams.dwOffset = params->dwStreamOutObjectOffset; 442 resourceParams.pdwCmd = cmd.HucIndirectStreamOutObjectbaseAddress.DW0_1.Value; 443 resourceParams.dwLocationInCmd = 6; 444 resourceParams.bIsWritable = true; 445 resourceParams.dwSize = params->dwStreamOutObjectSize; 446 447 MHW_MI_CHK_STATUS(AddResourceToCmd( 448 m_osInterface, 449 cmdBuffer, 450 &resourceParams)); 451 } 452 453 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize)); 454 455 return MOS_STATUS_SUCCESS; 456 } 457 AddHucStreamObjectCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_VDBOX_HUC_STREAM_OBJ_PARAMS * params)458 MOS_STATUS AddHucStreamObjectCmd( 459 MOS_COMMAND_BUFFER *cmdBuffer, 460 MHW_VDBOX_HUC_STREAM_OBJ_PARAMS *params) 461 { 462 MHW_MI_CHK_NULL(m_osInterface); 463 MHW_MI_CHK_NULL(cmdBuffer); 464 MHW_MI_CHK_NULL(params); 465 466 typename THucCmds::HUC_STREAM_OBJECT_CMD cmd; 467 468 cmd.DW1.IndirectStreamInDataLength = params->dwIndStreamInLength; 469 cmd.DW2.IndirectStreamInStartAddress = params->dwIndStreamInStartAddrOffset; 470 cmd.DW2.HucProcessing = params->bHucProcessing; 471 cmd.DW3.IndirectStreamOutStartAddress = params->dwIndStreamOutStartAddrOffset; 472 cmd.DW4.HucBitstreamEnable = params->bStreamInEnable; 473 cmd.DW4.StreamOut = params->bStreamOutEnable; 474 cmd.DW4.EmulationPreventionByteRemoval = params->bEmulPreventionByteRemoval; 475 cmd.DW4.StartCodeSearchEngine = params->bStartCodeSearchEngine; 476 cmd.DW4.Drmlengthmode = params->bLengthModeEnabled; 477 cmd.DW4.StartCodeByte2 = params->ucStartCodeByte2; 478 cmd.DW4.StartCodeByte1 = params->ucStartCodeByte1; 479 cmd.DW4.StartCodeByte0 = params->ucStartCodeByte0; 480 481 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize)); 482 483 return MOS_STATUS_SUCCESS; 484 } 485 AddHucStartCmd(MOS_COMMAND_BUFFER * cmdBuffer,bool lastStreamObject)486 MOS_STATUS AddHucStartCmd( 487 MOS_COMMAND_BUFFER *cmdBuffer, 488 bool lastStreamObject) 489 { 490 MHW_MI_CHK_NULL(m_osInterface); 491 MHW_MI_CHK_NULL(cmdBuffer); 492 493 typename THucCmds::HUC_START_CMD cmd; 494 495 // set last stream object or not 496 cmd.DW1.Laststreamobject = (lastStreamObject != 0); 497 498 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize)); 499 500 return MOS_STATUS_SUCCESS; 501 } 502 }; 503 504 #endif 505