| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Transforms/Utils/ |
| H A D | SimplifyLibCalls.cpp | 409 Value *And = B.CreateICmpNE(NBytes, Zero); in memChrToCharCompare() local
1245 Value *And = B.CreateLogicalAnd(NNeZ, CEqS0); in optimizeMemRChr() local
1338 Value *And = B.CreateAnd(CEqSPos, NGtPos); in optimizeMemChr() local
1346 Value *And = B.CreateAnd(NNeZ, CEqS0); in optimizeMemChr() local
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| /aosp_15_r20/external/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCasts.cpp | 902 Value *And = Builder->CreateAnd(A, AndConst, CSrc->getName()+".mask"); in visitZExt() local
947 Value *And; in visitZExt() local
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| H A D | InstCombineShifts.cpp | 405 Value *And = Builder->CreateAnd(NSh, in FoldShiftByConstant() local
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| H A D | InstCombineSimplifyDemanded.cpp | 368 Instruction *And = BinaryOperator::CreateAnd(I->getOperand(0), AndC); in SimplifyDemandedUseBits() local
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| H A D | InstCombineAndOrXor.cpp | 163 Value *And = Builder->CreateAnd(X, AndRHS); in OptAndOp() local
183 Value *And = Builder->CreateAnd(X, Together); in OptAndOp() local
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| /aosp_15_r20/external/cronet/third_party/rust/chromium_crates_io/vendor/fend-core-1.4.6/src/ |
| H A D | ast.rs | 16 And, enumerator
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| /aosp_15_r20/external/perfetto/src/trace_processor/containers/ |
| H A D | bit_vector.cc | 247 void BitVector::And(const BitVector& sec) { in And() function in perfetto::trace_processor::BitVector
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| H A D | bit_vector.h | 451 void And(uint64_t mask) { *word_ &= mask; } in And() function
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| /aosp_15_r20/prebuilts/go/linux-x86/src/internal/runtime/atomic/ |
| D | atomic_wasm.go | 165 func And(ptr *uint32, val uint32) { func
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 1496 SDValue And = N->getOperand(0); in PostprocessISelDAG() local
1549 SDValue And = N->getOperand(0); in PostprocessISelDAG() local
1931 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask); in foldMaskAndShiftToExtract() local
2297 SDValue And = N.getOperand(0); in matchAddressRecursively() local
4440 bool X86DAGToDAGISel::shrinkAndImmediate(SDNode *And) { in shrinkAndImmediate()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineMulDivRem.cpp | 404 Value *And = Builder.CreateAnd(X, Y, "mulbool"); in visitMul() local
414 Value *And = Builder.CreateAnd(X, Y, "mulbool"); in visitMul() local
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| /aosp_15_r20/art/test/953-invoke-polymorphic-compiler/src/ |
| H A D | Main.java | 182 private static boolean And(boolean lhs, boolean rhs) { in And() method in Main
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| /aosp_15_r20/external/tensorflow/tensorflow/compiler/xla/service/llvm_ir/ |
| H A D | ir_builder_mixin.h | 58 llvm::Value* And(Args&&... args) { in And() function
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| /aosp_15_r20/external/swiftshader/third_party/subzero/src/ |
| H A D | IceAssemblerX8664.cpp | 2329 void AssemblerX8664::And(Type Ty, GPRRegister dst, GPRRegister src) { in And() function in Ice::X8664::AssemblerX8664
2333 void AssemblerX8664::And(Type Ty, GPRRegister dst, const AsmAddress &address) { in And() function in Ice::X8664::AssemblerX8664
2337 void AssemblerX8664::And(Type Ty, GPRRegister dst, const Immediate &imm) { in And() function in Ice::X8664::AssemblerX8664
2341 void AssemblerX8664::And(Type Ty, const AsmAddress &address, GPRRegister reg) { in And() function in Ice::X8664::AssemblerX8664
2345 void AssemblerX8664::And(Type Ty, const AsmAddress &address, in And() function in Ice::X8664::AssemblerX8664
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| H A D | IceAssemblerX8632.cpp | 2201 void AssemblerX8632::And(Type Ty, GPRRegister dst, GPRRegister src) { in And() function in Ice::X8632::AssemblerX8632
2205 void AssemblerX8632::And(Type Ty, GPRRegister dst, const AsmAddress &address) { in And() function in Ice::X8632::AssemblerX8632
2209 void AssemblerX8632::And(Type Ty, GPRRegister dst, const Immediate &imm) { in And() function in Ice::X8632::AssemblerX8632
2213 void AssemblerX8632::And(Type Ty, const AsmAddress &address, GPRRegister reg) { in And() function in Ice::X8632::AssemblerX8632
2217 void AssemblerX8632::And(Type Ty, const AsmAddress &address, in And() function in Ice::X8632::AssemblerX8632
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 440 auto And = BuildMI(MBB, I, DL, SAndB32, FlatScrInitHi) in emitEntryFunctionFlatScratchInit() local
1145 auto And = BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_AND_B32), FramePtrReg) in emitPrologue() local
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| /aosp_15_r20/external/pytorch/test/cpp/tensorexpr/ |
| H A D | test_cpp_codegen.cpp | 110 TEST(CppPrinter, And) { in TEST() argument
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| /aosp_15_r20/prebuilts/go/linux-x86/src/math/big/ |
| D | int.go | 1171 func (z *Int) And(x, y *Int) *Int { func
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 4587 SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL); in foldLogicOfSetCCs() local
4640 SDValue And = DAG.getNode(ISD::AND, DL, OpVT, Add, MaskC); in foldLogicOfSetCCs() local
4758 SDValue And = DAG.getNode(ISD::AND, SL, HalfVT, Shift, NewMask); in visitANDLike() local
4996 SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode), in BackwardsPropagateMask() local
5012 SDValue And = DAG.getNode(ISD::AND, SDLoc(Op1), Op1.getValueType(), in BackwardsPropagateMask() local
5021 SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0), in BackwardsPropagateMask() local
5095 static SDValue combineShiftAnd1ToBitTest(SDNode *And, SelectionDAG &DAG) { in combineShiftAnd1ToBitTest()
6955 auto matchAndXor = [&X, &Y, &M](SDValue And, unsigned XorIdx, SDValue Other) { in unfoldMaskedMerge()
7978 SDValue And = DAG.getNode(ISD::AND, DL, InnerShiftVT, NewShift, Mask); in visitSRL() local
8592 SDValue And = DAG.getNode(ISD::AND, DL, N0.getValueType(), N0, N1_0); in visitSELECT() local
[all …]
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| /aosp_15_r20/external/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 937 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask); in foldMaskAndShiftToExtract() local
1212 SDValue And = N.getOperand(0); in matchAddressRecursively() local
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| /aosp_15_r20/art/compiler/optimizing/ |
| H A D | intrinsics_arm_vixl.cc | 752 __ And(temp2, temp2, temp3); in GenerateStringCompareToLoop() local
753 __ And(out, out, temp3); in GenerateStringCompareToLoop() local
2068 __ And(out_reg_hi, out_reg_hi, in_reg_hi); in GenLowestOneBit() local
2092 __ And(out, temp, in); in GenLowestOneBit() local
4016 __ And(LowRegisterFrom(new_value), LowRegisterFrom(loaded_value), LowRegisterFrom(arg)); in GenerateGetAndUpdate() local
4017 __ And(HighRegisterFrom(new_value), HighRegisterFrom(loaded_value), HighRegisterFrom(arg)); in GenerateGetAndUpdate() local
4019 __ And(RegisterFrom(new_value), RegisterFrom(loaded_value), RegisterFrom(arg)); in GenerateGetAndUpdate() local
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| /aosp_15_r20/external/icing/icing/index/iterator/ |
| H A D | doc-hit-info-iterator-and_test.cc | 38 TEST(CreateAndIteratorTest, And) { in TEST() argument
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| /aosp_15_r20/external/aws-sdk-java-v2/services/freetier/src/main/resources/codegen-resources/ |
| H A D | service-2.json | 71 "And":{ object
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Transforms/AggressiveInstCombine/ |
| H A D | AggressiveInstCombine.cpp | 264 Value *And = Builder.CreateAnd(MOps.Root, Mask); in foldAnyOrAllBitsSet() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/M68k/ |
| H A D | M68kInstrInfo.cpp | 334 unsigned Mask, And; in AddZExt() local
|