| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/MC/ |
| D | MCExpr.h | 496 And, ///< Bitwise and. enumerator
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86BaseInfo.h | 117 And, enumerator
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| /aosp_15_r20/external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 2370 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst); in ExpandLegalINT_TO_FP() local
2387 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, in ExpandLegalINT_TO_FP() local
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| H A D | DAGCombiner.cpp | 2998 SDValue And = DAG.getNode(ISD::AND, SL, HalfVT, Shift, NewMask); in visitANDLike() local
5187 SDValue And = DAG.getNode(ISD::AND, SDLoc(N), N0.getValueType(), in visitSELECT() local
6156 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, in visitSIGN_EXTEND() local
6459 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT, in visitZERO_EXTEND() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 360 unsigned And = WebAssembly::AND_I32; in LowerFPToInt() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 2425 SDValue And = DAG.getNode(ISD::AND, dl, SrcVT, Op0, AndConst); in ExpandLegalINT_TO_FP() local
2965 SDValue And = DAG.getNode(ISD::AND, dl, VT, Node->getOperand(0), One); in ExpandNode() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 960 if (LogicOp And = interpretAndImmediate(MI.getOpcode())) { in convertToThreeAddress() local
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| /aosp_15_r20/art/compiler/utils/arm64/ |
| H A D | jni_macro_assembler_arm64.cc | 704 ___ And(reg.X(), reg.X(), ~kIndirectRefKindMask); in DecodeJNITransitionOrLocalJObject() local
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| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 1282 const SDValue &And = N->getOperand(0); in SelectS_BFE() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 961 if (LogicOp And = interpretAndImmediate(MI.getOpcode())) { in convertToThreeAddress() local
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| /aosp_15_r20/art/compiler/optimizing/ |
| H A D | code_generator_riscv64.cc | 1500 __ And(tmp, tmp, tmp2); in DivRemByPowerOfTwo() local
2168 __ And(rd, rs1, rs2); in HandleBinaryOp() local
5241 __ And(tmp, tmp, xor_reg); in VisitSelect() local
5410 __ And(dst, dst, tmp); // Cleared for NaN. in VisitTypeConversion() local
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| H A D | code_generator_vector_arm64_neon.cc | 800 __ And(dst.V16B(), lhs.V16B(), rhs.V16B()); // lanes do not matter in VisitVecAnd() local
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| H A D | intrinsics_arm64.cc | 513 __ And(dst, temp, src); in GenLowestOneBit() local
1860 __ And(new_value, old_value_reg, arg.IsX() ? arg.X() : arg.W()); in GenerateGetAndUpdate() local
2405 __ And(temp1, temp, Operand(1)); // Extract compression flag. in VisitStringEquals() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/ |
| H A D | AtomicExpandPass.cpp | 794 Value *And = Builder.CreateAnd(WideWord, PMV.Inv_Mask, "unmasked"); in insertMaskedValue() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 3192 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add); in SimplifySetCC() local
3207 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add); in SimplifySetCC() local
6234 SDValue And = DAG.getNode(ISD::AND, dl, SrcVT, Src, AndConst); in expandUINT_TO_FP() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 2422 SDValue And = DAG.getNode(ISD::AND, dl, ResTy, {Xor0, Xor1}); in emitHvxAddWithOverflow() local
2457 SDValue And = DAG.getNode(ISD::AND, dl, IntTy, {Inp, AmtP1}); in emitHvxShiftRightRnd() local
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| H A D | HexagonLoopIdiomRecognition.cpp | 1056 Value *And = IRBuilder<>(In).CreateAnd(T->getOperand(0), Mask); in promoteTo() local
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| /aosp_15_r20/external/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 4520 for (auto *And : AndsToMaybeRemove) in optimizeLoadExt() local
5412 Instruction *And = dyn_cast<Instruction>(Cmp->getOperand(0)); in sinkAndCmp() local
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| /aosp_15_r20/external/swiftshader/third_party/subzero/src/ |
| H A D | IceInstMIPS32.h | 196 And, enumerator
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 2164 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); in LowerFCEIL() local
2325 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); in LowerFFLOOR() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 2057 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); in LowerFCEIL() local
2284 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); in LowerFFLOOR() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSelect.cpp | 2666 Value *And = Builder.CreateAnd(CondVal, TrueSI->getCondition()); in visitSelectInst() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAddSub.cpp | 2110 Value *And = Builder.CreateAnd(X, ConstantInt::get(I.getType(), *C2)); in visitSub() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 451 unsigned And = WebAssembly::AND_I32; in LowerFPToInt() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonLoopIdiomRecognition.cpp | 1040 Value *And = IRBuilder<>(In).CreateAnd(T->getOperand(0), Mask); in promoteTo() local
|