1{
2  "License": [
3    "Copyright (C) 2023 The Android Open Source Project",
4    "",
5    "Licensed under the Apache License, Version 2.0 (the “License”);",
6    "you may not use this file except in compliance with the License.",
7    "You may obtain a copy of the License at",
8    "",
9    "     http://www.apache.org/licenses/LICENSE-2.0",
10    "",
11    "Unless required by applicable law or agreed to in writing, software",
12    "distributed under the License is distributed on an “AS IS” BASIS,",
13    "WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.",
14    "See the License for the specific language governing permissions and",
15    "limitations under the License."
16  ],
17  "arch": "x86_64",
18  "insns": [
19    {
20      "encodings": {
21        "Adcq": { "opcode": "13" },
22        "Sbbq": { "opcode": "1B" }
23      },
24      "args": [
25        { "class": "GeneralReg64", "usage": "use_def" },
26        { "class": "Mem64", "usage": "use" },
27        { "class": "FLAGS", "usage": "use_def" }
28      ]
29    },
30    {
31      "encodings": {
32        "Adcq": { "opcode": "11", "type": "reg_to_rm" },
33        "Sbbq": { "opcode": "19", "type": "reg_to_rm" }
34      },
35      "args": [
36        { "class": "GeneralReg64/Mem64", "usage": "use_def" },
37        { "class": "GeneralReg64", "usage": "use" },
38        { "class": "FLAGS", "usage": "use_def" }
39      ]
40    },
41    {
42      "encodings": {
43        "Adcq": { "opcodes": [ "81", "2" ] },
44        "Sbbq": { "opcodes": [ "81", "3" ] }
45      },
46      "args": [
47        { "class": "GeneralReg64/Mem64", "usage": "use_def" },
48        { "class": "Imm32" },
49        { "class": "FLAGS", "usage": "use_def" }
50      ]
51    },
52    {
53      "encodings": {
54        "AdcqAccumulator": { "opcodes": [ "48", "15" ] },
55        "SbbqAccumulator": { "opcodes": [ "48", "1D" ] }
56      },
57      "args": [
58        { "class": "RAX", "usage": "use_def" },
59        { "class": "Imm32" },
60        { "class": "FLAGS", "usage": "use_def" }
61      ]
62    },
63    {
64      "encodings": {
65        "AdcqImm8": { "opcodes": [ "83", "2" ] },
66        "Rclq": { "opcodes": [ "C1", "2" ] },
67        "Rcrq": { "opcodes": [ "C1", "3" ] },
68        "SbbqImm8": { "opcodes": [ "83", "3" ] }
69      },
70      "args": [
71        { "class": "GeneralReg64/Mem64", "usage": "use_def" },
72        { "class": "Imm8" },
73        { "class": "FLAGS", "usage": "use_def" }
74      ]
75    },
76    {
77      "encodings": {
78        "Addq": { "opcode": "01", "type": "reg_to_rm" },
79        "Andq": { "opcode": "21", "type": "reg_to_rm" },
80        "Btcq": { "opcodes": [ "0F", "BB" ], "type": "reg_to_rm" },
81        "Btrq": { "opcodes": [ "0F", "B3" ], "type": "reg_to_rm" },
82        "Btsq": { "opcodes": [ "0F", "AB" ], "type": "reg_to_rm" },
83        "Orq": { "opcode": "09", "type": "reg_to_rm" },
84        "Subq": { "opcode": "29", "type": "reg_to_rm" },
85        "Xorq": { "opcode": "31", "type": "reg_to_rm" }
86      },
87      "args": [
88        { "class": "GeneralReg64/Mem64", "usage": "use_def" },
89        { "class": "GeneralReg64", "usage": "use" },
90        { "class": "FLAGS", "usage": "def" }
91      ]
92    },
93    {
94      "encodings": {
95        "Addq": { "opcode": "03" },
96        "Andq": { "opcode": "23" },
97        "Orq": { "opcode": "0B" },
98        "Subq": { "opcode": "2B" },
99        "Xorq": { "opcode": "33" }
100      },
101      "args": [
102        { "class": "GeneralReg64", "usage": "use_def" },
103        { "class": "Mem64", "usage": "use" },
104        { "class": "FLAGS", "usage": "def" }
105      ]
106    },
107    {
108      "encodings": {
109        "Addq": { "opcodes": [ "81", "0" ] },
110        "Andq": { "opcodes": [ "81", "4" ] },
111        "Orq": { "opcodes": [ "81", "1" ] },
112        "Subq": { "opcodes": [ "81", "5" ] },
113        "Xorq": { "opcodes": [ "81", "6" ] }
114      },
115      "args": [
116        { "class": "GeneralReg64/Mem64", "usage": "use_def" },
117        { "class": "Imm32" },
118        { "class": "FLAGS", "usage": "def" }
119      ]
120    },
121    {
122      "encodings": {
123        "AddqAccumulator": { "opcodes": [ "48", "05" ] },
124        "AndqAccumulator": { "opcodes": [ "48", "25" ] },
125        "OrqAccumulator": { "opcodes": [ "48", "0D" ] },
126        "SubqAccumulator": { "opcodes": [ "48", "2D" ] },
127        "XorqAccumulator": { "opcodes": [ "48", "35" ] }
128      },
129      "args": [
130        { "class": "RAX", "usage": "use_def" },
131        { "class": "Imm32" },
132        { "class": "FLAGS", "usage": "def" }
133      ]
134    },
135    {
136      "encodings": {
137        "AddqImm8": { "opcodes": [ "83", "0" ] },
138        "AndqImm8": { "opcodes": [ "83", "4" ] },
139        "Btcq": { "opcodes": [ "0F", "BA", "7" ] },
140        "Btq": { "opcodes": [ "0F", "BA", "4" ] },
141        "Btrq": { "opcodes": [ "0F", "BA", "6" ] },
142        "Btsq": { "opcodes": [ "0F", "BA", "5" ] },
143        "OrqImm8": { "opcodes": [ "83", "1" ] },
144        "Rolq": { "opcodes": [ "C1", "0" ] },
145        "Rorq": { "opcodes": [ "C1", "1" ] },
146        "Sarq": { "opcodes": [ "C1", "7" ] },
147        "Shlq": { "opcodes": [ "C1", "4" ] },
148        "Shrq": { "opcodes": [ "C1", "5" ] },
149        "SubqImm8": { "opcodes": [ "83", "5" ] },
150        "XorqImm8": { "opcodes": [ "83", "6" ] }
151      },
152      "args": [
153        { "class": "GeneralReg64/Mem64", "usage": "use_def" },
154        { "class": "Imm8" },
155        { "class": "FLAGS", "usage": "def" }
156      ]
157    },
158    {
159      "encodings": {
160        "Andnq": { "feature": "BMI", "opcodes": [ "C4", "02", "80", "F2" ], "type": "vex_rm_to_reg" }
161      },
162      "args": [
163        { "class": "GeneralReg64", "usage": "def" },
164        { "class": "GeneralReg64", "usage": "use" },
165        { "class": "GeneralReg64/Mem64", "usage": "use" },
166        { "class": "FLAGS", "usage": "def" }
167      ]
168    },
169    {
170      "encodings": {
171        "Bextrq": { "feature": "BMI", "opcodes": [ "C4", "02", "80", "F7" ] },
172        "Bzhiq": { "feature": "BMI2", "opcodes": [ "C4", "02", "80", "F5" ] }
173      },
174      "args": [
175        { "class": "GeneralReg64", "usage": "use_def" },
176        { "class": "GeneralReg64/Mem64", "usage": "use" },
177        { "class": "GeneralReg64", "usage": "use" },
178        { "class": "FLAGS", "usage": "def" }
179      ]
180    },
181    {
182      "encodings": {
183        "Blsiq": { "feature": "BMI", "opcodes": [ "C4", "02", "80", "F3", "3" ], "type": "rm_to_vex" },
184        "Blsmskq": { "feature": "BMI", "opcodes": [ "C4", "02", "80", "F3", "2" ], "type": "rm_to_vex" },
185        "Blsrq": { "feature": "BMI", "opcodes": [ "C4", "02", "80", "F3", "1" ], "type": "rm_to_vex" },
186        "Bsfq": { "opcodes": [ "0F", "BC" ] },
187        "Bsrq": { "opcodes": [ "0F", "BD" ] },
188        "Lzcntq": { "feature": "LZCNT", "opcodes": [ "F3", "0F", "BD" ] },
189        "Popcntq": { "feature": "POPCNT", "opcodes": [ "F3", "0F", "B8" ] },
190        "Tzcntq": { "feature": "BMI", "opcodes": [ "F3", "0F", "BC" ] }
191      },
192      "args": [
193        { "class": "GeneralReg64", "usage": "def" },
194        { "class": "GeneralReg64/Mem64", "usage": "use" },
195        { "class": "FLAGS", "usage": "def" }
196      ]
197    },
198    {
199      "encodings": {
200        "Bswapq": { "opcodes": [ "0F", "C8" ] }
201      },
202      "args": [
203        { "class": "GeneralReg64", "usage": "use_def" }
204      ]
205    },
206    {
207      "encodings": {
208        "Btq": { "opcodes": [ "0F", "A3" ], "type": "reg_to_rm" },
209        "Cmpq": { "opcode": "39", "type": "reg_to_rm" },
210        "Testq": { "opcode": "85", "type": "reg_to_rm" }
211      },
212      "args": [
213        { "class": "GeneralReg64/Mem64", "usage": "use" },
214        { "class": "GeneralReg64", "usage": "use" },
215        { "class": "FLAGS", "usage": "def" }
216      ]
217    },
218    {
219      "encodings": {
220        "Callq": { "opcodes": [ "FF", "2" ] }
221      },
222      "args": [
223        { "class": "RSP", "usage": "use_def" },
224        { "class": "VecMem64", "usage": "use" }
225      ]
226    },
227    {
228      "encodings": {
229        "Cdqe": { "opcodes": [ "48", "98" ] },
230        "Cltq": { "opcodes": [ "48", "98" ] }
231      },
232      "args": [
233        { "class": "EAX", "usage": "use" },
234        { "class": "RAX", "usage": "def" }
235      ]
236    },
237    {
238      "encodings": {
239        "Cmovq": { "opcodes": [ "0F", "40" ] }
240      },
241      "args": [
242        { "class": "Cond" },
243        { "class": "GeneralReg64", "usage": "use_def" },
244        { "class": "GeneralReg64/Mem64", "usage": "use" },
245        { "class": "FLAGS", "usage": "use" }
246      ]
247    },
248    {
249      "encodings": {
250        "CmpXchg16b": { "opcodes": [ "0F", "C7", "1" ] },
251        "Lock CmpXchg16b": { "opcodes": [ "F0", "0F", "C7", "1" ] }
252      },
253      "args": [
254        { "class": "RAX", "usage": "use_def" },
255        { "class": "RDX", "usage": "use_def" },
256        { "class": "RBX", "usage": "use" },
257        { "class": "RCX", "usage": "use" },
258        { "class": "Mem128", "usage": "use_def" },
259        { "class": "FLAGS", "usage": "def" }
260      ]
261    },
262    {
263      "encodings": {
264        "CmpXchgq": { "opcodes": [ "0F", "B1" ], "type": "reg_to_rm" }
265      },
266      "args": [
267        { "class": "RAX", "usage": "use_def" },
268        { "class": "GeneralReg64/Mem64", "usage": "use_def" },
269        { "class": "GeneralReg64", "usage": "use" },
270        { "class": "FLAGS", "usage": "def" }
271      ]
272    },
273    {
274      "encodings": {
275        "Cmpq": { "opcodes": [ "81", "7" ] },
276        "Testq": { "opcodes": [ "F7", "0" ] }
277      },
278      "args": [
279        { "class": "GeneralReg64/Mem64", "usage": "use" },
280        { "class": "Imm32" },
281        { "class": "FLAGS", "usage": "def" }
282      ]
283    },
284    {
285      "encodings": {
286        "Cmpq": { "opcode": "3B" }
287      },
288      "args": [
289        { "class": "GeneralReg64", "usage": "use" },
290        { "class": "Mem64", "usage": "use" },
291        { "class": "FLAGS", "usage": "def" }
292      ]
293    },
294    {
295      "encodings": {
296        "CmpqAccumulator": { "opcodes": [ "48", "3D" ] },
297        "TestqAccumulator": { "opcodes": [ "48", "A9" ] }
298      },
299      "args": [
300        { "class": "RAX", "usage": "use" },
301        { "class": "Imm32" },
302        { "class": "FLAGS", "usage": "def" }
303      ]
304    },
305    {
306      "encodings": {
307        "CmpqImm8": { "opcodes": [ "83", "7" ] }
308      },
309      "args": [
310        { "class": "GeneralReg64/Mem64", "usage": "use" },
311        { "class": "Imm8" },
312        { "class": "FLAGS", "usage": "def" }
313      ]
314    },
315    {
316      "encodings": {
317        "Cqo": { "opcodes": [ "48", "99" ] },
318        "Cqto": { "opcodes": [ "48", "99" ] }
319      },
320      "args": [
321        { "class": "RAX", "usage": "use" },
322        { "class": "RDX", "usage": "def" }
323      ]
324    },
325    {
326      "encodings": {
327        "Crc32q": { "opcodes": [ "F2", "0F", "38", "F1" ] }
328      },
329      "args": [
330        { "class": "GeneralReg64", "usage": "use_def" },
331        { "class": "GeneralReg64/Mem64", "usage": "use" }
332      ]
333    },
334    {
335      "encodings": {
336        "Cvtsd2siq": { "opcodes": [ "F2", "0F", "2D" ] },
337        "Cvttsd2siq": { "opcodes": [ "F2", "0F", "2C" ] }
338      },
339      "args": [
340        { "class": "GeneralReg64", "usage": "def" },
341        { "class": "FpReg64/VecMem64", "usage": "use" }
342      ]
343    },
344    {
345      "encodings": {
346        "Cvtsi2sdq": { "opcodes": [ "F2", "0F", "2A" ] }
347      },
348      "args": [
349        { "class": "FpReg64", "usage": "def" },
350        { "class": "GeneralReg64/Mem64", "usage": "use" }
351      ]
352    },
353    {
354      "encodings": {
355        "Cvtsi2ssq": { "opcodes": [ "F3", "0F", "2A" ] }
356      },
357      "args": [
358        { "class": "FpReg32", "usage": "def" },
359        { "class": "GeneralReg64/Mem64", "usage": "use" }
360      ]
361    },
362    {
363      "encodings": {
364        "Cvtss2siq": { "opcodes": [ "F3", "0F", "2D" ] },
365        "Cvttss2siq": { "opcodes": [ "F3", "0F", "2C" ] }
366      },
367      "args": [
368        { "class": "GeneralReg64", "usage": "def" },
369        { "class": "FpReg32/Mem32", "usage": "use" }
370      ]
371    },
372    {
373      "encodings": {
374        "Decl": { "opcodes": [ "FF", "1" ] },
375        "Incl": { "opcodes": [ "FF", "0" ] }
376      },
377      "args": [
378        { "class": "GeneralReg32", "usage": "use_def" },
379        { "class": "FLAGS", "usage": "def" }
380      ]
381    },
382    {
383      "encodings": {
384        "Decq": { "opcodes": [ "FF", "1" ] },
385        "Incq": { "opcodes": [ "FF", "0" ] },
386        "Negq": { "opcodes": [ "F7", "3" ] },
387        "RolqByOne": { "opcodes": [ "D1", "0" ] },
388        "RorqByOne": { "opcodes": [ "D1", "1" ] },
389        "SarqByOne": { "opcodes": [ "D1", "7" ] },
390        "ShlqByOne": { "opcodes": [ "D1", "4" ] },
391        "ShrqByOne": { "opcodes": [ "D1", "5" ] }
392      },
393      "args": [
394        { "class": "GeneralReg64/Mem64", "usage": "use_def" },
395        { "class": "FLAGS", "usage": "def" }
396      ]
397    },
398    {
399      "encodings": {
400        "Decw": { "opcodes": [ "66", "FF", "1" ] },
401        "Incw": { "opcodes": [ "66", "FF", "0" ] }
402      },
403      "args": [
404        { "class": "GeneralReg16", "usage": "use_def" },
405        { "class": "FLAGS", "usage": "def" }
406      ]
407    },
408    {
409      "encodings": {
410        "Divq": { "opcodes": [ "F7", "6" ] },
411        "Idivq": { "opcodes": [ "F7", "7" ] }
412      },
413      "args": [
414        { "class": "RAX", "usage": "use_def" },
415        { "class": "RDX", "usage": "use_def" },
416        { "class": "GeneralReg64/Mem64", "usage": "use" },
417        { "class": "FLAGS", "usage": "def" }
418      ]
419    },
420    {
421      "encodings": {
422        "Fxrstor64": { "opcodes": [ "0F", "AE", "1" ] }
423      },
424      "args": [
425        { "class": "Mem64", "usage": "use" },
426        { "class": "CC", "usage": "def" }
427      ]
428    },
429    {
430      "encodings": {
431        "Fxsave64": { "opcodes": [ "0F", "AE", "0" ] }
432      },
433      "args": [
434        { "class": "CC", "usage": "def" },
435        { "class": "Mem64", "usage": "use" }
436      ]
437    },
438    {
439      "encodings": {
440        "Imulq": { "opcodes": [ "F7", "5" ] },
441        "Mulq": { "opcodes": [ "F7", "4" ] }
442      },
443      "args": [
444        { "class": "RAX", "usage": "use_def" },
445        { "class": "RDX", "usage": "def" },
446        { "class": "GeneralReg64/Mem64", "usage": "use" },
447        { "class": "FLAGS", "usage": "def" }
448      ]
449    },
450    {
451      "encodings": {
452        "Imulq": { "opcode": "69" }
453      },
454      "args": [
455        { "class": "GeneralReg64", "usage": "def" },
456        { "class": "GeneralReg64/Mem64", "usage": "use" },
457        { "class": "Imm32" },
458        { "class": "FLAGS", "usage": "def" }
459      ]
460    },
461    {
462      "encodings": {
463        "Imulq": { "opcodes": [ "0F", "AF" ] }
464      },
465      "args": [
466        { "class": "GeneralReg64", "usage": "use_def" },
467        { "class": "GeneralReg64/Mem64", "usage": "use" },
468        { "class": "FLAGS", "usage": "def" }
469      ]
470    },
471    {
472      "encodings": {
473        "ImulqImm8": { "opcode": "6B" }
474      },
475      "args": [
476        { "class": "GeneralReg64", "usage": "def" },
477        { "class": "GeneralReg64/Mem64", "usage": "use" },
478        { "class": "Imm8" },
479        { "class": "FLAGS", "usage": "def" }
480      ]
481    },
482    {
483      "encodings": {
484        "Jmpq": { "opcodes": [ "FF", "4" ] }
485      },
486      "args": [
487        { "class": "VecMem64", "usage": "use" }
488      ]
489    },
490    {
491      "encodings": {
492        "Leaq": { "opcode": "8D" }
493      },
494      "args": [
495        { "class": "GeneralReg64", "usage": "def" },
496        { "class": "Mem", "usage": "use" }
497      ]
498    },
499    {
500      "encodings": {
501        "Lock CmpXchgq": { "opcodes": [ "F0", "0F", "B1" ], "type": "reg_to_rm" }
502      },
503      "args": [
504        { "class": "RAX", "usage": "use_def" },
505        { "class": "Mem64", "usage": "use_def" },
506        { "class": "GeneralReg64", "usage": "use" },
507        { "class": "FLAGS", "usage": "def" }
508      ]
509    },
510    {
511      "encodings": {
512        "Lock Xaddq": { "opcodes": [ "F0", "0F", "C1" ], "type": "reg_to_rm" },
513        "Xaddq": { "opcodes": [ "0F", "C1" ], "type": "reg_to_rm" }
514      },
515      "args": [
516        { "class": "Mem64", "usage": "use_def" },
517        { "class": "GeneralReg64", "usage": "use_def" },
518        { "class": "FLAGS", "usage": "use_def" }
519      ]
520    },
521    {
522      "encodings": {
523        "Movq": { "opcodes": [ "66", "0F", "7E" ], "type": "reg_to_rm" },
524        "Vmovq": { "feature": "AVX", "opcodes": [ "C4", "01", "81", "7E" ], "type": "reg_to_rm" }
525      },
526      "args": [
527        { "class": "GeneralReg64", "usage": "def" },
528        { "class": "XmmReg", "usage": "use" }
529      ]
530    },
531    {
532      "encodings": {
533        "Movq": { "opcodes": [ "66", "0F", "6E" ] },
534        "Vmovq": { "feature": "AVX", "opcodes": [ "C4", "01", "81", "6E" ] }
535      },
536      "args": [
537        { "class": "XmmReg", "usage": "def" },
538        { "class": "GeneralReg64", "usage": "use" }
539      ]
540    },
541    {
542      "stems": [ "Movq" ],
543      "args": [
544        { "class": "GeneralReg64", "usage": "def" },
545        { "class": "Imm64" }
546      ]
547    },
548    {
549      "encodings": {
550        "Movq": { "opcode": "8B" }
551      },
552      "args": [
553        { "class": "GeneralReg64", "usage": "def" },
554        { "class": "Mem64", "usage": "use" }
555      ]
556    },
557    {
558      "encodings": {
559        "Movq": { "opcode": "89", "type": "reg_to_rm" }
560      },
561      "args": [
562        { "class": "GeneralReg64/Mem64", "usage": "def" },
563        { "class": "GeneralReg64", "usage": "use" }
564      ]
565    },
566    {
567      "encodings": {
568        "Movq": { "opcodes": [ "C7", "0" ] }
569      },
570      "args": [
571        { "class": "Mem64", "usage": "def" },
572        { "class": "Imm32" }
573      ]
574    },
575    {
576      "encodings": {
577        "Movsxbq": { "opcodes": [ "0F", "BE" ] },
578        "Movzxbq": { "opcodes": [ "0F", "B6" ] }
579      },
580      "args": [
581        { "class": "GeneralReg64", "usage": "def" },
582        { "class": "GeneralReg8/Mem8", "usage": "use" }
583      ]
584    },
585    {
586      "encodings": {
587        "Movsxlq": { "opcode": "63" }
588      },
589      "args": [
590        { "class": "GeneralReg64", "usage": "def" },
591        { "class": "GeneralReg32/Mem32", "usage": "use" }
592      ]
593    },
594    {
595      "encodings": {
596        "Movsxwq": { "opcodes": [ "0F", "BF" ] },
597        "Movzxwq": { "opcodes": [ "0F", "B7" ] }
598      },
599      "args": [
600        { "class": "GeneralReg64", "usage": "def" },
601        { "class": "GeneralReg16/Mem16", "usage": "use" }
602      ]
603    },
604    {
605      "encodings": {
606        "Mulxq": { "feature": "BMI2", "opcodes": [ "C4", "82", "83", "F6" ], "type": "vex_rm_to_reg" },
607        "Pdepq": { "feature": "BMI2", "opcodes": [ "C4", "82", "83", "F5" ], "type": "vex_rm_to_reg" },
608        "Pextq": { "feature": "BMI2", "opcodes": [ "C4", "82", "82", "F5" ], "type": "vex_rm_to_reg" }
609      },
610      "args": [
611        { "class": "GeneralReg64", "usage": "use_def" },
612        { "class": "GeneralReg64", "usage": "use" },
613        { "class": "GeneralReg64/Mem64", "usage": "use" }
614      ]
615    },
616    {
617      "encodings": {
618        "Notq": { "opcodes": [ "F7", "2" ] }
619      },
620      "args": [
621        { "class": "GeneralReg64/Mem64", "usage": "use_def" }
622      ]
623    },
624    {
625      "encodings": {
626        "Pextrq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "16" ], "type": "reg_to_rm" },
627        "Vpextrq": { "feature": "AVX", "opcodes": [ "C4", "03", "81", "16" ], "type": "reg_to_rm" }
628      },
629      "args": [
630        { "class": "GeneralReg64", "usage": "def" },
631        { "class": "VecReg128", "usage": "use" },
632        { "class": "Imm8" }
633      ]
634    },
635    {
636      "encodings": {
637        "Pinsrq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "22" ] }
638      },
639      "args": [
640        { "class": "VecReg128", "usage": "use_def" },
641        { "class": "GeneralReg64", "usage": "use" },
642        { "class": "Imm8" }
643      ]
644    },
645    {
646      "encodings": {
647        "Popq": { "opcodes": [ "8F", "0" ] }
648      },
649      "args": [
650        { "class": "RSP", "usage": "use_def" },
651        { "class": "VecMem64", "usage": "def" }
652      ]
653    },
654    {
655      "encodings": {
656        "Pushq": { "opcodes": [ "FF", "6" ] }
657      },
658      "args": [
659        { "class": "RSP", "usage": "use_def" },
660        { "class": "VecMem64", "usage": "use" }
661      ]
662    },
663    {
664      "encodings": {
665        "RclqByCl": { "opcodes": [ "D3", "2" ] },
666        "RcrqByCl": { "opcodes": [ "D3", "3" ] }
667      },
668      "args": [
669        { "class": "GeneralReg64/Mem64", "usage": "use_def" },
670        { "class": "CL", "usage": "use" },
671        { "class": "FLAGS", "usage": "use_def" }
672      ]
673    },
674    {
675      "encodings": {
676        "RclqByOne": { "opcodes": [ "D1", "2" ] },
677        "RcrqByOne": { "opcodes": [ "D1", "3" ] }
678      },
679      "args": [
680        { "class": "GeneralReg64/Mem64", "usage": "use_def" },
681        { "class": "FLAGS", "usage": "use_def" }
682      ]
683    },
684    {
685      "encodings": {
686        "RolqByCl": { "opcodes": [ "D3", "0" ] },
687        "RorqByCl": { "opcodes": [ "D3", "1" ] },
688        "SarqByCl": { "opcodes": [ "D3", "7" ] },
689        "ShlqByCl": { "opcodes": [ "D3", "4" ] },
690        "ShrqByCl": { "opcodes": [ "D3", "5" ] }
691      },
692      "args": [
693        { "class": "GeneralReg64/Mem64", "usage": "use_def" },
694        { "class": "CL", "usage": "use" },
695        { "class": "FLAGS", "usage": "def" }
696      ]
697    },
698    {
699      "encodings": {
700        "Rorxq": { "feature": "BMI2", "opcodes": [ "C4", "03", "83", "F0" ] }
701      },
702      "args": [
703        { "class": "GeneralReg64", "usage": "def" },
704        { "class": "GeneralReg64/Mem64", "usage": "use" },
705        { "class": "Imm8" }
706      ]
707    },
708    {
709      "encodings": {
710        "Sarxq": { "feature": "BMI2", "opcodes": [ "C4", "02", "82", "F7" ] },
711        "Shlxq": { "feature": "BMI2", "opcodes": [ "C4", "02", "81", "F7" ] },
712        "Shrxq": { "feature": "BMI2", "opcodes": [ "C4", "02", "83", "F7" ] }
713      },
714      "args": [
715        { "class": "GeneralReg64", "usage": "use_def" },
716        { "class": "GeneralReg64/Mem64", "usage": "use" },
717        { "class": "GeneralReg64", "usage": "use" }
718      ]
719    },
720    {
721      "encodings": {
722        "Shldq": { "opcodes": [ "0F", "A4" ], "type": "reg_to_rm" },
723        "Shrdq": { "opcodes": [ "0F", "AC" ], "type": "reg_to_rm" }
724      },
725      "args": [
726        { "class": "GeneralReg64/Mem64", "usage": "use_def" },
727        { "class": "GeneralReg64", "usage": "use" },
728        { "class": "Imm8" },
729        { "class": "FLAGS", "usage": "def" }
730      ]
731    },
732    {
733      "encodings": {
734        "ShldqByCl": { "opcodes": [ "0F", "A5" ], "type": "reg_to_rm" },
735        "ShrdqByCl": { "opcodes": [ "0F", "AD" ], "type": "reg_to_rm" }
736      },
737      "args": [
738        { "class": "GeneralReg64/Mem64", "usage": "use_def" },
739        { "class": "GeneralReg64", "usage": "use" },
740        { "class": "CL", "usage": "use" },
741        { "class": "FLAGS", "usage": "def" }
742      ]
743    },
744    {
745      "stems": [ "Vmovapd", "Vmovaps", "Vmovdqa", "Vmovdqu" ],
746      "feature": "AVX",
747      "args": [
748        { "class": "XmmReg", "usage": "def" },
749        { "class": "XmmReg", "usage": "use" }
750      ]
751    },
752    {
753      "stems": [ "Vmovsd", "Vmovss" ],
754      "args": [
755        { "class": "XmmReg", "usage": "def" },
756        { "class": "XmmReg", "usage": "use" },
757        { "class": "XmmReg", "usage": "use" }
758      ]
759    },
760    {
761      "encodings": {
762        "Vpinsrq": { "feature": "AVX", "opcodes": [ "C4", "03", "81", "22" ], "type": "vex_rm_to_reg" }
763      },
764      "args": [
765        { "class": "VecReg128", "usage": "def" },
766        { "class": "VecReg128", "usage": "use" },
767        { "class": "GeneralReg64", "usage": "use" },
768        { "class": "Imm8" }
769      ]
770    },
771    {
772      "stems": [ "Xchgq" ],
773      "args": [
774        { "class": "GeneralReg64", "usage": "use_def" },
775        { "class": "GeneralReg64", "usage": "use_def" }
776      ]
777    },
778    {
779      "encodings": {
780        "Xchgq": { "opcode": "87" }
781      },
782      "args": [
783        { "class": "GeneralReg64", "usage": "use_def" },
784        { "class": "Mem64", "usage": "use_def" }
785      ]
786    }
787  ]
788}
789