xref: /btstack/port/renesas-tb-s1ja-cc256x/template/btstack_example/synergy_cfg/ssp_cfg/bsp/bsp_clock_cfg.h (revision 3b5c872a8c45689e8cc17891f01530f5aa5e911c)
1 /* generated configuration header file - do not edit */
2 #ifndef BSP_CLOCK_CFG_H_
3 #define BSP_CLOCK_CFG_H_
4 #define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */
5 #define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */
6 #define BSP_CFG_CLOCK_SOURCE (CGC_CLOCK_HOCO) /* Clock Src: HOCO */
7 #define BSP_CFG_ICK_DIV (CGC_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
8 #define BSP_CFG_PCKB_DIV (CGC_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */
9 #define BSP_CFG_PCKD_DIV (CGC_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */
10 #define BSP_CFG_FCK_DIV (CGC_SYS_CLOCK_DIV_2) /* FCLK Div /2 */
11 #define BSP_CFG_SDADC_CLOCK_SOURCE (0) /* Clock Src: HOCO */
12 #define BSP_CFG_SDADCCLK_DIV (7) /* SDADCCLK Div /12 */
13 #endif /* BSP_CLOCK_CFG_H_ */
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