1 /*********************************************************************************************************************** 2 * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. 3 * 4 * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products 5 * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are 6 * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use 7 * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property 8 * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas 9 * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION 10 * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT 11 * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES 12 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR 13 * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM 14 * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION 15 * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, 16 * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, 17 * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY 18 * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. 19 **********************************************************************************************************************/ 20 21 #ifndef BSP_FEATURE_H 22 #define BSP_FEATURE_H 23 24 /*********************************************************************************************************************** 25 * Includes <System Includes> , "Project Includes" 26 **********************************************************************************************************************/ 27 28 /*********************************************************************************************************************** 29 * Macro definitions 30 **********************************************************************************************************************/ 31 32 /** The main oscillator drive value is based upon the oscillator frequency selected in the configuration */ 33 #if (BSP_CFG_XTAL_HZ > (19999999)) 34 #define CGC_MAINCLOCK_DRIVE (0x00U) 35 #elif (BSP_CFG_XTAL_HZ > (15999999)) && (BSP_CFG_XTAL_HZ < (20000000)) 36 #define CGC_MAINCLOCK_DRIVE (0x01U) 37 #elif (BSP_CFG_XTAL_HZ > (7999999)) && (BSP_CFG_XTAL_HZ < (16000000)) 38 #define CGC_MAINCLOCK_DRIVE (0x02U) 39 #else 40 #define CGC_MAINCLOCK_DRIVE (0x03U) 41 #endif 42 43 /*********************************************************************************************************************** 44 * Typedef definitions 45 **********************************************************************************************************************/ 46 47 /*********************************************************************************************************************** 48 * Exported global variables (to be accessed by other files) 49 **********************************************************************************************************************/ 50 51 /*********************************************************************************************************************** 52 * Private global variables and functions 53 **********************************************************************************************************************/ 54 55 #define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0) // Feature not available on this MCU 56 #define BSP_FEATURE_ACMPHS_VREF (0) // Feature not available on this MCU 57 58 #define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0) // Feature not available on this MCU 59 #define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0) // Feature not available on this MCU 60 61 #define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) 62 #define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) 63 #define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) 64 #define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U) 65 #define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) 66 #define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) 67 #define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0U) 68 #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) 69 #define BSP_FEATURE_ADC_HAS_PGA (0U) 70 #define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U) 71 #define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) 72 #define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U) 73 #define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U) 74 #define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) 75 #define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) 76 #define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x0000FFFFU) 77 #define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) // TSCDR is a 32-bit register on this MCU 78 #define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) 79 #define BSP_FEATURE_ADC_TSN_SLOPE (4000) 80 #define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x33FF) // 0 to 9, 12, 13 81 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x7F0007) // 0 to 2, 16 to 22 82 #define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) 83 #define BSP_FEATURE_ADC_HAS_ADBUF (1U) 84 85 #define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0U) 86 #define BSP_FEATURE_ADC_B_TSN_SLOPE (0U) 87 #define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS (0U) 88 #define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS (0U) 89 90 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F) 91 #define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (5) 92 #define BSP_FEATURE_AGT_HAS_AGTW (0U) 93 94 #define BSP_FEATURE_BSP_FLASH_CACHE (1) 95 #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) 96 #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) 97 #define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) 98 #define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (1) 99 #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU 100 #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) 101 #define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU 102 #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU 103 #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U) 104 #define BSP_FEATURE_BSP_HAS_SP_MON (0U) 105 #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA6M4 there are specific registers for configuring the USB clock. 106 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) 107 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) 108 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) 109 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) 110 #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) 111 #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU 112 #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. 113 #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) 114 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) 115 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) 116 #define BSP_FEATURE_BSP_OSIS_PADDING (0U) 117 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) 118 #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) 119 #define BSP_FEATURE_BSP_RESET_TRNG (0U) 120 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. 121 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (50000000U) // The maximum frequency allowed without having one ROM wait cycle. 122 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (150000000U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option). 123 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (100000000U) // The maximum frequency allowed without having two ROM wait cycles. 124 #define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0U) 125 #define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190U) 126 #define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U) 127 128 #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) 129 #define BSP_FEATURE_CAN_CLOCK (0U) 130 #define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) 131 #define BSP_FEATURE_CAN_NUM_CHANNELS (2U) 132 133 #define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU 134 #define BSP_FEATURE_CANFD_LITE (0U) 135 #define BSP_FEATURE_CANFD_FD_SUPPORT (0U) 136 137 #define BSP_FEATURE_CGC_HAS_BCLK (1U) 138 #define BSP_FEATURE_CGC_HAS_FCLK (1U) 139 #define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) 140 #define BSP_FEATURE_CGC_HAS_FLWT (1U) 141 #define BSP_FEATURE_CGC_HAS_FLL (1U) 142 #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) 143 #define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) 144 #define BSP_FEATURE_CGC_HAS_PCLKA (1U) 145 #define BSP_FEATURE_CGC_HAS_PCLKB (1U) 146 #define BSP_FEATURE_CGC_HAS_PCLKC (1U) 147 #define BSP_FEATURE_CGC_HAS_PCLKD (1U) 148 #define BSP_FEATURE_CGC_HAS_PLL (1U) 149 #define BSP_FEATURE_CGC_HAS_PLL2 (1U) // On the RA6M4 there is another PLL that can be used as a clock source for USB and OCTASPI. 150 #define BSP_FEATURE_CGC_HAS_SOSC (1U) 151 #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. 152 #define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) 153 #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) 154 #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) 155 #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) 156 #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) 157 #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz 158 #define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode 159 #define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode 160 #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) 161 #define BSP_FEATURE_CGC_MODRV_MASK (0x30U) 162 #define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U) 163 #define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) 164 #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP 165 #define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (200000000U) 166 #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) 167 #define BSP_FEATURE_CGC_SODRV_MASK (0x02U) 168 #define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) 169 #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) 170 171 #define BSP_FEATURE_CRYPTO_HAS_AES (1) 172 #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) 173 #define BSP_FEATURE_CRYPTO_HAS_ECC (1) 174 #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) 175 #define BSP_FEATURE_CRYPTO_HAS_HASH (1) 176 #define BSP_FEATURE_CRYPTO_HAS_RSA (1) 177 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) 178 #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) 179 #define BSP_FEATURE_CRYPTO_HAS_SCE9 (1) 180 181 #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U) 182 #define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3U) 183 #define BSP_FEATURE_CTSU_HAS_TXVSEL (1) 184 #define BSP_FEATURE_CTSU_VERSION (1) 185 186 #define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU 187 #define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU 188 #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU 189 #define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU 190 191 #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) 192 #define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) 193 #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) 194 #define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U) 195 #define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT (0U) 196 #define BSP_FEATURE_DAC_MAX_CHANNELS (2U) 197 198 #define BSP_FEATURE_DOC_VERSION (1U) 199 200 #define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) 201 #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) 202 203 #define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M4 has Data Watchpoint Cycle Count Register 204 205 #define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Positions of event link set registers (ELSRs) available on this MCU 206 #define BSP_FEATURE_ELC_VERSION (1U) 207 208 #define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) 209 #define BSP_FEATURE_ETHER_MAX_CHANNELS (1U) 210 211 #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000U) 212 #define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) 213 #define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) 214 #define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) 215 #define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128U) 216 #define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U) 217 #define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U) 218 #define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1) 219 #define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (1) 220 #define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x00200000U) 221 #define BSP_FEATURE_FLASH_HP_VERSION (40U) 222 #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU 223 #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU 224 #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU 225 #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU 226 #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU 227 #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU 228 #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU 229 #define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU 230 #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU 231 #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU 232 233 #define BSP_FEATURE_GPTEH_CHANNEL_MASK (0) 234 235 #define BSP_FEATURE_GPTE_CHANNEL_MASK (0) 236 237 #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FU) 238 #define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x1FFU) 239 #define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) 240 #define BSP_FEATURE_GPT_HAS_GTCLKCR (0U) 241 #define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU 242 #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU 243 #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU 244 #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU 245 #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U) 246 #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) 247 248 #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) 249 #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) 250 #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0DFFFFULL) // Note there is another WUPEN1 register 251 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) 252 253 #define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U << 0U) 254 #define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x03) 255 #define BSP_FEATURE_IIC_VERSION (1U) 256 #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) 257 #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) 258 259 #define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU 260 #define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU 261 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU 262 263 #define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) 264 #define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U) 265 266 #define BSP_FEATURE_KINT_HAS_MSTP (0U) 267 268 #define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0U) 269 #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) 270 #define BSP_FEATURE_LPM_DPSIEGR_MASK (0x13FFFFU) 271 #define BSP_FEATURE_LPM_DPSIER_MASK (0x0D1FFFFFU) 272 #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) 273 #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) 274 #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U) 275 #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U) 276 #define BSP_FEATURE_LPM_HAS_STCONR (0U) 277 #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) 278 #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register 279 #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register 280 281 #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) 282 #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) 283 #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V 284 #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V 285 #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V 286 #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V 287 #define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize 288 289 #define BSP_FEATURE_IOPORT_VERSION (1U) 290 291 #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) 292 #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU 293 #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) 294 #define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) 295 #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU 296 #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU 297 #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU 298 #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) 299 #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) 300 301 #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x68000000U) 302 #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x70000000U) 303 304 #define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) 305 306 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) 307 308 #define BSP_FEATURE_RTC_HAS_ROPSEL (0U) 309 310 #define BSP_FEATURE_SCI_VERSION (1U) 311 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x3F9U) 312 #define BSP_FEATURE_SCI_CHANNELS (0x3FFU) 313 #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) 314 #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3F9U) 315 #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) 316 #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x03F9U) // Channel 0, channel 3 to channel 9 have CSTPEN feature 317 318 #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) 319 #define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U) 320 #define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01U) 321 #define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) 322 #define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported 323 324 #define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) 325 326 #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU 327 #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU 328 #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU 329 330 #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) 331 #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) 332 #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) 333 #define BSP_FEATURE_SPI_MAX_CHANNEL (2U) 334 335 #define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01U) 336 337 #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) 338 #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) 339 340 #define BSP_FEATURE_TFU_SPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU 341 342 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) 343 344 #define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) 345 346 #define BSP_FEATURE_BSP_NUM_PMSAR (9U) 347 348 #endif 349