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Searched defs:BaseReg (Results 1 – 25 of 198) sorted by relevance

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/aosp_15_r20/external/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.cpp314 unsigned BaseReg, in isFrameOffsetLegal()
325 unsigned BaseReg, in materializeFrameBaseRegister()
346 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
H A DAArch64LoadStoreOptimizer.cpp1104 unsigned BaseReg = getLdStBaseOp(LoadMI).getReg(); in findMatchingStore() local
1217 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn() local
1422 unsigned BaseReg, int Offset) { in isMatchingUpdateInsn()
1480 unsigned BaseReg = getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnForward() local
1534 unsigned BaseReg = getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnBackward() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp462 Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg(); in checkRegUsage() local
514 Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg(); in optLEAALU() local
573 Register BaseReg = Base.getReg(); in optTwoAddrLEA() local
766 Register BaseReg = Base.getReg(); in processInstrForSlow3OpLEA() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp298 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
354 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses()
460 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp287 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
343 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses()
449 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
/aosp_15_r20/external/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp123 unsigned BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx)); in reservedPrivateSegmentBufferReg() local
272 unsigned BaseReg, in materializeFrameBaseRegister()
303 void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
362 unsigned BaseReg, in isFrameOffsetLegal()
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp497 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
527 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
535 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
548 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
H A DThumbRegisterInfo.cpp125 const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, in emitThumbRegPlusImmInReg()
188 Register BaseReg, int NumBytes, in emitThumbRegPlusImmediate()
441 void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
H A DARMBaseRegisterInfo.cpp681 Register BaseReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in materializeFrameBaseRegister() local
693 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
722 Register BaseReg, in isFrameOffsetLegal()
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.cpp398 unsigned BaseReg, in isFrameOffsetLegal()
408 unsigned BaseReg, in materializeFrameBaseRegister()
429 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
H A DAArch64LoadStoreOptimizer.cpp1176 Register BaseReg = getLdStBaseOp(LoadMI).getReg(); in findMatchingStore() local
1447 Register BaseReg = getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn() local
1703 unsigned BaseReg, int Offset) { in isMatchingUpdateInsn()
1754 Register BaseReg = getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnForward() local
1814 Register BaseReg = getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnBackward() local
/aosp_15_r20/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is16BitMemOperand() local
206 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is32BitMemOperand() local
225 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is64BitMemOperand() local
358 unsigned BaseReg = Base.getReg(); in emitMemModRMByte() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp126 const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmInReg()
189 unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmediate()
430 void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
H A DARMBaseRegisterInfo.cpp631 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister()
655 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
683 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, in isFrameOffsetLegal()
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIFixupVectorISel.cpp86 unsigned &BaseReg, in findSRegBaseAndIndex()
175 unsigned BaseReg = 0; in fixupGlobalSaddr() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp186 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is16BitMemOperand() local
205 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is32BitMemOperand() local
227 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is64BitMemOperand() local
378 unsigned BaseReg = Base.getReg(); in emitMemModRMByte() local
/aosp_15_r20/external/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp125 const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmInReg()
181 unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmediate()
421 void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
H A DARMBaseRegisterInfo.cpp586 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister()
610 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
638 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, in isFrameOffsetLegal()
H A DThumb2SizeReduction.cpp469 unsigned BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
498 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
511 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp1224 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(LoadMI).getReg(); in findMatchingStore() local
1530 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn() local
1865 unsigned BaseReg, int Offset) { in isMatchingUpdateInsn()
1916 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnForward() local
1994 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnBackward() local
H A DAArch64RegisterInfo.cpp711 Register BaseReg, in isFrameOffsetLegal()
733 Register BaseReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass); in materializeFrameBaseRegister() local
745 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp558 Register BaseReg, in isFrameOffsetLegal()
585 Register BaseReg = MFI.createVirtualRegister(&RISCV::GPRRegClass); in materializeFrameBaseRegister() local
594 void RISCVRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/
H A DLocalStackSlotAllocation.cpp272 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg()
345 Register BaseReg; in insertFrameReferenceRegisters() local
/aosp_15_r20/external/llvm/lib/CodeGen/
H A DLocalStackSlotAllocation.cpp255 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg()
326 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp581 for (const SCEV *BaseReg : BaseRegs) in hasRegsUsedByUsesOtherThan() local
598 for (const SCEV *BaseReg : BaseRegs) { in print() local
1342 for (const SCEV *BaseReg : F.BaseRegs) { in RateFormula() local
1552 for (const SCEV *BaseReg : F.BaseRegs) in InsertFormula() local
3366 for (const SCEV *BaseReg : F.BaseRegs) in CountRegisters() local
3574 const SCEV *BaseReg = IsScaledReg ? Base.ScaledReg : Base.BaseRegs[Idx]; in GenerateReassociationsImpl() local
3694 for (const SCEV *BaseReg : Base.BaseRegs) { in GenerateCombinations() local
3880 for (const SCEV *BaseReg : Base.BaseRegs) in GenerateICmpZeroScales() local
4048 for (const SCEV *&BaseReg : F.BaseRegs) { in GenerateTruncates() local
4232 const SCEV *BaseReg = F.BaseRegs[N]; in GenerateCrossUseConstantOffsets() local
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