1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_render_hwcmd_g8_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g8_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_RENDER_HWCMD_G8_X_H__ 29 #define __MHW_RENDER_HWCMD_G8_X_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_render_g8_X 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief MEDIA_OBJECT 50 //! \details 51 //! 52 //! 53 struct MEDIA_OBJECT_CMD 54 { 55 union 56 { 57 //!< DWORD 0 58 struct 59 { 60 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 61 uint32_t MediaCommandSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< MEDIA_COMMAND_SUB_OPCODE 62 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 63 uint32_t MediaCommandPipeline : __CODEGEN_BITFIELD(27, 28) ; //!< MEDIA_COMMAND_PIPELINE 64 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 65 }; 66 uint32_t Value; 67 } DW0; 68 union 69 { 70 //!< DWORD 1 71 struct 72 { 73 uint32_t InterfaceDescriptorOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< Interface Descriptor Offset 74 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 75 }; 76 uint32_t Value; 77 } DW1; 78 union 79 { 80 //!< DWORD 2 81 struct 82 { 83 uint32_t IndirectDataLength : __CODEGEN_BITFIELD( 0, 16) ; //!< Indirect Data Length 84 uint32_t SubsliceDestinationSelect : __CODEGEN_BITFIELD(17, 18) ; //!< SUBSLICE_DESTINATION_SELECT 85 uint32_t SliceDestinationSelect : __CODEGEN_BITFIELD(19, 20) ; //!< SLICE_DESTINATION_SELECT 86 uint32_t UseScoreboard : __CODEGEN_BITFIELD(21, 21) ; //!< USE_SCOREBOARD 87 uint32_t ForceDestination : __CODEGEN_BITFIELD(22, 22) ; //!< Force Destination 88 uint32_t Reserved87 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 89 uint32_t ThreadSynchronization : __CODEGEN_BITFIELD(24, 24) ; //!< THREAD_SYNCHRONIZATION 90 uint32_t Reserved89 : __CODEGEN_BITFIELD(25, 30) ; //!< Reserved 91 uint32_t ChildrenPresent : __CODEGEN_BITFIELD(31, 31) ; //!< Children Present 92 }; 93 uint32_t Value; 94 } DW2; 95 union 96 { 97 //!< DWORD 3 98 struct 99 { 100 uint32_t IndirectDataStartAddress ; //!< Indirect Data Start Address 101 }; 102 uint32_t Value; 103 } DW3; 104 union 105 { 106 //!< DWORD 4 107 struct 108 { 109 uint32_t ScoreboardX : __CODEGEN_BITFIELD( 0, 8) ; //!< Scoreboard X 110 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 111 uint32_t ScoredboardY : __CODEGEN_BITFIELD(16, 24) ; //!< Scoredboard Y 112 uint32_t Reserved153 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 113 }; 114 uint32_t Value; 115 } DW4; 116 union 117 { 118 //!< DWORD 5 119 struct 120 { 121 uint32_t ScoreboardMask : __CODEGEN_BITFIELD( 0, 7) ; //!< Scoreboard Mask 122 uint32_t Reserved168 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 123 uint32_t ScoreboardColor : __CODEGEN_BITFIELD(16, 19) ; //!< Scoreboard Color 124 uint32_t Reserved180 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 125 }; 126 uint32_t Value; 127 } DW5; 128 129 //! \name Local enumerations 130 131 enum MEDIA_COMMAND_SUB_OPCODE 132 { 133 MEDIA_COMMAND_SUB_OPCODE_MEDIAOBJECTSUBOP = 0, //!< No additional details 134 }; 135 136 enum MEDIA_COMMAND_OPCODE 137 { 138 MEDIA_COMMAND_OPCODE_MEDIAOBJECT = 1, //!< No additional details 139 }; 140 141 enum MEDIA_COMMAND_PIPELINE 142 { 143 MEDIA_COMMAND_PIPELINE_MEDIA = 2, //!< No additional details 144 }; 145 146 enum COMMAND_TYPE 147 { 148 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 149 }; 150 151 //! \brief SUBSLICE_DESTINATION_SELECT 152 //! \details 153 //! This field selects the SubSlice that this thread must be sent to. 154 //! Ignored if <b>Force Destination</b> = 0 155 enum SUBSLICE_DESTINATION_SELECT 156 { 157 SUBSLICE_DESTINATION_SELECT_SUBSLICE0 = 0, //!< No additional details 158 SUBSLICE_DESTINATION_SELECT_SUBSLICE1 = 1, //!< No additional details 159 SUBSLICE_DESTINATION_SELECT_SUBSLICE2 = 2, //!< No additional details 160 }; 161 162 //! \brief SLICE_DESTINATION_SELECT 163 //! \details 164 //! This bit along with the subslice destination select determines the slice 165 //! that this thread must be sent to. Ignored if <b>Force Destination</b> = 166 //! 0, or if product only has 1 slice. 167 enum SLICE_DESTINATION_SELECT 168 { 169 SLICE_DESTINATION_SELECT_SLICE0 = 0, //!< No additional details 170 SLICE_DESTINATION_SELECT_SLICE1 = 1, //!< Cannot be used in products without a Slice 1. 171 SLICE_DESTINATION_SELECT_SLICE2 = 2, //!< Cannot be used in products without a Slice 2. 172 }; 173 174 //! \brief USE_SCOREBOARD 175 //! \details 176 //! This field specifies whether the thread associated with this command 177 //! uses hardware scoreboard. Only when this field is set, the scoreboard 178 //! control fields in the VFE Dword are valid. If this field is cleared, the 179 //! thread associated with this command bypasses hardware scoreboard. 180 enum USE_SCOREBOARD 181 { 182 USE_SCOREBOARD_NOTUSINGSCOREBOARD = 0, //!< No additional details 183 USE_SCOREBOARD_USINGSCOREBOARD = 1, //!< No additional details 184 }; 185 186 //! \brief THREAD_SYNCHRONIZATION 187 //! \details 188 //! This field when set indicates that the dispatch of the thread originated 189 //! from this command is based on the "spawn root thread" message. 190 enum THREAD_SYNCHRONIZATION 191 { 192 THREAD_SYNCHRONIZATION_NOTHREADSYNCHRONIZATION = 0, //!< No additional details 193 THREAD_SYNCHRONIZATION_THREADDISPATCHISSYNCHRONIZEDBYTHESPAWNROOTTHREADMESSAGE = 1, //!< No additional details 194 }; 195 196 //! \name Initializations 197 198 //! \brief Explicit member initialization function 199 MEDIA_OBJECT_CMD(); 200 201 static const size_t dwSize = 6; 202 static const size_t byteSize = 24; 203 }; 204 205 //! 206 //! \brief PIPELINE_SELECT 207 //! \details 208 //! The PIPELINE_SELECT command is used to specify which GPE pipeline is to 209 //! be considered the 'current' active pipeline. Issuing 210 //! 3D-pipeline-specific commands when the Media pipeline is selected, or 211 //! vice versa, is UNDEFINED. 212 //! 213 //! Issuing 3D-pipeline-specific commands when the GPGPU pipeline is 214 //! selected, or vice versa, is UNDEFINED. 215 //! 216 //! Programming common non pipeline commands (e.g., STATE_BASE_ADDRESS) is 217 //! allowed in all pipeline modes. 218 //! 219 //! Software must ensure all the write caches are flushed through a stalling 220 //! PIPE_CONTROL command followed by another PIPE_CONTROL command to 221 //! invalidate read only caches prior to programming MI_PIPELINE_SELECT 222 //! command to change the Pipeline Select Mode. Example: ... Workload-3Dmode 223 //! PIPE_CONTROL (CS Stall, Depth Cache Flush Enable, Render Target Cache 224 //! Flush Enable, DC Flush Enable) PIPE_CONTROL (Constant Cache Invalidate, 225 //! Texture Cache Invalidate, Instruction Cache Invalidate, State Cache 226 //! invalidate) PIPELINE_SELECT ( GPGPU) 227 //! 228 //! Software must clear the COLOR_CALC_STATE Valid field in 229 //! 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT with 230 //! Pipeline Select set to GPGPU. 231 //! 232 //! Render CS Only: SW must always program PIPE_CONTROL with CS Stall and 233 //! Render Target Cache Flush Enable set prior to programming 234 //! PIPELINE_SELECT command for GPGPU workloads i.e when pipeline mode is 235 //! set to GPGPU. This is required to achieve better GPGPU preemption 236 //! latencies for certain programming sequences. If programming PIPE_CONTROL 237 //! has performance implications then preemption latencies can be trade off 238 //! against performance by not implementing this programming note. 239 //! 240 //! Hardware Binding Tables are only supported for 3D workloads. Resource 241 //! streamer must be enabled only for 3D workloads. Resource streamer must 242 //! be disabled for Media and GPGPU workloads. Batch buffer containing both 243 //! 3D and GPGPU workloads must take care of disabling and enabling Resource 244 //! Streamer appropriately while changing the PIPELINE_SELECT mode from 3D 245 //! to GPGPU and vice versa. Resource streamer must be disabled using 246 //! MI_RS_CONTROL command and Hardware Binding Tables must be disabled by 247 //! programming 3DSTATE_BINDING_TABLE_POOL_ALLOC with "Binding Table Pool 248 //! Enable" set to disable (i.e. value '0'). Example below shows disabling 249 //! and enabling of resource streamer in a batch buffer for 3D and GPGPU 250 //! workloads. MI_BATCH_BUFFER_START (Resource Streamer Enabled) 251 //! PIPELINE_SELECT (3D) 3DSTATE_BINDING_TABLE_POOL_ALLOC (Binding Table 252 //! Pool Enabled) 3D WORKLOAD MI_RS_CONTROL (Disable Resource Streamer) 253 //! 3DSTATE_BINDING_TABLE_POOL_ALLOC (Binding Table Pool Disabled) 254 //! PIPELINE_SELECT (GPGPU) GPGPU Workload 3DSTATE_BINDING_TABLE_POOL_ALLOC 255 //! (Binding Table Pool Enabled) MI_RS_CONTROL (Enable Resource Streamer) 3D 256 //! WORKLOAD MI_BATCH_BUFFER_END 257 //! 258 //! Render command streamer (RCS) does Fixed Function DOP CG for media and 259 //! gpgpu workloads. During context restore 3D semi pipeline state is 260 //! restored to WM, which triggers implicit flush. Theoretically under 261 //! certain conditions RCS can trigger FFDOP CG while WM in doing implicit 262 //! flush leading to hangs. Only way to resolve this issue is by 263 //! disabling FFDOP CG feature. This issue is being fixed on G0 stepping. 264 //! 265 //! So far this issue is not yet hit in pre-silicon validation, emulation, 266 //! Silicon-SV or Silicon-Driver being a rare condition. 267 //! Disabling FFDOP CG is not being applied at this point to allow valdiaiton 268 //! to make progress on FFDOP CG feature, further decision will be taken 269 //! when this issue occurs. Validation teams are requested to triage any 270 //! GPGPU workload hangs with WM no done with FFDOP CG disabled to eliminate 271 //! this scenario. 272 //! 273 struct PIPELINE_SELECT_CMD 274 { 275 union 276 { 277 //!< DWORD 0 278 struct 279 { 280 uint32_t PipelineSelection : __CODEGEN_BITFIELD( 0, 1) ; //!< PIPELINE_SELECTION 281 uint32_t Reserved2 : __CODEGEN_BITFIELD( 2, 15) ; //!< Reserved 282 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 283 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 284 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 285 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 286 }; 287 uint32_t Value; 288 } DW0; 289 290 //! \name Local enumerations 291 292 enum PIPELINE_SELECTION 293 { 294 PIPELINE_SELECTION_3D = 0, //!< 3D pipeline is selected 295 PIPELINE_SELECTION_MEDIA = 1, //!< Media pipeline is selected (Includes HD optical disc playback, HD video playback, and generic media workloads) 296 PIPELINE_SELECTION_GPGPU = 2, //!< GPGPU pipeline is selected 297 }; 298 299 enum _3D_COMMAND_SUB_OPCODE 300 { 301 _3D_COMMAND_SUB_OPCODE_PIPELINESELECT = 4, //!< No additional details 302 }; 303 304 enum _3D_COMMAND_OPCODE 305 { 306 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 307 }; 308 309 enum COMMAND_SUBTYPE 310 { 311 COMMAND_SUBTYPE_GFXPIPESINGLEDW = 1, //!< No additional details 312 }; 313 314 enum COMMAND_TYPE 315 { 316 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 317 }; 318 319 //! \name Initializations 320 321 //! \brief Explicit member initialization function 322 PIPELINE_SELECT_CMD(); 323 324 static const size_t dwSize = 1; 325 static const size_t byteSize = 4; 326 }; 327 328 //! 329 //! \brief STATE_BASE_ADDRESS 330 //! \details 331 //! The STATE_BASE_ADDRESS command sets the base pointers for subsequent 332 //! state, instruction, and media indirect object accesses by the GPE. 333 //! For more information see the Base Address Utilization table in the 334 //! Memory Access Indirection narrative topic. 335 //! 336 //! The following commands must be reissued following any change to the base 337 //! addresses: 3DSTATE_CC_POINTERS 338 //! 3DSTATE_BINDING_TABLE_POINTERS 339 //! 3DSTATE_SAMPLER_STATE_POINTERS 340 //! 3DSTATE_VIEWPORT_STATE_POINTERS 341 //! MEDIA_STATE_POINTERS 342 //! Execution of this command causes a full pipeline flush, thus its use 343 //! should be minimized for higher performance. 344 //! 345 //! SW must always program PIPE_CONTROL with "CS Stall" and "Render Target 346 //! Cache Flush Enable" set before programming STATE_BASE_ADDRESS command 347 //! for GPGPU workloads i.e when pipeline select is GPGPU via 348 //! PIPELINE_SELECT command. This is required to achieve better GPGPU 349 //! preemption latencies in certain workload programming sequences. If 350 //! programming PIPE_CONTROL has performance implications then preemption 351 //! latencies can be traded off against performance by not implementing this 352 //! programming note. 353 //! 354 struct STATE_BASE_ADDRESS_CMD 355 { 356 union 357 { 358 //!< DWORD 0 359 struct 360 { 361 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 362 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 363 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 364 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 365 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 366 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 367 }; 368 uint32_t Value; 369 } DW0; 370 union 371 { 372 //!< DWORD 1..2 373 struct 374 { 375 uint64_t GeneralStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE 376 uint64_t Reserved33 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 377 uint64_t GeneralStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< General State Memory Object Control State 378 uint64_t Reserved43 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 379 uint64_t GeneralStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< General State Base Address 380 }; 381 uint32_t Value[2]; 382 } DW1_2; 383 union 384 { 385 //!< DWORD 3 386 struct 387 { 388 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 389 uint32_t StatelessDataPortAccessMemoryObjectControlState : __CODEGEN_BITFIELD(16, 22) ; //!< Stateless Data Port Access Memory Object Control State 390 uint32_t Reserved119 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 391 }; 392 uint32_t Value; 393 } DW3; 394 union 395 { 396 //!< DWORD 4..5 397 struct 398 { 399 uint64_t SurfaceStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 400 uint64_t Reserved129 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 401 uint64_t SurfaceStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Surface State Memory Object Control State 402 uint64_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 403 uint64_t SurfaceStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Surface State Base Address 404 }; 405 uint32_t Value[2]; 406 } DW4_5; 407 union 408 { 409 //!< DWORD 6..7 410 struct 411 { 412 uint64_t DynamicStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE 413 uint64_t Reserved193 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 414 uint64_t DynamicStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Dynamic State Memory Object Control State 415 uint64_t Reserved203 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 416 uint64_t DynamicStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Dynamic State Base Address 417 }; 418 uint32_t Value[2]; 419 } DW6_7; 420 union 421 { 422 //!< DWORD 8..9 423 struct 424 { 425 uint64_t IndirectObjectBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE 426 uint64_t Reserved257 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 427 uint64_t IndirectObjectMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Indirect Object Memory Object Control State 428 uint64_t Reserved267 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 429 uint64_t IndirectObjectBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Indirect Object Base Address 430 }; 431 uint32_t Value[2]; 432 } DW8_9; 433 union 434 { 435 //!< DWORD 10..11 436 struct 437 { 438 uint64_t InstructionBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE 439 uint64_t Reserved321 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 440 uint64_t InstructionMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Instruction Memory Object Control State 441 uint64_t Reserved331 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 442 uint64_t InstructionBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Instruction Base Address 443 }; 444 uint32_t Value[2]; 445 } DW10_11; 446 union 447 { 448 //!< DWORD 12 449 struct 450 { 451 uint32_t GeneralStateBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE 452 uint32_t Reserved385 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 453 uint32_t GeneralStateBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< General State Buffer Size 454 }; 455 uint32_t Value; 456 } DW12; 457 union 458 { 459 //!< DWORD 13 460 struct 461 { 462 uint32_t DynamicStateBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE 463 uint32_t Reserved417 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 464 uint32_t DynamicStateBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< Dynamic State Buffer Size 465 }; 466 uint32_t Value; 467 } DW13; 468 union 469 { 470 //!< DWORD 14 471 struct 472 { 473 uint32_t IndirectObjectBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE 474 uint32_t Reserved449 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 475 uint32_t IndirectObjectBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< Indirect Object Buffer Size 476 }; 477 uint32_t Value; 478 } DW14; 479 union 480 { 481 //!< DWORD 15 482 struct 483 { 484 uint32_t InstructionBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE 485 uint32_t Reserved481 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 486 uint32_t InstructionBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< Instruction Buffer Size 487 }; 488 uint32_t Value; 489 } DW15; 490 491 //! \name Local enumerations 492 493 enum _3D_COMMAND_SUB_OPCODE 494 { 495 _3D_COMMAND_SUB_OPCODE_STATEBASEADDRESS = 1, //!< No additional details 496 }; 497 498 enum _3D_COMMAND_OPCODE 499 { 500 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 501 }; 502 503 enum COMMAND_SUBTYPE 504 { 505 COMMAND_SUBTYPE_GFXPIPECOMMON = 0, //!< No additional details 506 }; 507 508 enum COMMAND_TYPE 509 { 510 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 511 }; 512 513 //! \brief GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE 514 //! \details 515 //! <p>The other fields in this DWord and the following DWord are updated 516 //! only when this bit is set.</p> 517 enum GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE 518 { 519 GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 520 GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 521 }; 522 523 //! \brief SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 524 //! \details 525 //! The other fields in this DWord and the following DWord are updated only 526 //! when this bit is set. 527 enum SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 528 { 529 SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 530 SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 531 }; 532 533 //! \brief DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE 534 //! \details 535 //! The other fields in this DWord and the following DWord are updated only 536 //! when this bit is set. 537 enum DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE 538 { 539 DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 540 DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 541 }; 542 543 //! \brief INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE 544 //! \details 545 //! <p>The other fields in this DWord and the following DWord are updated 546 //! only when this bit is set.</p> 547 enum INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE 548 { 549 INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 550 INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 551 }; 552 553 //! \brief INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE 554 //! \details 555 //! <p>The other fields in this DWord and the following DWord are updated 556 //! only when this bit is set.</p> 557 enum INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE 558 { 559 INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 560 INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 561 }; 562 563 //! \brief GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE 564 //! \details 565 //! The bound in this DWord is updated only when this bit is set. 566 enum GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE 567 { 568 GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 569 GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE_ENABLE = 1, //!< Modify the updated bound. 570 }; 571 572 //! \brief DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE 573 //! \details 574 //! FormatDesc 575 enum DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE 576 { 577 DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 578 DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE_ENABLE = 1, //!< Modify the updated bound. 579 }; 580 581 //! \brief INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE 582 //! \details 583 //! FormatDesc 584 enum INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE 585 { 586 INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 587 INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE_ENABLE = 1, //!< Modify the updated bound. 588 }; 589 590 //! \brief INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE 591 //! \details 592 //! FormatDesc 593 enum INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE 594 { 595 INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 596 }; 597 598 //! \name Initializations 599 600 //! \brief Explicit member initialization function 601 STATE_BASE_ADDRESS_CMD(); 602 603 static const size_t dwSize = 16; 604 static const size_t byteSize = 64; 605 }; 606 607 //! 608 //! \brief MEDIA_VFE_STATE 609 //! \details 610 //! A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless the 611 //! only bits that are changed are scoreboard related: Scoreboard Enable, 612 //! Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For these 613 //! scoreboard related states, a MEDIA_STATE_FLUSH is sufficient. 614 //! 615 //! MEDIA_STATE_FLUSH (optional, only if barrier dependency is needed) 616 //! 617 //! MEDIA_INTERFACE_DESCRIPTOR_LOAD (optional) 618 //! 619 //! 620 //! 621 struct MEDIA_VFE_STATE_CMD 622 { 623 union 624 { 625 //!< DWORD 0 626 struct 627 { 628 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 629 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 630 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 631 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 632 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 633 }; 634 uint32_t Value; 635 } DW0; 636 union 637 { 638 //!< DWORD 1 639 struct 640 { 641 uint32_t PerThreadScratchSpace : __CODEGEN_BITFIELD( 0, 3) ; //!< Per Thread Scratch Space 642 uint32_t StackSize : __CODEGEN_BITFIELD( 4, 7) ; //!< Stack Size 643 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 9) ; //!< Reserved 644 uint32_t ScratchSpaceBasePointer : __CODEGEN_BITFIELD(10, 31) ; //!< Scratch Space Base Pointer 645 }; 646 uint32_t Value; 647 } DW1; 648 union 649 { 650 //!< DWORD 2 651 struct 652 { 653 uint32_t ScratchSpaceBasePointerHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Scratch Space Base Pointer High 654 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 655 }; 656 uint32_t Value; 657 } DW2; 658 union 659 { 660 //!< DWORD 3 661 struct 662 { 663 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 664 uint32_t BypassGatewayControl : __CODEGEN_BITFIELD( 6, 6) ; //!< BYPASS_GATEWAY_CONTROL 665 uint32_t ResetGatewayTimer : __CODEGEN_BITFIELD( 7, 7) ; //!< RESET_GATEWAY_TIMER 666 uint32_t NumberOfUrbEntries : __CODEGEN_BITFIELD( 8, 15) ; //!< Number of URB Entries 667 uint32_t MaximumNumberOfThreads : __CODEGEN_BITFIELD(16, 31) ; //!< Maximum Number of Threads 668 }; 669 uint32_t Value; 670 } DW3; 671 union 672 { 673 //!< DWORD 4 674 struct 675 { 676 uint32_t SliceDisable : __CODEGEN_BITFIELD( 0, 1) ; //!< SLICE_DISABLE 677 uint32_t Reserved130 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 678 }; 679 uint32_t Value; 680 } DW4; 681 union 682 { 683 //!< DWORD 5 684 struct 685 { 686 uint32_t CurbeAllocationSize : __CODEGEN_BITFIELD( 0, 15) ; //!< CURBE Allocation Size 687 uint32_t UrbEntryAllocationSize : __CODEGEN_BITFIELD(16, 31) ; //!< URB Entry Allocation Size 688 }; 689 uint32_t Value; 690 } DW5; 691 union 692 { 693 //!< DWORD 6 694 struct 695 { 696 uint32_t ScoreboardMask : __CODEGEN_BITFIELD( 0, 7) ; //!< Scoreboard Mask 697 uint32_t Reserved200 : __CODEGEN_BITFIELD( 8, 29) ; //!< Reserved 698 uint32_t ScoreboardType : __CODEGEN_BITFIELD(30, 30) ; //!< SCOREBOARD_TYPE 699 uint32_t ScoreboardEnable : __CODEGEN_BITFIELD(31, 31) ; //!< SCOREBOARD_ENABLE 700 }; 701 uint32_t Value; 702 } DW6; 703 union 704 { 705 //!< DWORD 7 706 struct 707 { 708 uint32_t Scoreboard0DeltaX : __CODEGEN_BITFIELD( 0, 3) ; //!< Scoreboard 0 Delta X 709 uint32_t Scoreboard0DeltaY : __CODEGEN_BITFIELD( 4, 7) ; //!< Scoreboard 0 Delta Y 710 uint32_t Scoreboard1DeltaX : __CODEGEN_BITFIELD( 8, 11) ; //!< Scoreboard 1 Delta X 711 uint32_t Scoreboard1DeltaY : __CODEGEN_BITFIELD(12, 15) ; //!< Scoreboard 1 Delta Y 712 uint32_t Scoreboard2DeltaX : __CODEGEN_BITFIELD(16, 19) ; //!< Scoreboard 2 Delta X 713 uint32_t Scoreboard2DeltaY : __CODEGEN_BITFIELD(20, 23) ; //!< Scoreboard 2 Delta Y 714 uint32_t Scoreboard3DeltaX : __CODEGEN_BITFIELD(24, 27) ; //!< Scoreboard 3 Delta X 715 uint32_t Scoreboard3DeltaY : __CODEGEN_BITFIELD(28, 31) ; //!< Scoreboard 3 Delta Y 716 }; 717 uint32_t Value; 718 } DW7; 719 union 720 { 721 //!< DWORD 8 722 struct 723 { 724 uint32_t Scoreboard4DeltaX : __CODEGEN_BITFIELD( 0, 3) ; //!< Scoreboard 4 Delta X 725 uint32_t Scoreboard4DeltaY : __CODEGEN_BITFIELD( 4, 7) ; //!< Scoreboard 4 Delta Y 726 uint32_t Scoreboard5DeltaX : __CODEGEN_BITFIELD( 8, 11) ; //!< Scoreboard 5 Delta X 727 uint32_t Scoreboard5DeltaY : __CODEGEN_BITFIELD(12, 15) ; //!< Scoreboard 5 Delta Y 728 uint32_t Scoreboard6DeltaX : __CODEGEN_BITFIELD(16, 19) ; //!< Scoreboard 6 Delta X 729 uint32_t Scoreboard6DeltaY : __CODEGEN_BITFIELD(20, 23) ; //!< Scoreboard 6 Delta Y 730 uint32_t Scoreboard7DeltaX : __CODEGEN_BITFIELD(24, 27) ; //!< Scoreboard 7 Delta X 731 uint32_t Scoreboard7DeltaY : __CODEGEN_BITFIELD(28, 31) ; //!< Scoreboard 7 Delta Y 732 }; 733 uint32_t Value; 734 } DW8; 735 736 //! \name Local enumerations 737 738 enum SUBOPCODE 739 { 740 SUBOPCODE_MEDIAVFESTATESUBOP = 0, //!< No additional details 741 }; 742 743 enum MEDIA_COMMAND_OPCODE 744 { 745 MEDIA_COMMAND_OPCODE_MEDIAVFESTATE = 0, //!< No additional details 746 }; 747 748 enum PIPELINE 749 { 750 PIPELINE_MEDIA = 2, //!< No additional details 751 }; 752 753 enum COMMAND_TYPE 754 { 755 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 756 }; 757 758 //! \brief BYPASS_GATEWAY_CONTROL 759 //! \details 760 //! This field configures Gateway to use a simple message protocol. 761 enum BYPASS_GATEWAY_CONTROL 762 { 763 BYPASS_GATEWAY_CONTROL_MAINTAININGOPENGATEWAYFORWARDMSGCLOSEGATEWAYPROTOCOL_LEGACYMODE = 0, //!< No additional details 764 BYPASS_GATEWAY_CONTROL_BYPASSINGOPENGATEWAYCLOSEGATEWAYPROTOCOL = 1, //!< No additional details 765 }; 766 767 //! \brief RESET_GATEWAY_TIMER 768 //! \details 769 //! This field controls the reset of the timestamp counter maintained in 770 //! Message Gateway. 771 enum RESET_GATEWAY_TIMER 772 { 773 RESET_GATEWAY_TIMER_MAINTAININGTHEEXISTINGTIMESTAMPSTATE = 0, //!< No additional details 774 RESET_GATEWAY_TIMER_RESETTINGRELATIVETIMERANDLATCHINGTHEGLOBALTIMESTAMP = 1, //!< No additional details 775 }; 776 777 //! \brief SLICE_DISABLE 778 //! \details 779 //! This field disables dispatch to slices and subslices for Media and GPGPU 780 //! applications. It is used to limit the amount of scratch space that needs 781 //! to be allocated for a context. If a particular configuration doesn't 782 //! have slice or subslice then there is no impact to disabling it. 783 enum SLICE_DISABLE 784 { 785 SLICE_DISABLE_ALLSUBSLICESENABLED = 0, //!< All subslices are enabled. 786 SLICE_DISABLE_ONLYSLICE0ENABLED = 1, //!< Slice 2 and 1 are disabled, only Slice 0 with all subslices is enabled. 787 SLICE_DISABLE_ONLYSLICE0SUBSLICE0ENABLED = 3, //!< Slice 2 and 1 are disabled, only Slice 0 with only subslice 0 enabled. 788 }; 789 790 //! \brief SCOREBOARD_TYPE 791 //! \details 792 //! This field selects the type of scoreboard in use. 793 enum SCOREBOARD_TYPE 794 { 795 SCOREBOARD_TYPE_STALLINGSCOREBOARD = 0, //!< No additional details 796 SCOREBOARD_TYPE_NON_STALLINGSCOREBOARD = 1, //!< No additional details 797 }; 798 799 //! \brief SCOREBOARD_ENABLE 800 //! \details 801 //! This field enables and disables the hardware scoreboard in the Media 802 //! Pipeline. If this field is cleared, hardware ignores the following 803 //! scoreboard state fields. 804 enum SCOREBOARD_ENABLE 805 { 806 SCOREBOARD_ENABLE_SCOREBOARDDISABLED = 0, //!< No additional details 807 SCOREBOARD_ENABLE_SCOREBOARDENABLED = 1, //!< No additional details 808 }; 809 810 //! \name Initializations 811 812 //! \brief Explicit member initialization function 813 MEDIA_VFE_STATE_CMD(); 814 815 static const size_t dwSize = 9; 816 static const size_t byteSize = 36; 817 }; 818 819 //! 820 //! \brief MEDIA_CURBE_LOAD 821 //! 822 struct MEDIA_CURBE_LOAD_CMD 823 { 824 union 825 { 826 //!< DWORD 0 827 struct 828 { 829 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 830 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 831 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 832 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 833 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 834 }; 835 uint32_t Value; 836 } DW0; 837 union 838 { 839 //!< DWORD 1 840 struct 841 { 842 uint32_t Reserved32 ; //!< Reserved 843 }; 844 uint32_t Value; 845 } DW1; 846 union 847 { 848 //!< DWORD 2 849 struct 850 { 851 uint32_t CurbeTotalDataLength : __CODEGEN_BITFIELD( 0, 16) ; //!< CURBE Total Data Length 852 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 853 }; 854 uint32_t Value; 855 } DW2; 856 union 857 { 858 //!< DWORD 3 859 struct 860 { 861 uint32_t CurbeDataStartAddress ; //!< CURBE Data Start Address 862 }; 863 uint32_t Value; 864 } DW3; 865 866 //! \name Local enumerations 867 868 enum SUBOPCODE 869 { 870 SUBOPCODE_MEDIACURBELOADSUBOP = 1, //!< No additional details 871 }; 872 873 enum MEDIA_COMMAND_OPCODE 874 { 875 MEDIA_COMMAND_OPCODE_MEDIACURBELOAD = 0, //!< No additional details 876 }; 877 878 enum PIPELINE 879 { 880 PIPELINE_MEDIA = 2, //!< No additional details 881 }; 882 883 enum COMMAND_TYPE 884 { 885 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 886 }; 887 888 //! \name Initializations 889 890 //! \brief Explicit member initialization function 891 MEDIA_CURBE_LOAD_CMD(); 892 893 static const size_t dwSize = 4; 894 static const size_t byteSize = 16; 895 }; 896 897 //! 898 //! \brief MEDIA_INTERFACE_DESCRIPTOR_LOAD 899 //! \details 900 //! A Media_State_Flush should be used before this command to ensure that 901 //! the temporary Interface Descriptor storage is cleared. 902 struct MEDIA_INTERFACE_DESCRIPTOR_LOAD_CMD 903 { 904 union 905 { 906 //!< DWORD 0 907 struct 908 { 909 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 910 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 911 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 912 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 913 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 914 }; 915 uint32_t Value; 916 } DW0; 917 union 918 { 919 //!< DWORD 1 920 struct 921 { 922 uint32_t Reserved32 ; //!< Reserved 923 }; 924 uint32_t Value; 925 } DW1; 926 union 927 { 928 //!< DWORD 2 929 struct 930 { 931 uint32_t InterfaceDescriptorTotalLength : __CODEGEN_BITFIELD( 0, 16) ; //!< Interface Descriptor Total Length 932 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 933 }; 934 uint32_t Value; 935 } DW2; 936 union 937 { 938 //!< DWORD 3 939 struct 940 { 941 uint32_t InterfaceDescriptorDataStartAddress ; //!< Interface Descriptor Data Start Address 942 }; 943 uint32_t Value; 944 } DW3; 945 946 //! \name Local enumerations 947 948 enum SUBOPCODE 949 { 950 SUBOPCODE_MEDIAINTERFACEDESCRIPTORLOADSUBOP = 2, //!< No additional details 951 }; 952 953 enum MEDIA_COMMAND_OPCODE 954 { 955 MEDIA_COMMAND_OPCODE_MEDIAINTERFACEDESCRIPTORLOAD = 0, //!< No additional details 956 }; 957 958 enum PIPELINE 959 { 960 PIPELINE_MEDIA = 2, //!< No additional details 961 }; 962 963 enum COMMAND_TYPE 964 { 965 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 966 }; 967 968 //! \name Initializations 969 970 //! \brief Explicit member initialization function 971 MEDIA_INTERFACE_DESCRIPTOR_LOAD_CMD(); 972 973 static const size_t dwSize = 4; 974 static const size_t byteSize = 16; 975 }; 976 977 //! 978 //! \brief MEDIA_OBJECT_WALKER 979 //! \details 980 //! 981 //! 982 struct MEDIA_OBJECT_WALKER_CMD 983 { 984 union 985 { 986 //!< DWORD 0 987 struct 988 { 989 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 990 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 991 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 992 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 993 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 994 }; 995 uint32_t Value; 996 } DW0; 997 union 998 { 999 //!< DWORD 1 1000 struct 1001 { 1002 uint32_t InterfaceDescriptorOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< Interface Descriptor Offset 1003 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 1004 }; 1005 uint32_t Value; 1006 } DW1; 1007 union 1008 { 1009 //!< DWORD 2 1010 struct 1011 { 1012 uint32_t IndirectDataLength : __CODEGEN_BITFIELD( 0, 16) ; //!< Indirect Data Length 1013 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 20) ; //!< Reserved 1014 uint32_t UseScoreboard : __CODEGEN_BITFIELD(21, 21) ; //!< USE_SCOREBOARD 1015 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 1016 uint32_t ThreadSynchronization : __CODEGEN_BITFIELD(24, 24) ; //!< THREAD_SYNCHRONIZATION 1017 uint32_t Reserved89 : __CODEGEN_BITFIELD(25, 30) ; //!< Reserved 1018 uint32_t ChildrenPresent : __CODEGEN_BITFIELD(31, 31) ; //!< Children Present 1019 }; 1020 uint32_t Value; 1021 } DW2; 1022 union 1023 { 1024 //!< DWORD 3 1025 struct 1026 { 1027 uint32_t IndirectDataStartAddress ; //!< Indirect Data Start Address 1028 }; 1029 uint32_t Value; 1030 } DW3; 1031 union 1032 { 1033 //!< DWORD 4 1034 struct 1035 { 1036 uint32_t Reserved128 ; //!< Reserved 1037 }; 1038 uint32_t Value; 1039 } DW4; 1040 union 1041 { 1042 //!< DWORD 5 1043 struct 1044 { 1045 uint32_t ScoreboardMask : __CODEGEN_BITFIELD( 0, 7) ; //!< Scoreboard Mask 1046 uint32_t GroupIdLoopSelect : __CODEGEN_BITFIELD( 8, 31) ; //!< GROUP_ID_LOOP_SELECT 1047 }; 1048 uint32_t Value; 1049 } DW5; 1050 union 1051 { 1052 //!< DWORD 6 1053 struct 1054 { 1055 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 1056 uint32_t MidLoopUnitX : __CODEGEN_BITFIELD( 8, 9) ; //!< Mid-Loop Unit X 1057 uint32_t Reserved202 : __CODEGEN_BITFIELD(10, 11) ; //!< Reserved 1058 uint32_t LocalMidLoopUnitY : __CODEGEN_BITFIELD(12, 13) ; //!< Local Mid-Loop Unit Y 1059 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1060 uint32_t MiddleLoopExtraSteps : __CODEGEN_BITFIELD(16, 20) ; //!< Middle Loop Extra Steps 1061 uint32_t Reserved213 : __CODEGEN_BITFIELD(21, 23) ; //!< Reserved 1062 uint32_t ColorCountMinusOne : __CODEGEN_BITFIELD(24, 27) ; //!< Color Count Minus One 1063 uint32_t Reserved220 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1064 }; 1065 uint32_t Value; 1066 } DW6; 1067 union 1068 { 1069 //!< DWORD 7 1070 struct 1071 { 1072 uint32_t LocalLoopExecCount : __CODEGEN_BITFIELD( 0, 9) ; //!< Local Loop Exec Count 1073 uint32_t Reserved234 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1074 uint32_t GlobalLoopExecCount : __CODEGEN_BITFIELD(16, 25) ; //!< Global Loop Exec Count 1075 uint32_t Reserved250 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 1076 }; 1077 uint32_t Value; 1078 } DW7; 1079 union 1080 { 1081 //!< DWORD 8 1082 struct 1083 { 1084 uint32_t BlockResolutionX : __CODEGEN_BITFIELD( 0, 8) ; //!< Block Resolution X 1085 uint32_t Reserved265 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 1086 uint32_t BlockResolutionY : __CODEGEN_BITFIELD(16, 24) ; //!< Block Resolution Y 1087 uint32_t Reserved281 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 1088 }; 1089 uint32_t Value; 1090 } DW8; 1091 union 1092 { 1093 //!< DWORD 9 1094 struct 1095 { 1096 uint32_t LocalStartX : __CODEGEN_BITFIELD( 0, 8) ; //!< Local Start X 1097 uint32_t Reserved297 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 1098 uint32_t LocalStartY : __CODEGEN_BITFIELD(16, 24) ; //!< Local Start Y 1099 uint32_t Reserved313 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 1100 }; 1101 uint32_t Value; 1102 } DW9; 1103 union 1104 { 1105 //!< DWORD 10 1106 struct 1107 { 1108 uint32_t Reserved320 ; //!< Reserved 1109 }; 1110 uint32_t Value; 1111 } DW10; 1112 union 1113 { 1114 //!< DWORD 11 1115 struct 1116 { 1117 uint32_t LocalOuterLoopStrideX : __CODEGEN_BITFIELD( 0, 9) ; //!< Local Outer Loop Stride X 1118 uint32_t Reserved362 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1119 uint32_t LocalOuterLoopStrideY : __CODEGEN_BITFIELD(16, 25) ; //!< Local Outer Loop Stride Y 1120 uint32_t Reserved378 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 1121 }; 1122 uint32_t Value; 1123 } DW11; 1124 union 1125 { 1126 //!< DWORD 12 1127 struct 1128 { 1129 uint32_t LocalInnerLoopUnitX : __CODEGEN_BITFIELD( 0, 9) ; //!< Local Inner Loop Unit X 1130 uint32_t Reserved394 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1131 uint32_t LocalInnerLoopUnitY : __CODEGEN_BITFIELD(16, 25) ; //!< Local Inner Loop Unit Y 1132 uint32_t Reserved410 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 1133 }; 1134 uint32_t Value; 1135 } DW12; 1136 union 1137 { 1138 //!< DWORD 13 1139 struct 1140 { 1141 uint32_t GlobalResolutionX : __CODEGEN_BITFIELD( 0, 8) ; //!< Global Resolution X 1142 uint32_t Reserved425 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 1143 uint32_t GlobalResolutionY : __CODEGEN_BITFIELD(16, 24) ; //!< Global Resolution Y 1144 uint32_t Reserved441 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 1145 }; 1146 uint32_t Value; 1147 } DW13; 1148 union 1149 { 1150 //!< DWORD 14 1151 struct 1152 { 1153 uint32_t GlobalStartX : __CODEGEN_BITFIELD( 0, 9) ; //!< Global Start X 1154 uint32_t Reserved458 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1155 uint32_t GlobalStartY : __CODEGEN_BITFIELD(16, 25) ; //!< Global Start Y 1156 uint32_t Reserved474 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 1157 }; 1158 uint32_t Value; 1159 } DW14; 1160 union 1161 { 1162 //!< DWORD 15 1163 struct 1164 { 1165 uint32_t GlobalOuterLoopStrideX : __CODEGEN_BITFIELD( 0, 9) ; //!< Global Outer Loop Stride X 1166 uint32_t Reserved490 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1167 uint32_t GlobalOuterLoopStrideY : __CODEGEN_BITFIELD(16, 25) ; //!< Global Outer Loop Stride Y 1168 uint32_t Reserved506 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 1169 }; 1170 uint32_t Value; 1171 } DW15; 1172 union 1173 { 1174 //!< DWORD 16 1175 struct 1176 { 1177 uint32_t GlobalInnerLoopUnitX : __CODEGEN_BITFIELD( 0, 9) ; //!< Global Inner Loop Unit X 1178 uint32_t Reserved522 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1179 uint32_t GlobalInnerLoopUnitY : __CODEGEN_BITFIELD(16, 25) ; //!< Global Inner Loop Unit Y 1180 uint32_t Reserved538 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 1181 }; 1182 uint32_t Value; 1183 } DW16; 1184 1185 //! \name Local enumerations 1186 1187 enum SUBOPCODE 1188 { 1189 SUBOPCODE_MEDIAOBJECTWALKERSUBOP = 3, //!< No additional details 1190 }; 1191 1192 enum MEDIA_COMMAND_OPCODE 1193 { 1194 MEDIA_COMMAND_OPCODE_MEDIAOBJECTWALKER = 1, //!< No additional details 1195 }; 1196 1197 enum PIPELINE 1198 { 1199 PIPELINE_MEDIA = 2, //!< No additional details 1200 }; 1201 1202 enum COMMAND_TYPE 1203 { 1204 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1205 }; 1206 1207 //! \brief USE_SCOREBOARD 1208 //! \details 1209 //! This field specifies whether the thread associated with this command 1210 //! uses hardware scoreboard. Only when this field is set, the scoreboard 1211 //! control fields in the VFE Dword are valid. If this field is cleared, the 1212 //! thread associated with this command bypasses hardware scoreboard. 1213 enum USE_SCOREBOARD 1214 { 1215 USE_SCOREBOARD_NOTUSINGSCOREBOARD = 0, //!< No additional details 1216 USE_SCOREBOARD_USINGSCOREBOARD = 1, //!< No additional details 1217 }; 1218 1219 //! \brief THREAD_SYNCHRONIZATION 1220 //! \details 1221 //! This field when set indicates that the dispatch of the thread originated 1222 //! from this command is based on the "spawn root thread" message. 1223 enum THREAD_SYNCHRONIZATION 1224 { 1225 THREAD_SYNCHRONIZATION_NOTHREADSYNCHRONIZATION = 0, //!< No additional details 1226 THREAD_SYNCHRONIZATION_THREADDISPATCHISSYNCHRONIZEDBYTHESPAWNROOTTHREADMESSAGE = 1, //!< No additional details 1227 }; 1228 1229 //! \brief GROUP_ID_LOOP_SELECT 1230 //! \details 1231 //! This bit field chooses which of the nested loops of the walker are used 1232 //! to identify threads which share a group id and therefore a shared 1233 //! barrier and SLM. The programmer must ensure that each group will fit 1234 //! into a single subslice. When barriers are enabled every group must have 1235 //! the same number of threads matching the number specified in the 1236 //! Interface Descriptor. 1237 enum GROUP_ID_LOOP_SELECT 1238 { 1239 GROUP_ID_LOOP_SELECT_UNNAMED0 = 0, //!< Groups are not created, barriers and SLM are not allocated 1240 GROUP_ID_LOOP_SELECT_UNNAMED1 = 1, //!< Each complete iteration of the Color loop defines a group, the group id is the concatenation of the Outer global, Inner global, Outer local, Mid local and Inner local loop execution counts. 1241 GROUP_ID_LOOP_SELECT_UNNAMED2 = 2, //!< Each complete iteration of the Inner local loop and Color loop defines a group, the group id is the concatenation of the Outer global loop to the Mid local loop execution counts. 1242 GROUP_ID_LOOP_SELECT_UNNAMED3 = 3, //!< Each complete iteration of the Mid local loop and lower loops defines a group, the group id is the concatenation of the Outer global loop to the Outer local loop execution counts. 1243 GROUP_ID_LOOP_SELECT_UNNAMED4 = 4, //!< Each complete iteration of the Outer local loop and lower loops defines a group, the group id is the concatenation of the Outer global loop and the Inner global loop execution counts. 1244 GROUP_ID_LOOP_SELECT_UNNAMED5 = 5, //!< Each complete iteration of the Inner global loop and lower loops defines a group, the group id is the Outer global loop execution count. 1245 }; 1246 1247 //! \name Initializations 1248 1249 //! \brief Explicit member initialization function 1250 MEDIA_OBJECT_WALKER_CMD(); 1251 1252 static const size_t dwSize = 17; 1253 static const size_t byteSize = 68; 1254 }; 1255 1256 //! 1257 //! \brief GPGPU_WALKER 1258 //! \details 1259 //! If the threads spawned by this command are required to observe memory 1260 //! writes performed by threads spawned from a previous command, software 1261 //! must precede this command with a command that performs a memory flush 1262 //! (e.g., MI_FLUSH). 1263 //! 1264 struct GPGPU_WALKER_CMD 1265 { 1266 union 1267 { 1268 //!< DWORD 0 1269 struct 1270 { 1271 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1272 uint32_t PredicateEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< Predicate Enable 1273 uint32_t Reserved9 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 1274 uint32_t IndirectParameterEnable : __CODEGEN_BITFIELD(10, 10) ; //!< Indirect Parameter Enable 1275 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1276 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 1277 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1278 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1279 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1280 }; 1281 uint32_t Value; 1282 } DW0; 1283 union 1284 { 1285 //!< DWORD 1 1286 struct 1287 { 1288 uint32_t InterfaceDescriptorOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< Interface Descriptor Offset 1289 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 1290 }; 1291 uint32_t Value; 1292 } DW1; 1293 union 1294 { 1295 //!< DWORD 2 1296 struct 1297 { 1298 uint32_t IndirectDataLength : __CODEGEN_BITFIELD( 0, 16) ; //!< Indirect Data Length 1299 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1300 }; 1301 uint32_t Value; 1302 } DW2; 1303 union 1304 { 1305 //!< DWORD 3 1306 struct 1307 { 1308 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1309 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Indirect Data Start Address 1310 }; 1311 uint32_t Value; 1312 } DW3; 1313 union 1314 { 1315 //!< DWORD 4 1316 struct 1317 { 1318 uint32_t ThreadWidthCounterMaximum : __CODEGEN_BITFIELD( 0, 5) ; //!< Thread Width Counter Maximum 1319 uint32_t Reserved134 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 1320 uint32_t ThreadHeightCounterMaximum : __CODEGEN_BITFIELD( 8, 13) ; //!< Thread Height Counter Maximum 1321 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1322 uint32_t ThreadDepthCounterMaximum : __CODEGEN_BITFIELD(16, 21) ; //!< Thread Depth Counter Maximum 1323 uint32_t Reserved150 : __CODEGEN_BITFIELD(22, 29) ; //!< Reserved 1324 uint32_t SimdSize : __CODEGEN_BITFIELD(30, 31) ; //!< SIMD_SIZE 1325 }; 1326 uint32_t Value; 1327 } DW4; 1328 union 1329 { 1330 //!< DWORD 5 1331 struct 1332 { 1333 uint32_t ThreadGroupIdStartingX ; //!< Thread Group ID Starting X 1334 }; 1335 uint32_t Value; 1336 } DW5; 1337 union 1338 { 1339 //!< DWORD 6 1340 struct 1341 { 1342 uint32_t Reserved192 ; //!< Reserved 1343 }; 1344 uint32_t Value; 1345 } DW6; 1346 union 1347 { 1348 //!< DWORD 7 1349 struct 1350 { 1351 uint32_t ThreadGroupIdXDimension ; //!< Thread Group ID X Dimension 1352 }; 1353 uint32_t Value; 1354 } DW7; 1355 union 1356 { 1357 //!< DWORD 8 1358 struct 1359 { 1360 uint32_t ThreadGroupIdStartingY ; //!< Thread Group ID Starting Y 1361 }; 1362 uint32_t Value; 1363 } DW8; 1364 union 1365 { 1366 //!< DWORD 9 1367 struct 1368 { 1369 uint32_t Reserved288 ; //!< Reserved 1370 }; 1371 uint32_t Value; 1372 } DW9; 1373 union 1374 { 1375 //!< DWORD 10 1376 struct 1377 { 1378 uint32_t ThreadGroupIdYDimension ; //!< Thread Group ID Y Dimension 1379 }; 1380 uint32_t Value; 1381 } DW10; 1382 union 1383 { 1384 //!< DWORD 11 1385 struct 1386 { 1387 uint32_t ThreadGroupIdStartingResumeZ ; //!< Thread Group ID Starting/Resume Z 1388 }; 1389 uint32_t Value; 1390 } DW11; 1391 union 1392 { 1393 //!< DWORD 12 1394 struct 1395 { 1396 uint32_t ThreadGroupIdZDimension ; //!< Thread Group ID Z Dimension 1397 }; 1398 uint32_t Value; 1399 } DW12; 1400 union 1401 { 1402 //!< DWORD 13 1403 struct 1404 { 1405 uint32_t RightExecutionMask ; //!< Right Execution Mask 1406 }; 1407 uint32_t Value; 1408 } DW13; 1409 union 1410 { 1411 //!< DWORD 14 1412 struct 1413 { 1414 uint32_t BottomExecutionMask ; //!< Bottom Execution Mask 1415 }; 1416 uint32_t Value; 1417 } DW14; 1418 1419 //! \name Local enumerations 1420 1421 enum SUBOPCODE 1422 { 1423 SUBOPCODE_GPGPUWALKERSUBOP = 5, //!< No additional details 1424 }; 1425 1426 enum MEDIA_COMMAND_OPCODE 1427 { 1428 MEDIA_COMMAND_OPCODE_GPGPUWALKER = 1, //!< No additional details 1429 }; 1430 1431 enum PIPELINE 1432 { 1433 PIPELINE_MEDIA = 2, //!< No additional details 1434 }; 1435 1436 enum COMMAND_TYPE 1437 { 1438 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1439 }; 1440 1441 //! \brief SIMD_SIZE 1442 //! \details 1443 //! This field determines the size of the payload and the number of bits of 1444 //! the execution mask that are expected. The kernel pointed to by the 1445 //! interface descriptor should match the SIMD declared here. 1446 enum SIMD_SIZE 1447 { 1448 SIMD_SIZE_SIMD8 = 0, //!< 8 LSBs of the execution mask are used 1449 SIMD_SIZE_SIMD16 = 1, //!< 16 LSBs used in execution mask 1450 SIMD_SIZE_SIMD32 = 2, //!< 32 bits of execution mask used 1451 }; 1452 1453 //! \name Initializations 1454 1455 //! \brief Explicit member initialization function 1456 GPGPU_WALKER_CMD(); 1457 1458 static const size_t dwSize = 15; 1459 static const size_t byteSize = 60; 1460 }; 1461 1462 //! 1463 //! \brief _3DSTATE_CHROMA_KEY 1464 //! \details 1465 //! The 3DSTATE_CHROMA_KEY instruction is used to program texture 1466 //! color/chroma-key key values. A table containing four set of values is 1467 //! supported. The ChromaKey Index sampler state variable is used to select 1468 //! which table entry is associated with the map. Texture chromakey 1469 //! functions are enabled and controlled via use of the ChromaKey Enable 1470 //! texture sampler state variable.Texture Color Key (keying on a paletted 1471 //! texture index) is not supported. 1472 //! 1473 struct _3DSTATE_CHROMA_KEY_CMD 1474 { 1475 union 1476 { 1477 //!< DWORD 0 1478 struct 1479 { 1480 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1481 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1482 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1483 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1484 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1485 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1486 }; 1487 uint32_t Value; 1488 } DW0; 1489 union 1490 { 1491 //!< DWORD 1 1492 struct 1493 { 1494 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 29) ; //!< Reserved 1495 uint32_t ChromakeyTableIndex : __CODEGEN_BITFIELD(30, 31) ; //!< ChromaKey Table Index 1496 }; 1497 uint32_t Value; 1498 } DW1; 1499 union 1500 { 1501 //!< DWORD 2 1502 struct 1503 { 1504 uint32_t ChromakeyLowValue ; //!< ChromaKey Low Value 1505 }; 1506 uint32_t Value; 1507 } DW2; 1508 union 1509 { 1510 //!< DWORD 3 1511 struct 1512 { 1513 uint32_t ChromakeyHighValue ; //!< ChromaKey High Value 1514 }; 1515 uint32_t Value; 1516 } DW3; 1517 1518 //! \name Local enumerations 1519 1520 enum _3D_COMMAND_SUB_OPCODE 1521 { 1522 _3D_COMMAND_SUB_OPCODE_3DSTATECHROMAKEY = 4, //!< No additional details 1523 }; 1524 1525 enum _3D_COMMAND_OPCODE 1526 { 1527 _3D_COMMAND_OPCODE_3DSTATENONPIPELINED = 1, //!< No additional details 1528 }; 1529 1530 enum COMMAND_SUBTYPE 1531 { 1532 COMMAND_SUBTYPE_GFXPIPE3D = 3, //!< No additional details 1533 }; 1534 1535 enum COMMAND_TYPE 1536 { 1537 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1538 }; 1539 1540 //! \name Initializations 1541 1542 //! \brief Explicit member initialization function 1543 _3DSTATE_CHROMA_KEY_CMD(); 1544 1545 static const size_t dwSize = 4; 1546 static const size_t byteSize = 16; 1547 }; 1548 1549 //! 1550 //! \brief _3DSTATE_SAMPLER_PALETTE_LOAD0 1551 //! \details 1552 //! The 3DSTATE_SAMPLER_PALETTE_LOAD0 instruction is used to load 32-bit 1553 //! values into the first texture palette. The texture palette is used 1554 //! whenever a texture with a paletted format (containing "Px [palette0]") 1555 //! is referenced by the sampler. 1556 //! 1557 //! This instruction is used to load all or a subset of the 256 entries of 1558 //! the first palette. Partial loads always start from the first (index 0) 1559 //! entry. 1560 //! 1561 struct _3DSTATE_SAMPLER_PALETTE_LOAD0_CMD 1562 { 1563 union 1564 { 1565 //!< DWORD 0 1566 struct 1567 { 1568 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWord Length 1569 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1570 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1571 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1572 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1573 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1574 }; 1575 uint32_t Value; 1576 } DW0; 1577 1578 //! \name Local enumerations 1579 1580 enum _3D_COMMAND_SUB_OPCODE 1581 { 1582 _3D_COMMAND_SUB_OPCODE_3DSTATESAMPLERPALETTELOAD0 = 2, //!< No additional details 1583 }; 1584 1585 enum _3D_COMMAND_OPCODE 1586 { 1587 _3D_COMMAND_OPCODE_3DSTATENONPIPELINED = 1, //!< No additional details 1588 }; 1589 1590 enum COMMAND_SUBTYPE 1591 { 1592 COMMAND_SUBTYPE_GFXPIPE3D = 3, //!< No additional details 1593 }; 1594 1595 enum COMMAND_TYPE 1596 { 1597 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1598 }; 1599 1600 //! \name Initializations 1601 1602 //! \brief Explicit member initialization function 1603 _3DSTATE_SAMPLER_PALETTE_LOAD0_CMD(); 1604 1605 static const size_t dwSize = 1; 1606 static const size_t byteSize = 4; 1607 }; 1608 1609 //! 1610 //! \brief _3DSTATE_SAMPLER_PALETTE_LOAD1 1611 //! \details 1612 //! The 3DSTATE_SAMPLER_PALETTE_LOAD1 instruction is used to load 32-bit 1613 //! values into the second texture palette. The second texture palette is 1614 //! used whenever a texture with a paletted format (containing 1615 //! "Px...[palette1]") is referenced by the sampler.This instruction is used 1616 //! to load all or a subset of the 256 entries of the second palette. 1617 //! Partial loads always start from the first (index 0) entry. 1618 //! 1619 struct _3DSTATE_SAMPLER_PALETTE_LOAD1_CMD 1620 { 1621 union 1622 { 1623 //!< DWORD 0 1624 struct 1625 { 1626 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1627 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1628 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1629 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1630 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1631 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1632 }; 1633 uint32_t Value; 1634 } DW0; 1635 1636 //! \name Local enumerations 1637 1638 enum _3D_COMMAND_SUB_OPCODE 1639 { 1640 _3D_COMMAND_SUB_OPCODE_3DSTATESAMPLERPALETTELOAD1 = 12, //!< No additional details 1641 }; 1642 1643 enum _3D_COMMAND_OPCODE 1644 { 1645 _3D_COMMAND_OPCODE_3DSTATENONPIPELINED = 1, //!< No additional details 1646 }; 1647 1648 enum COMMAND_SUBTYPE 1649 { 1650 COMMAND_SUBTYPE_GFXPIPE3D = 3, //!< No additional details 1651 }; 1652 1653 enum COMMAND_TYPE 1654 { 1655 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1656 }; 1657 1658 //! \name Initializations 1659 1660 //! \brief Explicit member initialization function 1661 _3DSTATE_SAMPLER_PALETTE_LOAD1_CMD(); 1662 1663 static const size_t dwSize = 1; 1664 static const size_t byteSize = 4; 1665 }; 1666 1667 //! 1668 //! \brief PALETTE_ENTRY 1669 //! \details 1670 //! 1671 //! 1672 struct PALETTE_ENTRY_CMD 1673 { 1674 union 1675 { 1676 //!< DWORD 0 1677 struct 1678 { 1679 uint32_t Blue : __CODEGEN_BITFIELD( 0, 7) ; //!< Blue 1680 uint32_t Green : __CODEGEN_BITFIELD( 8, 15) ; //!< Green 1681 uint32_t Red : __CODEGEN_BITFIELD(16, 23) ; //!< Red 1682 uint32_t Alpha : __CODEGEN_BITFIELD(24, 31) ; //!< Alpha 1683 }; 1684 uint32_t Value; 1685 } DW0; 1686 1687 //! \name Local enumerations 1688 1689 //! \name Initializations 1690 1691 //! \brief Explicit member initialization function 1692 PALETTE_ENTRY_CMD(); 1693 1694 static const size_t dwSize = 1; 1695 static const size_t byteSize = 4; 1696 }; 1697 1698 //! 1699 //! \brief STATE_SIP 1700 //! \details 1701 //! The STATE_SIP command specifies the starting instruction location of the 1702 //! System Routine that is shared by all threads in execution. 1703 //! 1704 struct STATE_SIP_CMD 1705 { 1706 union 1707 { 1708 //!< DWORD 0 1709 struct 1710 { 1711 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1712 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1713 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1714 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1715 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1716 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1717 }; 1718 uint32_t Value; 1719 } DW0; 1720 union 1721 { 1722 //!< DWORD 1..2 1723 struct 1724 { 1725 uint64_t Reserved32 : __CODEGEN_BITFIELD( 0, 3) ; //!< Reserved 1726 uint64_t SystemInstructionPointer : __CODEGEN_BITFIELD( 4, 63) ; //!< System Instruction Pointer 1727 }; 1728 uint32_t Value[2]; 1729 } DW1_2; 1730 1731 //! \name Local enumerations 1732 1733 enum _3D_COMMAND_SUB_OPCODE 1734 { 1735 _3D_COMMAND_SUB_OPCODE_STATESIP = 2, //!< No additional details 1736 }; 1737 1738 enum _3D_COMMAND_OPCODE 1739 { 1740 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 1741 }; 1742 1743 enum COMMAND_SUBTYPE 1744 { 1745 COMMAND_SUBTYPE_GFXPIPECOMMON = 0, //!< No additional details 1746 }; 1747 1748 enum COMMAND_TYPE 1749 { 1750 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1751 }; 1752 1753 //! \name Initializations 1754 1755 //! \brief Explicit member initialization function 1756 STATE_SIP_CMD(); 1757 1758 static const size_t dwSize = 3; 1759 static const size_t byteSize = 12; 1760 }; 1761 1762 //! 1763 //! \brief GPGPU_CSR_BASE_ADDRESS 1764 //! \details 1765 //! The GPGPU_CSR_BASE_ADDRESS command sets the base pointers for EU and L3 1766 //! to Context Save and Restore EU State and SLM for GPGPU mid-thread 1767 //! preemption. 1768 //! 1769 //! Execution of this command causes a full pipeline flush, thus its use 1770 //! should be minimized for higher performance. State and instruction caches 1771 //! are flushed on completion of the flush. 1772 //! 1773 //! SW must always program PIPE_CONTROL with "CS Stall" and "Render Target 1774 //! Cache Flush Enable" set prior to programming GPGPU_CSR_BASE_ADDRESS 1775 //! command for GPGPU workloads i.e when pipeline select is GPGPU via 1776 //! PIPELINE_SELECT command. This is required to achieve better GPGPU 1777 //! preemption latencies for certain programming sequences. If programming 1778 //! PIPE_CONTROL has performance implications then preemption latencies can 1779 //! be trade off against performance by not implementing this programming 1780 //! note. 1781 //! 1782 struct GPGPU_CSR_BASE_ADDRESS_CMD 1783 { 1784 union 1785 { 1786 //!< DWORD 0 1787 struct 1788 { 1789 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1790 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1791 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1792 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1793 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1794 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1795 }; 1796 uint32_t Value; 1797 } DW0; 1798 union 1799 { 1800 //!< DWORD 1..2 1801 struct 1802 { 1803 uint64_t Reserved32 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1804 uint64_t GpgpuCsrBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< GPGPU CSR Base Address 1805 }; 1806 uint32_t Value[2]; 1807 } DW1_2; 1808 1809 //! \name Local enumerations 1810 1811 enum _3D_COMMAND_SUB_OPCODE 1812 { 1813 _3D_COMMAND_SUB_OPCODE_GPGPUCSRBASEADDRESS = 4, //!< No additional details 1814 }; 1815 1816 enum _3D_COMMAND_OPCODE 1817 { 1818 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 1819 }; 1820 1821 enum COMMAND_SUBTYPE 1822 { 1823 COMMAND_SUBTYPE_GFXPIPECOMMON = 0, //!< No additional details 1824 }; 1825 1826 enum COMMAND_TYPE 1827 { 1828 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1829 }; 1830 1831 //! \name Initializations 1832 1833 //! \brief Explicit member initialization function 1834 GPGPU_CSR_BASE_ADDRESS_CMD(); 1835 1836 static const size_t dwSize = 3; 1837 static const size_t byteSize = 12; 1838 }; 1839 1840 }; 1841 1842 #pragma pack() 1843 1844 #endif // __MHW_RENDER_HWCMD_G8_X_H__ 1845