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Searched defs:CACR (Results 1 – 22 of 22) sorted by relevance

/btstack/port/samv71-xplained-atwilc3000/ASF/thirdparty/CMSIS/Include/
H A Dcore_cm7.h458 …__IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register … member
/btstack/port/stm32-l451-miromico-sx1280/Drivers/CMSIS/Include/
H A Dcore_cm7.h503 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ member
H A Dcore_armv8mml.h545 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ member
H A Dcore_cm33.h545 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ member
/btstack/port/stm32-l073rz-nucleo-em9304/Drivers/CMSIS/Include/
H A Dcore_cm7.h548 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ member
/btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra/arm/CMSIS_5/CMSIS/Core/Include/
H A Dcore_cm7.h509 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ member
/btstack/port/stm32-l476rg-nucleo-sx1280/Drivers/CMSIS/Include/
H A Dcore_cm7.h503 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ member
/btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Include/
H A Dcore_cm7.h503 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ member
H A Dcore_cm33.h545 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ member
H A Dcore_armv8mml.h545 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ member
/btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Core/Include/
H A Dcore_cm7.h503 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ member
H A Dcore_armv8mml.h545 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ member
H A Dcore_cm33.h545 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ member
/btstack/port/stm32-wb55xx-nucleo-freertos/Drivers/CMSIS/Include/
H A Dcore_cm7.h503 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ member
/btstack/port/stm32-f4discovery-cc256x/Drivers/CMSIS/Include/
H A Dcore_cm7.h503 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ member
H A Dcore_cm33.h545 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ member
H A Dcore_armv8mml.h545 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ member
/btstack/port/renesas-tb-s1ja-cc256x/template/btstack_example/synergy/ssp/inc/bsp/cmsis/Include/
H A Dcore_armv8mml.h501 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ member
/btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Device/ST/STM32F4xx/Include/
H A Dstm32f429xx.h667 …__IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Ad… member
H A Dstm32f439xx.h668 …__IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Ad… member
H A Dstm32f469xx.h730 …__IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Ad… member
H A Dstm32f479xx.h731 …__IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Ad… member