1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _DRAMC_COMMON_MT8183_H_ 4 #define _DRAMC_COMMON_MT8183_H_ 5 6 enum { 7 DRAM_DFS_SHUFFLE_1 = 0, 8 DRAM_DFS_SHUFFLE_2, 9 DRAM_DFS_SHUFFLE_3, 10 DRAM_DFS_SHUFFLE_MAX 11 }; 12 13 enum { 14 CHANNEL_A = 0, 15 CHANNEL_B, 16 CHANNEL_MAX 17 }; 18 19 enum { 20 RANK_0 = 0, 21 RANK_1, 22 RANK_MAX 23 }; 24 25 enum dram_odt_type { 26 ODT_OFF = 0, 27 ODT_ON, 28 ODT_MAX 29 }; 30 31 enum { 32 CA_NUM_LP4 = 6, 33 DQ_DATA_WIDTH = 16, 34 DQS_BIT_NUMBER = 8, 35 DQS_NUMBER = (DQ_DATA_WIDTH / DQS_BIT_NUMBER) 36 }; 37 38 /* 39 * Internal CBT mode enum 40 * 1. Calibration flow uses vGet_Dram_CBT_Mode to 41 * differentiate between mixed vs non-mixed LP4 42 * 2. Declared as dram_cbt_mode[RANK_MAX] internally to 43 * store each rank's CBT mode type 44 */ 45 enum { 46 CBT_NORMAL_MODE = 0, 47 CBT_BYTE_MODE1 48 }; 49 50 enum { 51 CBT_R0_R1_NORMAL = 0, /* Normal mode */ 52 CBT_R0_R1_BYTE, /* Byte mode */ 53 CBT_R0_NORMAL_R1_BYTE, /* Mixed mode R0: Normal R1: Byte */ 54 CBT_R0_BYTE_R1_NORMAL /* Mixed mode R0: Byte R1: Normal */ 55 }; 56 57 enum { 58 FSP_0 = 0, 59 FSP_1, 60 FSP_MAX 61 }; 62 63 #endif /* _DRAMC_COMMON_MT8183_H_ */ 64