1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H 4 #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H 5 6 #include <acpi/acpi.h> 7 8 /* PCH types */ 9 #define PCH_TYPE_CPT 0x1c /* CougarPoint */ 10 #define PCH_TYPE_PPT 0x1e /* IvyBridge */ 11 12 /* PCH stepping values for LPC device */ 13 #define PCH_STEP_A0 0 14 #define PCH_STEP_A1 1 15 #define PCH_STEP_B0 2 16 #define PCH_STEP_B1 3 17 #define PCH_STEP_B2 4 18 #define PCH_STEP_B3 5 19 20 #define SMBUS_SLAVE_ADDR 0x24 21 /* TODO Make sure these don't get changed by stage2 */ 22 #define DEFAULT_GPIOBASE 0x0480 23 #define DEFAULT_PMBASE 0x0500 24 25 #include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ 26 27 #if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) 28 #define CROS_GPIO_DEVICE_NAME "CougarPoint" 29 #elif CONFIG(SOUTHBRIDGE_INTEL_C216) 30 #define CROS_GPIO_DEVICE_NAME "PantherPoint" 31 #endif 32 33 #ifndef __ACPI__ 34 35 int pch_silicon_revision(void); 36 int pch_silicon_type(void); 37 int pch_silicon_supported(int type, int rev); 38 bool pch_is_mobile(void); 39 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); 40 41 void enable_usb_bar(void); 42 43 void early_thermal_init(void); 44 void southbridge_configure_default_intmap(void); 45 void southbridge_rcba_config(void); 46 /* Optional mainboard hook to do additional configuration 47 on the RCBA config space. It is called after the raminit. */ 48 void mainboard_late_rcba_config(void); 49 /* Optional mainboard hook to do additional LPC configuration 50 or to override what is set up by default. */ 51 void mainboard_pch_lpc_setup(void); 52 void early_pch_init_native(void); 53 void early_pch_init(void); 54 void early_pch_init_native_dmi_pre(void); 55 void early_pch_init_native_dmi_post(void); 56 57 struct southbridge_usb_port 58 { 59 int enabled; 60 int current; 61 int oc_pin; 62 }; 63 64 void pch_enable(struct device *dev); 65 66 void early_usb_init(void); 67 68 /* PCI Configuration Space (D30:F0): PCI2PCI */ 69 #define PSTS 0x06 70 #define SMLT 0x1b 71 #define SECSTS 0x1e 72 #define INTR 0x3c 73 74 #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) 75 #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) 76 #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) 77 #define PCH_THERMAL_DEV PCI_DEV(0, 0x1f, 6) 78 #define PCH_IOAPIC_PCI_BUS 250 79 #define PCH_IOAPIC_PCI_SLOT 31 80 #define PCH_HPET_PCI_BUS 250 81 #define PCH_HPET_PCI_SLOT 15 82 83 /* PCI Configuration Space (D28:F0): PCI2PCI */ 84 #define PCH_PCIE_DEV_SLOT 28 85 #define PCH_PCIE_DEV(_func) PCI_DEV(0, PCH_PCIE_DEV_SLOT, _func) 86 87 /* PCI Configuration Space (D20:F0): xHCI */ 88 #define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) 89 90 #define XHCI_PWR_CNTL_STS 0x74 91 92 /* xHCI memory base registers */ 93 #define XHCI_PORTSC_x_USB3(port) (0x4c0 + (port) * 0x10) 94 95 /* PCI Configuration Space (D31:F0): LPC */ 96 #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) 97 #define SERIRQ_CNTL 0x64 98 99 #define GEN_PMCON_1 0xa0 100 #define GEN_PMCON_2 0xa2 101 #define GEN_PMCON_3 0xa4 102 #define GEN_PMCON_LOCK 0xa6 103 #define ETR3 0xac 104 #define ETR3_CWORWRE (1 << 18) 105 #define ETR3_CF9GR (1 << 20) 106 #define ETR3_CF9LOCK (1 << 31) 107 108 /* GEN_PMCON_3 bits */ 109 #define RTC_BATTERY_DEAD (1 << 2) 110 #define RTC_POWER_FAILED (1 << 1) 111 #define SLEEP_AFTER_POWER_FAIL (1 << 0) 112 113 #define PMBASE 0x40 114 #define ACPI_CNTL 0x44 115 #define ACPI_EN (1 << 7) 116 #define BIOS_CNTL 0xDC 117 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ 118 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ 119 120 #define GPIO_ROUT 0xb8 121 #define GPI_DISABLE 0x00 122 #define GPI_IS_SMI 0x01 123 #define GPI_IS_SCI 0x02 124 #define GPI_IS_NMI 0x03 125 126 #define PIRQA_ROUT 0x60 127 #define PIRQB_ROUT 0x61 128 #define PIRQC_ROUT 0x62 129 #define PIRQD_ROUT 0x63 130 #define PIRQE_ROUT 0x68 131 #define PIRQF_ROUT 0x69 132 #define PIRQG_ROUT 0x6A 133 #define PIRQH_ROUT 0x6B 134 135 #define LPC_IBDF 0x6C /* I/O APIC bus/dev/fn */ 136 #define LPC_HnBDF(n) (0x70 + n * 2) /* HPET n bus/dev/fn */ 137 138 #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ 139 #define LPC_EN 0x82 /* LPC IF Enables Register */ 140 #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ 141 #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ 142 #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ 143 #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ 144 #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ 145 #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ 146 #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ 147 #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ 148 #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ 149 #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ 150 #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ 151 #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ 152 #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ 153 #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ 154 #define LGMR 0x98 /* LPC Generic Memory Range */ 155 #define BIOS_DEC_EN1 0xd8 /* BIOS Decode Enable */ 156 157 /* PCI Configuration Space (D31:F2): SATA */ 158 #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) 159 #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) 160 #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ 161 #define IDE_DECODE_ENABLE (1 << 15) 162 #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ 163 164 #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ 165 #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ 166 #define SATA_SP 0xd0 /* Scratchpad */ 167 168 /* SATA IOBP Registers */ 169 #define SATA_IOBP_SP0G3IR 0xea000151 170 #define SATA_IOBP_SP1G3IR 0xea000051 171 172 /* PCI Configuration Space (D31:F3): SMBus */ 173 #define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3) 174 #define SMB_BASE 0x20 175 #define HOSTC 0x40 176 177 /* HOSTC bits */ 178 #define I2C_EN (1 << 2) 179 #define SMB_SMI_EN (1 << 1) 180 #define HST_EN (1 << 0) 181 182 /* Southbridge IO BARs */ 183 184 #define GPIOBASE 0x48 185 186 #define PMBASE 0x40 187 188 #define CIR0 0x0050 /* 32bit */ 189 #define TCLOCKDN (1u << 31) 190 191 #define RPC 0x0400 /* 32bit */ 192 #define RPFN 0x0404 /* 32bit */ 193 194 #define CIR2 0x900 /* 16bit */ 195 #define CIR3 0x1100 /* 16bit */ 196 #define UPDCR 0x1114 /* 32bit */ 197 198 /* Root Port configuratinon space hide */ 199 #define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) 200 /* Get the function number assigned to a Root Port */ 201 #define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) 202 /* Set the function number for a Root Port */ 203 #define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) 204 /* Root Port function number mask */ 205 #define RPFN_FNMASK(port) (7 << ((port) * 4)) 206 207 #define TRSR 0x1e00 /* 8bit */ 208 #define TRCR 0x1e10 /* 64bit */ 209 #define TWDR 0x1e18 /* 64bit */ 210 211 #define IOTR0 0x1e80 /* 64bit */ 212 #define IOTR1 0x1e88 /* 64bit */ 213 #define IOTR2 0x1e90 /* 64bit */ 214 #define IOTR3 0x1e98 /* 64bit */ 215 216 #define VCNEGPND 2 217 218 #define TCTL 0x3000 /* 8bit */ 219 220 #define NOINT 0 221 #define INTA 1 222 #define INTB 2 223 #define INTC 3 224 #define INTD 4 225 226 #define DIR_IDR 12 /* Interrupt D Pin Offset */ 227 #define DIR_ICR 8 /* Interrupt C Pin Offset */ 228 #define DIR_IBR 4 /* Interrupt B Pin Offset */ 229 #define DIR_IAR 0 /* Interrupt A Pin Offset */ 230 231 #define PIRQA 0 232 #define PIRQB 1 233 #define PIRQC 2 234 #define PIRQD 3 235 #define PIRQE 4 236 #define PIRQF 5 237 #define PIRQG 6 238 #define PIRQH 7 239 240 /* DMI control */ 241 #define V0CTL 0x2014 /* 32bit */ 242 #define V0STS 0x201a /* 16bit */ 243 #define V1CTL 0x2020 /* 32bit */ 244 #define V1STS 0x2026 /* 16bit */ 245 #define CIR31 0x2030 /* 32bit */ 246 #define CIR32 0x2040 /* 32bit */ 247 #define CIR1 0x2088 /* 32bit */ 248 #define REC 0x20ac /* 32bit */ 249 #define LCAP 0x21a4 /* 32bit */ 250 #define LCTL 0x21a8 /* 16bit */ 251 #define LSTS 0x21aa /* 16bit */ 252 #define DLCTL2 0x21b0 /* 16bit */ 253 #define DMIC 0x2234 /* 32bit */ 254 #define CIR30 0x2238 /* 32bit */ 255 #define CIR5 0x228c /* 32bit */ 256 #define DMC 0x2304 /* 32bit */ 257 #define CIR6 0x2314 /* 32bit */ 258 #define CIR9 0x2320 /* 32bit */ 259 #define DMC2 0x2324 /* 32bit - name guessed */ 260 261 /* IO Buffer Programming */ 262 #define IOBPIRI 0x2330 263 #define IOBPD 0x2334 264 #define IOBPS 0x2338 265 #define IOBPS_RW_BX ((1 << 9)|(1 << 10)) 266 #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) 267 #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) 268 269 #define D31IP 0x3100 /* 32bit */ 270 #define D31IP_TTIP 24 /* Thermal Throttle Pin */ 271 #define D31IP_SIP2 20 /* SATA Pin 2 */ 272 #define D31IP_SMIP 12 /* SMBUS Pin */ 273 #define D31IP_SIP 8 /* SATA Pin */ 274 #define D30IP 0x3104 /* 32bit */ 275 #define D30IP_PIP 0 /* PCI Bridge Pin */ 276 #define D29IP 0x3108 /* 32bit */ 277 #define D29IP_E1P 0 /* EHCI #1 Pin */ 278 #define D28IP 0x310c /* 32bit */ 279 #define D28IP_P8IP 28 /* PCI Express Port 8 */ 280 #define D28IP_P7IP 24 /* PCI Express Port 7 */ 281 #define D28IP_P6IP 20 /* PCI Express Port 6 */ 282 #define D28IP_P5IP 16 /* PCI Express Port 5 */ 283 #define D28IP_P4IP 12 /* PCI Express Port 4 */ 284 #define D28IP_P3IP 8 /* PCI Express Port 3 */ 285 #define D28IP_P2IP 4 /* PCI Express Port 2 */ 286 #define D28IP_P1IP 0 /* PCI Express Port 1 */ 287 #define D27IP 0x3110 /* 32bit */ 288 #define D27IP_ZIP 0 /* HD Audio Pin */ 289 #define D26IP 0x3114 /* 32bit */ 290 #define D26IP_E2P 0 /* EHCI #2 Pin */ 291 #define D25IP 0x3118 /* 32bit */ 292 #define D25IP_LIP 0 /* GbE LAN Pin */ 293 #define D22IP 0x3124 /* 32bit */ 294 #define D22IP_KTIP 12 /* KT Pin */ 295 #define D22IP_IDERIP 8 /* IDE-R Pin */ 296 #define D22IP_MEI2IP 4 /* MEI #2 Pin */ 297 #define D22IP_MEI1IP 0 /* MEI #1 Pin */ 298 #define D20IP 0x3128 /* 32bit */ 299 #define D20IP_XHCIIP 0 300 #define D31IR 0x3140 /* 16bit */ 301 #define D30IR 0x3142 /* 16bit */ 302 #define D29IR 0x3144 /* 16bit */ 303 #define D28IR 0x3146 /* 16bit */ 304 #define D27IR 0x3148 /* 16bit */ 305 #define D26IR 0x314c /* 16bit */ 306 #define D25IR 0x3150 /* 16bit */ 307 #define D22IR 0x315c /* 16bit */ 308 #define D20IR 0x3160 /* 16bit */ 309 #define OIC 0x31fe /* 16bit */ 310 #define SOFT_RESET_CTRL 0x38f4 311 #define SOFT_RESET_DATA 0x38f8 312 313 #define DIR_ROUTE(x,a,b,c,d) \ 314 RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ 315 ((b) << DIR_IBR) | ((a) << DIR_IAR)) 316 317 #define PRSTS 0x3310 /* 32bit */ 318 #define CIR7 0x3314 /* 32bit */ 319 #define PM_CFG 0x3318 /* 32bit */ 320 #define CIR8 0x3324 /* 32bit */ 321 #define CIR10 0x3340 /* 32bit */ 322 #define CIR11 0x3344 /* 32bit */ 323 #define CIR12 0x3360 /* 32bit */ 324 #define CIR14 0x3368 /* 32bit */ 325 #define CIR15 0x3378 /* 32bit */ 326 #define CIR13 0x337c /* 32bit */ 327 #define CIR16 0x3388 /* 32bit */ 328 #define CIR18 0x3390 /* 32bit */ 329 #define CIR17 0x33a0 /* 32bit */ 330 #define CIR23 0x33b0 /* 32bit */ 331 #define CIR19 0x33c0 /* 32bit */ 332 #define PMSYNC_CFG 0x33c8 /* 32bit */ 333 #define CIR20 0x33cc /* 32bit */ 334 #define CIR21 0x33d0 /* 32bit */ 335 #define CIR22 0x33d4 /* 32bit */ 336 337 #define RC 0x3400 /* 32bit */ 338 #define HPTC 0x3404 /* 32bit */ 339 #define GCS 0x3410 /* 32bit */ 340 #define BUC 0x3414 /* 32bit */ 341 #define PCH_DISABLE_GBE (1 << 5) 342 #define FD 0x3418 /* 32bit */ 343 #define DISPBDF 0x3424 /* 16bit */ 344 #define FD2 0x3428 /* 32bit */ 345 #define CG 0x341c /* 32bit */ 346 347 /* Function Disable 1 RCBA 0x3418 */ 348 #define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)) 349 #define PCH_DISABLE_P2P (1 << 1) 350 #define PCH_DISABLE_SATA1 (1 << 2) 351 #define PCH_DISABLE_SMBUS (1 << 3) 352 #define PCH_DISABLE_HD_AUDIO (1 << 4) 353 #define PCH_DISABLE_EHCI2 (1 << 13) 354 #define PCH_DISABLE_LPC (1 << 14) 355 #define PCH_DISABLE_EHCI1 (1 << 15) 356 #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) 357 #define PCH_DISABLE_THERMAL (1 << 24) 358 #define PCH_DISABLE_SATA2 (1 << 25) 359 #define PCH_DISABLE_XHCI (1 << 27) 360 361 /* Function Disable 2 RCBA 0x3428 */ 362 #define PCH_DISABLE_KT (1 << 4) 363 #define PCH_DISABLE_IDER (1 << 3) 364 #define PCH_DISABLE_MEI2 (1 << 2) 365 #define PCH_DISABLE_MEI1 (1 << 1) 366 #define PCH_ENABLE_DBDF (1 << 0) 367 368 /* USB Initialization Registers[13:0] */ 369 #define USBIR0 0x3500 /* 32bit */ 370 #define USBIR1 0x3504 /* 32bit */ 371 #define USBIR2 0x3508 /* 32bit */ 372 #define USBIR3 0x350c /* 32bit */ 373 #define USBIR4 0x3510 /* 32bit */ 374 #define USBIR5 0x3514 /* 32bit */ 375 #define USBIR6 0x3518 /* 32bit */ 376 #define USBIR7 0x351c /* 32bit */ 377 #define USBIR8 0x3520 /* 32bit */ 378 #define USBIR9 0x3524 /* 32bit */ 379 #define USBIR10 0x3528 /* 32bit */ 380 #define USBIR11 0x352c /* 32bit */ 381 #define USBIR12 0x3530 /* 32bit */ 382 #define USBIR13 0x3534 /* 32bit */ 383 384 /* Up to 5" onboard trace length */ 385 #define USBIR_TXRX_GAIN_MOBILE_LOW 0x20000153 386 387 /* Up to 6" onboard trace length */ 388 #define USBIR_TXRX_GAIN_DESKTOP_LOW 0x20000F53 389 390 /* Up to 14" onboard trace length, up to 8" on wires */ 391 #define USBIR_TXRX_GAIN_DEFAULT 0x20000f57 392 #define USBIR_TXRX_GAIN_MOBILE_HIGH USBIR_TXRX_GAIN_DEFAULT 393 394 /* Up to 10" onboard trace length, up to 15" on wires */ 395 #define USBIR_TXRX_GAIN_HIGH 0x2000055B 396 397 /* Desktop 6-series PCHs */ 398 /* In order: up to and not including 8"/13"/15" on wires */ 399 #define USBIR_TXRX_GAIN_DESKTOP6_LOW USBIR_TXRX_GAIN_DESKTOP_LOW 400 #define USBIR_TXRX_GAIN_DESKTOP6_MED USBIR_TXRX_GAIN_DEFAULT 401 #define USBIR_TXRX_GAIN_DESKTOP6_HIGH 0x20000f5b 402 403 /* Desktop 7-series PCHs */ 404 /* In order: up to and not including 8"/10"/15" on wires */ 405 #define USBIR_TXRX_GAIN_DESKTOP7_LOW USBIR_TXRX_GAIN_DEFAULT 406 #define USBIR_TXRX_GAIN_DESKTOP7_MED 0x20000553 407 #define USBIR_TXRX_GAIN_DESKTOP7_HIGH USBIR_TXRX_GAIN_HIGH 408 409 /* Miscellaneous Control Register */ 410 #define MISCCTL 0x3590 /* 32bit */ 411 /* USB Port Disable Override */ 412 #define USBPDO 0x359c /* 32bit */ 413 /* USB Overcurrent MAP Register */ 414 #define USBOCM1 0x35a0 /* 32bit */ 415 #define USBOCM2 0x35a4 /* 32bit */ 416 /* Rate Matching Hub Wake Control Register */ 417 #define RMHWKCTL 0x35b0 /* 32bit */ 418 419 #define CIR24 0x3a28 /* 32bit */ 420 #define CIR25 0x3a2c /* 32bit */ 421 #define CIR26 0x3a6c /* 32bit */ 422 #define CIR27 0x3a80 /* 32bit */ 423 #define CIR28 0x3a84 /* 32bit */ 424 #define CIR29 0x3a88 /* 32bit */ 425 426 /* XHCI USB 3.0 */ 427 #define XOCM 0xc0 /* 32bit */ 428 #define XUSB2PRM 0xd4 /* 32bit */ 429 #define USB3PRM 0xdc /* 32bit */ 430 431 /* ICH7 PMBASE */ 432 #define PM1_STS 0x00 433 #define WAK_STS (1 << 15) 434 #define PCIEXPWAK_STS (1 << 14) 435 #define PRBTNOR_STS (1 << 11) 436 #define RTC_STS (1 << 10) 437 #define PWRBTN_STS (1 << 8) 438 #define GBL_STS (1 << 5) 439 #define BM_STS (1 << 4) 440 #define TMROF_STS (1 << 0) 441 #define PM1_EN 0x02 442 #define PCIEXPWAK_DIS (1 << 14) 443 #define RTC_EN (1 << 10) 444 #define PWRBTN_EN (1 << 8) 445 #define GBL_EN (1 << 5) 446 #define TMROF_EN (1 << 0) 447 #define PM1_CNT 0x04 448 #define GBL_RLS (1 << 2) 449 #define BM_RLD (1 << 1) 450 #define SCI_EN (1 << 0) 451 #define PM1_TMR 0x08 452 #define PROC_CNT 0x10 453 #define LV2 0x14 454 #define LV3 0x15 455 #define LV4 0x16 456 #define GPE0_STS 0x20 457 #define PME_B0_STS (1 << 13) 458 #define PME_STS (1 << 11) 459 #define BATLOW_STS (1 << 10) 460 #define PCI_EXP_STS (1 << 9) 461 #define RI_STS (1 << 8) 462 #define SMB_WAK_STS (1 << 7) 463 #define TCOSCI_STS (1 << 6) 464 #define SWGPE_STS (1 << 2) 465 #define HOT_PLUG_STS (1 << 1) 466 #define GPE0_EN 0x28 467 #define PME_B0_EN (1 << 13) 468 #define PME_EN (1 << 11) 469 #define TCOSCI_EN (1 << 6) 470 #define SMI_EN 0x30 471 #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic 472 #define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic 473 #define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS 474 #define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) 475 #define MCSMI_EN (1 << 11) // Trap microcontroller range access 476 #define BIOS_RLS (1 << 7) // asserts SCI on bit set 477 #define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set 478 #define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# 479 #define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# 480 #define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic 481 #define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit 482 #define EOS (1 << 1) // End of SMI (deassert SMI#) 483 #define GBL_SMI_EN (1 << 0) // SMI# generation at all? 484 #define SMI_STS 0x34 485 #define ALT_GP_SMI_EN 0x38 486 #define ALT_GP_SMI_STS 0x3a 487 488 /* PM I/O Space */ 489 #define UPRWC 0x3c 490 #define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ 491 492 #define GPE_CNTL 0x42 493 #define DEVACT_STS 0x44 494 #define PM2_CNT 0x50 // mobile only 495 #define C3_RES 0x54 496 497 #if CONFIG(TCO_SPACE_NOT_YET_SPLIT) 498 #define TCO1_STS 0x64 499 #define TCO_TIMEOUT (1 << 3) 500 #define DMISCI_STS (1 << 9) 501 #define TCO2_STS 0x66 502 #define TCO2_STS_SECOND_TO (1 << 1) 503 #define TCO1_CNT 0x68 504 #define TCO_TMR_HLT (1 << 11) 505 #define TCO_LOCK (1 << 12) 506 #define TCO2_CNT 0x6a 507 #endif 508 509 #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ 510 #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ 511 #define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ 512 #define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ 513 #define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ 514 #define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ 515 #define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) 516 #define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ 517 #define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ 518 #define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ 519 #define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ 520 #define SPIBAR_FADDR 0x3808 /* SPI flash address */ 521 #define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */ 522 523 #endif /* __ACPI__ */ 524 #endif /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */ 525