1 /* 2 * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_H 8 #define ARCH_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * MIDR bit definitions 14 ******************************************************************************/ 15 #define MIDR_IMPL_MASK U(0xff) 16 #define MIDR_IMPL_SHIFT U(24) 17 #define MIDR_VAR_SHIFT U(20) 18 #define MIDR_VAR_BITS U(4) 19 #define MIDR_VAR_MASK U(0xf) 20 #define MIDR_REV_SHIFT U(0) 21 #define MIDR_REV_BITS U(4) 22 #define MIDR_REV_MASK U(0xf) 23 #define MIDR_PN_MASK U(0xfff) 24 #define MIDR_PN_SHIFT U(4) 25 26 /******************************************************************************* 27 * MPIDR macros 28 ******************************************************************************/ 29 #define MPIDR_MT_MASK (U(1) << 24) 30 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 31 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 32 #define MPIDR_AFFINITY_BITS U(8) 33 #define MPIDR_AFFLVL_MASK U(0xff) 34 #define MPIDR_AFFLVL_SHIFT U(3) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 39 #define MPIDR_AFFINITY_MASK U(0x00ffffff) 40 #define MPIDR_AFFLVL0 U(0) 41 #define MPIDR_AFFLVL1 U(1) 42 #define MPIDR_AFFLVL2 U(2) 43 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 44 45 #define MPIDR_AFFLVL0_VAL(mpidr) \ 46 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 47 #define MPIDR_AFFLVL1_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL2_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL3_VAL(mpidr) U(0) 52 53 #define MPIDR_AFF_ID(mpid, n) \ 54 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 55 56 #define MPID_MASK (MPIDR_MT_MASK |\ 57 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\ 58 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\ 59 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 60 61 /* 62 * An invalid MPID. This value can be used by functions that return an MPID to 63 * indicate an error. 64 */ 65 #define INVALID_MPID U(0xFFFFFFFF) 66 67 /* 68 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 69 * add one while using this macro to define array sizes. 70 */ 71 #define MPIDR_MAX_AFFLVL U(2) 72 73 /* Data Cache set/way op type defines */ 74 #define DC_OP_ISW U(0x0) 75 #define DC_OP_CISW U(0x1) 76 #if ERRATA_A53_827319 77 #define DC_OP_CSW DC_OP_CISW 78 #else 79 #define DC_OP_CSW U(0x2) 80 #endif 81 82 /******************************************************************************* 83 * Generic timer memory mapped registers & offsets 84 ******************************************************************************/ 85 #define CNTCR_OFF U(0x000) 86 /* Counter Count Value Lower register */ 87 #define CNTCVL_OFF U(0x008) 88 /* Counter Count Value Upper register */ 89 #define CNTCVU_OFF U(0x00C) 90 #define CNTFID_OFF U(0x020) 91 92 #define CNTCR_EN (U(1) << 0) 93 #define CNTCR_HDBG (U(1) << 1) 94 #define CNTCR_FCREQ(x) ((x) << 8) 95 96 /******************************************************************************* 97 * System register bit definitions 98 ******************************************************************************/ 99 /* CLIDR definitions */ 100 #define LOUIS_SHIFT U(21) 101 #define LOC_SHIFT U(24) 102 #define CLIDR_FIELD_WIDTH U(3) 103 104 /* CSSELR definitions */ 105 #define LEVEL_SHIFT U(1) 106 107 /* ID_DFR0 definitions */ 108 #define ID_DFR0_PERFMON_SHIFT U(24) 109 #define ID_DFR0_PERFMON_MASK U(0xf) 110 #define ID_DFR0_PERFMON_PMUV3 U(3) 111 #define ID_DFR0_PERFMON_PMUV3P5 U(6) 112 #define ID_DFR0_COPTRC_SHIFT U(12) 113 #define ID_DFR0_COPTRC_MASK U(0xf) 114 #define COPTRC_IMPLEMENTED U(1) 115 #define ID_DFR0_COPTRC_LENGTH U(4) 116 #define ID_DFR0_TRACEFILT_SHIFT U(28) 117 #define ID_DFR0_TRACEFILT_MASK U(0xf) 118 #define TRACEFILT_IMPLEMENTED U(1) 119 #define ID_DFR0_TRACEFILT_LENGTH U(4) 120 121 /* ID_DFR1_EL1 definitions */ 122 #define ID_DFR1_MTPMU_SHIFT U(0) 123 #define ID_DFR1_MTPMU_MASK U(0xf) 124 #define MTPMU_IMPLEMENTED U(1) 125 #define MTPMU_NOT_IMPLEMENTED U(15) 126 127 /* ID_MMFR3 definitions */ 128 #define ID_MMFR3_PAN_SHIFT U(16) 129 #define ID_MMFR3_PAN_MASK U(0xf) 130 131 /* ID_MMFR4 definitions */ 132 #define ID_MMFR4_CNP_SHIFT U(12) 133 #define ID_MMFR4_CNP_LENGTH U(4) 134 #define ID_MMFR4_CNP_MASK U(0xf) 135 136 #define ID_MMFR4_CCIDX_SHIFT U(24) 137 #define ID_MMFR4_CCIDX_LENGTH U(4) 138 #define ID_MMFR4_CCIDX_MASK U(0xf) 139 140 /* ID_PFR0 definitions */ 141 #define ID_PFR0_AMU_SHIFT U(20) 142 #define ID_PFR0_AMU_LENGTH U(4) 143 #define ID_PFR0_AMU_MASK U(0xf) 144 #define ID_PFR0_AMU_V1 U(0x1) 145 #define ID_PFR0_AMU_V1P1 U(0x2) 146 147 #define ID_PFR0_DIT_SHIFT U(24) 148 #define ID_PFR0_DIT_LENGTH U(4) 149 #define ID_PFR0_DIT_MASK U(0xf) 150 #define DIT_IMPLEMENTED (U(1) << ID_PFR0_DIT_SHIFT) 151 152 /* ID_PFR1 definitions */ 153 #define ID_PFR1_VIRTEXT_SHIFT U(12) 154 #define ID_PFR1_VIRTEXT_MASK U(0xf) 155 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 156 & ID_PFR1_VIRTEXT_MASK) 157 #define ID_PFR1_GENTIMER_SHIFT U(16) 158 #define ID_PFR1_GENTIMER_MASK U(0xf) 159 #define ID_PFR1_GIC_SHIFT U(28) 160 #define ID_PFR1_GIC_MASK U(0xf) 161 #define ID_PFR1_SEC_SHIFT U(4) 162 #define ID_PFR1_SEC_MASK U(0xf) 163 #define ID_PFR1_ELx_ENABLED U(1) 164 165 /* ID_PFR2 definitions */ 166 #define ID_PFR2_SSBS_SHIFT U(4) 167 #define ID_PFR2_SSBS_MASK U(0xf) 168 #define SSBS_NOT_IMPLEMENTED U(0) 169 170 /* SCTLR definitions */ 171 #define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \ 172 (U(1) << 3)) 173 #if ARM_ARCH_MAJOR == 7 174 #define SCTLR_RES1 SCTLR_RES1_DEF 175 #else 176 #define SCTLR_RES1 (SCTLR_RES1_DEF | (U(1) << 11)) 177 #endif 178 #define SCTLR_M_BIT (U(1) << 0) 179 #define SCTLR_A_BIT (U(1) << 1) 180 #define SCTLR_C_BIT (U(1) << 2) 181 #define SCTLR_CP15BEN_BIT (U(1) << 5) 182 #define SCTLR_ITD_BIT (U(1) << 7) 183 #define SCTLR_Z_BIT (U(1) << 11) 184 #define SCTLR_I_BIT (U(1) << 12) 185 #define SCTLR_V_BIT (U(1) << 13) 186 #define SCTLR_RR_BIT (U(1) << 14) 187 #define SCTLR_NTWI_BIT (U(1) << 16) 188 #define SCTLR_NTWE_BIT (U(1) << 18) 189 #define SCTLR_WXN_BIT (U(1) << 19) 190 #define SCTLR_UWXN_BIT (U(1) << 20) 191 #define SCTLR_EE_BIT (U(1) << 25) 192 #define SCTLR_TRE_BIT (U(1) << 28) 193 #define SCTLR_AFE_BIT (U(1) << 29) 194 #define SCTLR_TE_BIT (U(1) << 30) 195 #define SCTLR_DSSBS_BIT (U(1) << 31) 196 #define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \ 197 SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT) 198 199 /* SDCR definitions */ 200 #define SDCR_SPD(x) ((x) << 14) 201 #define SDCR_SPD_LEGACY U(0x0) 202 #define SDCR_SPD_DISABLE U(0x2) 203 #define SDCR_SPD_ENABLE U(0x3) 204 #define SDCR_SPME_BIT (U(1) << 17) 205 #define SDCR_TTRF_BIT (U(1) << 19) 206 #define SDCR_SCCD_BIT (U(1) << 23) 207 #define SDCR_MTPME_BIT (U(1) << 28) 208 #define SDCR_RESET_VAL U(0x0) 209 210 /* HSCTLR definitions */ 211 #define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 212 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 213 (U(1) << 11) | (U(1) << 4) | (U(1) << 3)) 214 215 #define HSCTLR_M_BIT (U(1) << 0) 216 #define HSCTLR_A_BIT (U(1) << 1) 217 #define HSCTLR_C_BIT (U(1) << 2) 218 #define HSCTLR_CP15BEN_BIT (U(1) << 5) 219 #define HSCTLR_ITD_BIT (U(1) << 7) 220 #define HSCTLR_SED_BIT (U(1) << 8) 221 #define HSCTLR_I_BIT (U(1) << 12) 222 #define HSCTLR_WXN_BIT (U(1) << 19) 223 #define HSCTLR_EE_BIT (U(1) << 25) 224 #define HSCTLR_TE_BIT (U(1) << 30) 225 226 /* CPACR definitions */ 227 #define CPACR_FPEN(x) ((x) << 20) 228 #define CPACR_FP_TRAP_PL0 UL(0x1) 229 #define CPACR_FP_TRAP_ALL UL(0x2) 230 #define CPACR_FP_TRAP_NONE UL(0x3) 231 232 /* SCR definitions */ 233 #define SCR_TWE_BIT (UL(1) << 13) 234 #define SCR_TWI_BIT (UL(1) << 12) 235 #define SCR_SIF_BIT (UL(1) << 9) 236 #define SCR_HCE_BIT (UL(1) << 8) 237 #define SCR_SCD_BIT (UL(1) << 7) 238 #define SCR_NET_BIT (UL(1) << 6) 239 #define SCR_AW_BIT (UL(1) << 5) 240 #define SCR_FW_BIT (UL(1) << 4) 241 #define SCR_EA_BIT (UL(1) << 3) 242 #define SCR_FIQ_BIT (UL(1) << 2) 243 #define SCR_IRQ_BIT (UL(1) << 1) 244 #define SCR_NS_BIT (UL(1) << 0) 245 #define SCR_VALID_BIT_MASK U(0x33ff) 246 #define SCR_RESET_VAL U(0x0) 247 248 #define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT) 249 250 /* HCR definitions */ 251 #define HCR_TGE_BIT (U(1) << 27) 252 #define HCR_AMO_BIT (U(1) << 5) 253 #define HCR_IMO_BIT (U(1) << 4) 254 #define HCR_FMO_BIT (U(1) << 3) 255 #define HCR_RESET_VAL U(0x0) 256 257 /* CNTHCTL definitions */ 258 #define CNTHCTL_RESET_VAL U(0x0) 259 #define PL1PCEN_BIT (U(1) << 1) 260 #define PL1PCTEN_BIT (U(1) << 0) 261 262 /* CNTKCTL definitions */ 263 #define PL0PTEN_BIT (U(1) << 9) 264 #define PL0VTEN_BIT (U(1) << 8) 265 #define PL0PCTEN_BIT (U(1) << 0) 266 #define PL0VCTEN_BIT (U(1) << 1) 267 #define EVNTEN_BIT (U(1) << 2) 268 #define EVNTDIR_BIT (U(1) << 3) 269 #define EVNTI_SHIFT U(4) 270 #define EVNTI_MASK U(0xf) 271 272 /* HCPTR definitions */ 273 #define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff)) 274 #define TCPAC_BIT (U(1) << 31) 275 #define TAM_SHIFT U(30) 276 #define TAM_BIT (U(1) << TAM_SHIFT) 277 #define TTA_BIT (U(1) << 20) 278 #define TCP11_BIT (U(1) << 11) 279 #define TCP10_BIT (U(1) << 10) 280 #define HCPTR_RESET_VAL HCPTR_RES1 281 282 /* VTTBR definitions */ 283 #define VTTBR_RESET_VAL ULL(0x0) 284 #define VTTBR_VMID_MASK ULL(0xff) 285 #define VTTBR_VMID_SHIFT U(48) 286 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 287 #define VTTBR_BADDR_SHIFT U(0) 288 289 /* HDCR definitions */ 290 #define HDCR_MTPME_BIT (U(1) << 28) 291 #define HDCR_HLP_BIT (U(1) << 26) 292 #define HDCR_HPME_BIT (U(1) << 7) 293 #define HDCR_RESET_VAL U(0x0) 294 295 /* HSTR definitions */ 296 #define HSTR_RESET_VAL U(0x0) 297 298 /* CNTHP_CTL definitions */ 299 #define CNTHP_CTL_RESET_VAL U(0x0) 300 301 /* NSACR definitions */ 302 #define NSASEDIS_BIT (U(1) << 15) 303 #define NSTRCDIS_BIT (U(1) << 20) 304 #define NSACR_CP11_BIT (U(1) << 11) 305 #define NSACR_CP10_BIT (U(1) << 10) 306 #define NSACR_IMP_DEF_MASK (U(0x7) << 16) 307 #define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT) 308 #define NSACR_RESET_VAL U(0x0) 309 310 /* CPACR definitions */ 311 #define ASEDIS_BIT (U(1) << 31) 312 #define TRCDIS_BIT (U(1) << 28) 313 #define CPACR_CP11_SHIFT U(22) 314 #define CPACR_CP10_SHIFT U(20) 315 #define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\ 316 (U(0x3) << CPACR_CP10_SHIFT)) 317 #define CPACR_RESET_VAL U(0x0) 318 319 /* FPEXC definitions */ 320 #define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8)) 321 #define FPEXC_EN_BIT (U(1) << 30) 322 #define FPEXC_RESET_VAL FPEXC_RES1 323 324 /* SPSR/CPSR definitions */ 325 #define SPSR_FIQ_BIT (U(1) << 0) 326 #define SPSR_IRQ_BIT (U(1) << 1) 327 #define SPSR_ABT_BIT (U(1) << 2) 328 #define SPSR_AIF_SHIFT U(6) 329 #define SPSR_AIF_MASK U(0x7) 330 331 #define SPSR_E_SHIFT U(9) 332 #define SPSR_E_MASK U(0x1) 333 #define SPSR_E_LITTLE U(0) 334 #define SPSR_E_BIG U(1) 335 336 #define SPSR_T_SHIFT U(5) 337 #define SPSR_T_MASK U(0x1) 338 #define SPSR_T_ARM U(0) 339 #define SPSR_T_THUMB U(1) 340 341 #define SPSR_MODE_SHIFT U(0) 342 #define SPSR_MODE_MASK U(0x7) 343 344 #define SPSR_SSBS_BIT BIT_32(23) 345 346 #define DISABLE_ALL_EXCEPTIONS \ 347 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT) 348 349 #define CPSR_DIT_BIT (U(1) << 21) 350 /* 351 * TTBCR definitions 352 */ 353 #define TTBCR_EAE_BIT (U(1) << 31) 354 355 #define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28) 356 #define TTBCR_SH1_OUTER_SHAREABLE (U(0x2) << 28) 357 #define TTBCR_SH1_INNER_SHAREABLE (U(0x3) << 28) 358 359 #define TTBCR_RGN1_OUTER_NC (U(0x0) << 26) 360 #define TTBCR_RGN1_OUTER_WBA (U(0x1) << 26) 361 #define TTBCR_RGN1_OUTER_WT (U(0x2) << 26) 362 #define TTBCR_RGN1_OUTER_WBNA (U(0x3) << 26) 363 364 #define TTBCR_RGN1_INNER_NC (U(0x0) << 24) 365 #define TTBCR_RGN1_INNER_WBA (U(0x1) << 24) 366 #define TTBCR_RGN1_INNER_WT (U(0x2) << 24) 367 #define TTBCR_RGN1_INNER_WBNA (U(0x3) << 24) 368 369 #define TTBCR_EPD1_BIT (U(1) << 23) 370 #define TTBCR_A1_BIT (U(1) << 22) 371 372 #define TTBCR_T1SZ_SHIFT U(16) 373 #define TTBCR_T1SZ_MASK U(0x7) 374 #define TTBCR_TxSZ_MIN U(0) 375 #define TTBCR_TxSZ_MAX U(7) 376 377 #define TTBCR_SH0_NON_SHAREABLE (U(0x0) << 12) 378 #define TTBCR_SH0_OUTER_SHAREABLE (U(0x2) << 12) 379 #define TTBCR_SH0_INNER_SHAREABLE (U(0x3) << 12) 380 381 #define TTBCR_RGN0_OUTER_NC (U(0x0) << 10) 382 #define TTBCR_RGN0_OUTER_WBA (U(0x1) << 10) 383 #define TTBCR_RGN0_OUTER_WT (U(0x2) << 10) 384 #define TTBCR_RGN0_OUTER_WBNA (U(0x3) << 10) 385 386 #define TTBCR_RGN0_INNER_NC (U(0x0) << 8) 387 #define TTBCR_RGN0_INNER_WBA (U(0x1) << 8) 388 #define TTBCR_RGN0_INNER_WT (U(0x2) << 8) 389 #define TTBCR_RGN0_INNER_WBNA (U(0x3) << 8) 390 391 #define TTBCR_EPD0_BIT (U(1) << 7) 392 #define TTBCR_T0SZ_SHIFT U(0) 393 #define TTBCR_T0SZ_MASK U(0x7) 394 395 /* 396 * HTCR definitions 397 */ 398 #define HTCR_RES1 ((U(1) << 31) | (U(1) << 23)) 399 400 #define HTCR_SH0_NON_SHAREABLE (U(0x0) << 12) 401 #define HTCR_SH0_OUTER_SHAREABLE (U(0x2) << 12) 402 #define HTCR_SH0_INNER_SHAREABLE (U(0x3) << 12) 403 404 #define HTCR_RGN0_OUTER_NC (U(0x0) << 10) 405 #define HTCR_RGN0_OUTER_WBA (U(0x1) << 10) 406 #define HTCR_RGN0_OUTER_WT (U(0x2) << 10) 407 #define HTCR_RGN0_OUTER_WBNA (U(0x3) << 10) 408 409 #define HTCR_RGN0_INNER_NC (U(0x0) << 8) 410 #define HTCR_RGN0_INNER_WBA (U(0x1) << 8) 411 #define HTCR_RGN0_INNER_WT (U(0x2) << 8) 412 #define HTCR_RGN0_INNER_WBNA (U(0x3) << 8) 413 414 #define HTCR_T0SZ_SHIFT U(0) 415 #define HTCR_T0SZ_MASK U(0x7) 416 417 #define MODE_RW_SHIFT U(0x4) 418 #define MODE_RW_MASK U(0x1) 419 #define MODE_RW_32 U(0x1) 420 421 #define MODE32_SHIFT U(0) 422 #define MODE32_MASK U(0x1f) 423 #define MODE32_usr U(0x10) 424 #define MODE32_fiq U(0x11) 425 #define MODE32_irq U(0x12) 426 #define MODE32_svc U(0x13) 427 #define MODE32_mon U(0x16) 428 #define MODE32_abt U(0x17) 429 #define MODE32_hyp U(0x1a) 430 #define MODE32_und U(0x1b) 431 #define MODE32_sys U(0x1f) 432 433 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 434 435 #define SPSR_MODE32(mode, isa, endian, aif) \ 436 ( \ 437 ( \ 438 (MODE_RW_32 << MODE_RW_SHIFT) | \ 439 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 440 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 441 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 442 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) \ 443 ) & \ 444 (~(SPSR_SSBS_BIT)) \ 445 ) 446 447 /* 448 * TTBR definitions 449 */ 450 #define TTBR_CNP_BIT ULL(0x1) 451 452 /* 453 * CTR definitions 454 */ 455 #define CTR_CWG_SHIFT U(24) 456 #define CTR_CWG_MASK U(0xf) 457 #define CTR_ERG_SHIFT U(20) 458 #define CTR_ERG_MASK U(0xf) 459 #define CTR_DMINLINE_SHIFT U(16) 460 #define CTR_DMINLINE_WIDTH U(4) 461 #define CTR_DMINLINE_MASK ((U(1) << 4) - U(1)) 462 #define CTR_L1IP_SHIFT U(14) 463 #define CTR_L1IP_MASK U(0x3) 464 #define CTR_IMINLINE_SHIFT U(0) 465 #define CTR_IMINLINE_MASK U(0xf) 466 467 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 468 469 /* PMCR definitions */ 470 #define PMCR_N_SHIFT U(11) 471 #define PMCR_N_MASK U(0x1f) 472 #define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT) 473 #define PMCR_LP_BIT (U(1) << 7) 474 #define PMCR_LC_BIT (U(1) << 6) 475 #define PMCR_DP_BIT (U(1) << 5) 476 #define PMCR_X_BIT (U(1) << 4) 477 #define PMCR_C_BIT (U(1) << 2) 478 #define PMCR_P_BIT (U(1) << 1) 479 #define PMCR_E_BIT (U(1) << 0) 480 #define PMCR_RESET_VAL U(0x0) 481 482 /******************************************************************************* 483 * Definitions of register offsets, fields and macros for CPU system 484 * instructions. 485 ******************************************************************************/ 486 487 #define TLBI_ADDR_SHIFT U(0) 488 #define TLBI_ADDR_MASK U(0xFFFFF000) 489 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 490 491 /******************************************************************************* 492 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 493 * system level implementation of the Generic Timer. 494 ******************************************************************************/ 495 #define CNTCTLBASE_CNTFRQ U(0x0) 496 #define CNTNSAR U(0x4) 497 #define CNTNSAR_NS_SHIFT(x) (x) 498 499 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 500 #define CNTACR_RPCT_SHIFT U(0x0) 501 #define CNTACR_RVCT_SHIFT U(0x1) 502 #define CNTACR_RFRQ_SHIFT U(0x2) 503 #define CNTACR_RVOFF_SHIFT U(0x3) 504 #define CNTACR_RWVT_SHIFT U(0x4) 505 #define CNTACR_RWPT_SHIFT U(0x5) 506 507 /******************************************************************************* 508 * Definitions of register offsets and fields in the CNTBaseN Frame of the 509 * system level implementation of the Generic Timer. 510 ******************************************************************************/ 511 /* Physical Count register. */ 512 #define CNTPCT_LO U(0x0) 513 /* Counter Frequency register. */ 514 #define CNTBASEN_CNTFRQ U(0x10) 515 /* Physical Timer CompareValue register. */ 516 #define CNTP_CVAL_LO U(0x20) 517 /* Physical Timer Control register. */ 518 #define CNTP_CTL U(0x2c) 519 520 /* Physical timer control register bit fields shifts and masks */ 521 #define CNTP_CTL_ENABLE_SHIFT 0 522 #define CNTP_CTL_IMASK_SHIFT 1 523 #define CNTP_CTL_ISTATUS_SHIFT 2 524 525 #define CNTP_CTL_ENABLE_MASK U(1) 526 #define CNTP_CTL_IMASK_MASK U(1) 527 #define CNTP_CTL_ISTATUS_MASK U(1) 528 529 /* MAIR macros */ 530 #define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3))) 531 #define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << U(3))) 532 533 /* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */ 534 #define SCR p15, 0, c1, c1, 0 535 #define SCTLR p15, 0, c1, c0, 0 536 #define ACTLR p15, 0, c1, c0, 1 537 #define SDCR p15, 0, c1, c3, 1 538 #define MPIDR p15, 0, c0, c0, 5 539 #define MIDR p15, 0, c0, c0, 0 540 #define HVBAR p15, 4, c12, c0, 0 541 #define VBAR p15, 0, c12, c0, 0 542 #define MVBAR p15, 0, c12, c0, 1 543 #define NSACR p15, 0, c1, c1, 2 544 #define CPACR p15, 0, c1, c0, 2 545 #define DCCIMVAC p15, 0, c7, c14, 1 546 #define DCCMVAC p15, 0, c7, c10, 1 547 #define DCIMVAC p15, 0, c7, c6, 1 548 #define DCCISW p15, 0, c7, c14, 2 549 #define DCCSW p15, 0, c7, c10, 2 550 #define DCISW p15, 0, c7, c6, 2 551 #define CTR p15, 0, c0, c0, 1 552 #define CNTFRQ p15, 0, c14, c0, 0 553 #define ID_MMFR3 p15, 0, c0, c1, 7 554 #define ID_MMFR4 p15, 0, c0, c2, 6 555 #define ID_DFR0 p15, 0, c0, c1, 2 556 #define ID_DFR1 p15, 0, c0, c3, 5 557 #define ID_PFR0 p15, 0, c0, c1, 0 558 #define ID_PFR1 p15, 0, c0, c1, 1 559 #define ID_PFR2 p15, 0, c0, c3, 4 560 #define MAIR0 p15, 0, c10, c2, 0 561 #define MAIR1 p15, 0, c10, c2, 1 562 #define TTBCR p15, 0, c2, c0, 2 563 #define TTBR0 p15, 0, c2, c0, 0 564 #define TTBR1 p15, 0, c2, c0, 1 565 #define TLBIALL p15, 0, c8, c7, 0 566 #define TLBIALLH p15, 4, c8, c7, 0 567 #define TLBIALLIS p15, 0, c8, c3, 0 568 #define TLBIMVA p15, 0, c8, c7, 1 569 #define TLBIMVAA p15, 0, c8, c7, 3 570 #define TLBIMVAAIS p15, 0, c8, c3, 3 571 #define TLBIMVAHIS p15, 4, c8, c3, 1 572 #define BPIALLIS p15, 0, c7, c1, 6 573 #define BPIALL p15, 0, c7, c5, 6 574 #define ICIALLU p15, 0, c7, c5, 0 575 #define HSCTLR p15, 4, c1, c0, 0 576 #define HCR p15, 4, c1, c1, 0 577 #define HCPTR p15, 4, c1, c1, 2 578 #define HSTR p15, 4, c1, c1, 3 579 #define CNTHCTL p15, 4, c14, c1, 0 580 #define CNTKCTL p15, 0, c14, c1, 0 581 #define VPIDR p15, 4, c0, c0, 0 582 #define VMPIDR p15, 4, c0, c0, 5 583 #define ISR p15, 0, c12, c1, 0 584 #define CLIDR p15, 1, c0, c0, 1 585 #define CSSELR p15, 2, c0, c0, 0 586 #define CCSIDR p15, 1, c0, c0, 0 587 #define CCSIDR2 p15, 1, c0, c0, 2 588 #define HTCR p15, 4, c2, c0, 2 589 #define HMAIR0 p15, 4, c10, c2, 0 590 #define ATS1CPR p15, 0, c7, c8, 0 591 #define ATS1HR p15, 4, c7, c8, 0 592 #define DBGOSDLR p14, 0, c1, c3, 4 593 594 /* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ 595 #define HDCR p15, 4, c1, c1, 1 596 #define PMCR p15, 0, c9, c12, 0 597 #define CNTHP_TVAL p15, 4, c14, c2, 0 598 #define CNTHP_CTL p15, 4, c14, c2, 1 599 600 /* AArch32 coproc registers for 32bit MMU descriptor support */ 601 #define PRRR p15, 0, c10, c2, 0 602 #define NMRR p15, 0, c10, c2, 1 603 #define DACR p15, 0, c3, c0, 0 604 605 /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ 606 #define ICC_IAR1 p15, 0, c12, c12, 0 607 #define ICC_IAR0 p15, 0, c12, c8, 0 608 #define ICC_EOIR1 p15, 0, c12, c12, 1 609 #define ICC_EOIR0 p15, 0, c12, c8, 1 610 #define ICC_HPPIR1 p15, 0, c12, c12, 2 611 #define ICC_HPPIR0 p15, 0, c12, c8, 2 612 #define ICC_BPR1 p15, 0, c12, c12, 3 613 #define ICC_BPR0 p15, 0, c12, c8, 3 614 #define ICC_DIR p15, 0, c12, c11, 1 615 #define ICC_PMR p15, 0, c4, c6, 0 616 #define ICC_RPR p15, 0, c12, c11, 3 617 #define ICC_CTLR p15, 0, c12, c12, 4 618 #define ICC_MCTLR p15, 6, c12, c12, 4 619 #define ICC_SRE p15, 0, c12, c12, 5 620 #define ICC_HSRE p15, 4, c12, c9, 5 621 #define ICC_MSRE p15, 6, c12, c12, 5 622 #define ICC_IGRPEN0 p15, 0, c12, c12, 6 623 #define ICC_IGRPEN1 p15, 0, c12, c12, 7 624 #define ICC_MGRPEN1 p15, 6, c12, c12, 7 625 626 /* 64 bit system register defines The format is: coproc, opt1, CRm */ 627 #define TTBR0_64 p15, 0, c2 628 #define TTBR1_64 p15, 1, c2 629 #define CNTVOFF_64 p15, 4, c14 630 #define VTTBR_64 p15, 6, c2 631 #define CNTPCT_64 p15, 0, c14 632 #define HTTBR_64 p15, 4, c2 633 #define CNTHP_CVAL_64 p15, 6, c14 634 #define PAR_64 p15, 0, c7 635 636 /* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */ 637 #define ICC_SGI1R_EL1_64 p15, 0, c12 638 #define ICC_ASGI1R_EL1_64 p15, 1, c12 639 #define ICC_SGI0R_EL1_64 p15, 2, c12 640 641 /* Fault registers. The format is: coproc, opt1, CRn, CRm, opt2 */ 642 #define DFSR p15, 0, c5, c0, 0 643 #define IFSR p15, 0, c5, c0, 1 644 #define DFAR p15, 0, c6, c0, 0 645 #define IFAR p15, 0, c6, c0, 2 646 647 /******************************************************************************* 648 * Definitions of MAIR encodings for device and normal memory 649 ******************************************************************************/ 650 /* 651 * MAIR encodings for device memory attributes. 652 */ 653 #define MAIR_DEV_nGnRnE U(0x0) 654 #define MAIR_DEV_nGnRE U(0x4) 655 #define MAIR_DEV_nGRE U(0x8) 656 #define MAIR_DEV_GRE U(0xc) 657 658 /* 659 * MAIR encodings for normal memory attributes. 660 * 661 * Cache Policy 662 * WT: Write Through 663 * WB: Write Back 664 * NC: Non-Cacheable 665 * 666 * Transient Hint 667 * NTR: Non-Transient 668 * TR: Transient 669 * 670 * Allocation Policy 671 * RA: Read Allocate 672 * WA: Write Allocate 673 * RWA: Read and Write Allocate 674 * NA: No Allocation 675 */ 676 #define MAIR_NORM_WT_TR_WA U(0x1) 677 #define MAIR_NORM_WT_TR_RA U(0x2) 678 #define MAIR_NORM_WT_TR_RWA U(0x3) 679 #define MAIR_NORM_NC U(0x4) 680 #define MAIR_NORM_WB_TR_WA U(0x5) 681 #define MAIR_NORM_WB_TR_RA U(0x6) 682 #define MAIR_NORM_WB_TR_RWA U(0x7) 683 #define MAIR_NORM_WT_NTR_NA U(0x8) 684 #define MAIR_NORM_WT_NTR_WA U(0x9) 685 #define MAIR_NORM_WT_NTR_RA U(0xa) 686 #define MAIR_NORM_WT_NTR_RWA U(0xb) 687 #define MAIR_NORM_WB_NTR_NA U(0xc) 688 #define MAIR_NORM_WB_NTR_WA U(0xd) 689 #define MAIR_NORM_WB_NTR_RA U(0xe) 690 #define MAIR_NORM_WB_NTR_RWA U(0xf) 691 692 #define MAIR_NORM_OUTER_SHIFT U(4) 693 694 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 695 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 696 697 /* PAR fields */ 698 #define PAR_F_SHIFT U(0) 699 #define PAR_F_MASK ULL(0x1) 700 #define PAR_ADDR_SHIFT U(12) 701 #define PAR_ADDR_MASK (BIT_64(40) - ULL(1)) /* 40-bits-wide page address */ 702 703 /******************************************************************************* 704 * Definitions for system register interface to AMU for FEAT_AMUv1 705 ******************************************************************************/ 706 #define AMCR p15, 0, c13, c2, 0 707 #define AMCFGR p15, 0, c13, c2, 1 708 #define AMCGCR p15, 0, c13, c2, 2 709 #define AMUSERENR p15, 0, c13, c2, 3 710 #define AMCNTENCLR0 p15, 0, c13, c2, 4 711 #define AMCNTENSET0 p15, 0, c13, c2, 5 712 #define AMCNTENCLR1 p15, 0, c13, c3, 0 713 #define AMCNTENSET1 p15, 0, c13, c3, 1 714 715 /* Activity Monitor Group 0 Event Counter Registers */ 716 #define AMEVCNTR00 p15, 0, c0 717 #define AMEVCNTR01 p15, 1, c0 718 #define AMEVCNTR02 p15, 2, c0 719 #define AMEVCNTR03 p15, 3, c0 720 721 /* Activity Monitor Group 0 Event Type Registers */ 722 #define AMEVTYPER00 p15, 0, c13, c6, 0 723 #define AMEVTYPER01 p15, 0, c13, c6, 1 724 #define AMEVTYPER02 p15, 0, c13, c6, 2 725 #define AMEVTYPER03 p15, 0, c13, c6, 3 726 727 /* Activity Monitor Group 1 Event Counter Registers */ 728 #define AMEVCNTR10 p15, 0, c4 729 #define AMEVCNTR11 p15, 1, c4 730 #define AMEVCNTR12 p15, 2, c4 731 #define AMEVCNTR13 p15, 3, c4 732 #define AMEVCNTR14 p15, 4, c4 733 #define AMEVCNTR15 p15, 5, c4 734 #define AMEVCNTR16 p15, 6, c4 735 #define AMEVCNTR17 p15, 7, c4 736 #define AMEVCNTR18 p15, 0, c5 737 #define AMEVCNTR19 p15, 1, c5 738 #define AMEVCNTR1A p15, 2, c5 739 #define AMEVCNTR1B p15, 3, c5 740 #define AMEVCNTR1C p15, 4, c5 741 #define AMEVCNTR1D p15, 5, c5 742 #define AMEVCNTR1E p15, 6, c5 743 #define AMEVCNTR1F p15, 7, c5 744 745 /* Activity Monitor Group 1 Event Type Registers */ 746 #define AMEVTYPER10 p15, 0, c13, c14, 0 747 #define AMEVTYPER11 p15, 0, c13, c14, 1 748 #define AMEVTYPER12 p15, 0, c13, c14, 2 749 #define AMEVTYPER13 p15, 0, c13, c14, 3 750 #define AMEVTYPER14 p15, 0, c13, c14, 4 751 #define AMEVTYPER15 p15, 0, c13, c14, 5 752 #define AMEVTYPER16 p15, 0, c13, c14, 6 753 #define AMEVTYPER17 p15, 0, c13, c14, 7 754 #define AMEVTYPER18 p15, 0, c13, c15, 0 755 #define AMEVTYPER19 p15, 0, c13, c15, 1 756 #define AMEVTYPER1A p15, 0, c13, c15, 2 757 #define AMEVTYPER1B p15, 0, c13, c15, 3 758 #define AMEVTYPER1C p15, 0, c13, c15, 4 759 #define AMEVTYPER1D p15, 0, c13, c15, 5 760 #define AMEVTYPER1E p15, 0, c13, c15, 6 761 #define AMEVTYPER1F p15, 0, c13, c15, 7 762 763 /* AMCNTENSET0 definitions */ 764 #define AMCNTENSET0_Pn_SHIFT U(0) 765 #define AMCNTENSET0_Pn_MASK U(0xffff) 766 767 /* AMCNTENSET1 definitions */ 768 #define AMCNTENSET1_Pn_SHIFT U(0) 769 #define AMCNTENSET1_Pn_MASK U(0xffff) 770 771 /* AMCNTENCLR0 definitions */ 772 #define AMCNTENCLR0_Pn_SHIFT U(0) 773 #define AMCNTENCLR0_Pn_MASK U(0xffff) 774 775 /* AMCNTENCLR1 definitions */ 776 #define AMCNTENCLR1_Pn_SHIFT U(0) 777 #define AMCNTENCLR1_Pn_MASK U(0xffff) 778 779 /* AMCR definitions */ 780 #define AMCR_CG1RZ_SHIFT U(17) 781 #define AMCR_CG1RZ_BIT (ULL(1) << AMCR_CG1RZ_SHIFT) 782 783 /* AMCFGR definitions */ 784 #define AMCFGR_NCG_SHIFT U(28) 785 #define AMCFGR_NCG_MASK U(0xf) 786 #define AMCFGR_N_SHIFT U(0) 787 #define AMCFGR_N_MASK U(0xff) 788 789 /* AMCGCR definitions */ 790 #define AMCGCR_CG0NC_SHIFT U(0) 791 #define AMCGCR_CG0NC_MASK U(0xff) 792 #define AMCGCR_CG1NC_SHIFT U(8) 793 #define AMCGCR_CG1NC_MASK U(0xff) 794 795 /******************************************************************************* 796 * Definitions for DynamicIQ Shared Unit registers 797 ******************************************************************************/ 798 #define CLUSTERPWRDN p15, 0, c15, c3, 6 799 #define CLUSTERPMCR p15, 0, c15, c5, 0 800 #define CLUSTERPMCNTENSET p15, 0, c15, c5, 1 801 #define CLUSTERPMCCNTR p15, 0, c15, c6, 0 802 #define CLUSTERPMOVSSET p15, 0, c15, c5, 3 803 #define CLUSTERPMOVSCLR p15, 0, c15, c5, 4 804 #define CLUSTERPMSELR p15, 0, c15, c5, 5 805 #define CLUSTERPMXEVTYPER p15, 0, c15, c6, 1 806 #define CLUSTERPMXEVCNTR p15, 0, c15, c6, 2 807 808 /* CLUSTERPMCR register definitions */ 809 #define CLUSTERPMCR_E_BIT BIT(0) 810 #define CLUSTERPMCR_N_SHIFT U(11) 811 #define CLUSTERPMCR_N_MASK U(0x1f) 812 813 814 /* CLUSTERPWRDN register definitions */ 815 #define DSU_CLUSTER_PWR_OFF 0 816 #define DSU_CLUSTER_PWR_ON 1 817 #define DSU_CLUSTER_PWR_MASK U(1) 818 #define DSU_CLUSTER_MEM_RET BIT(1) 819 820 #endif /* ARCH_H */ 821