1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _INTEL_ME_H 4 #define _INTEL_ME_H 5 6 #include <device/device.h> 7 #include <types.h> 8 9 #define ME_RETRY 100000 /* 1 second */ 10 #define ME_DELAY 10 /* 10 us */ 11 12 /* 13 * Management Engine PCI registers 14 */ 15 16 #define PCI_CPU_DEVICE PCI_DEV(0,0,0) 17 #define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */ 18 #define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ 19 20 #define PCI_ME_HFS 0x40 21 #define ME_HFS_CWS_RESET 0 22 #define ME_HFS_CWS_INIT 1 23 #define ME_HFS_CWS_REC 2 24 #define ME_HFS_CWS_NORMAL 5 25 #define ME_HFS_CWS_WAIT 6 26 #define ME_HFS_CWS_TRANS 7 27 #define ME_HFS_CWS_INVALID 8 28 #define ME_HFS_STATE_PREBOOT 0 29 #define ME_HFS_STATE_M0_UMA 1 30 #define ME_HFS_STATE_M3 4 31 #define ME_HFS_STATE_M0 5 32 #define ME_HFS_STATE_BRINGUP 6 33 #define ME_HFS_STATE_ERROR 7 34 #define ME_HFS_ERROR_NONE 0 35 #define ME_HFS_ERROR_UNCAT 1 36 #define ME_HFS_ERROR_IMAGE 3 37 #define ME_HFS_ERROR_DEBUG 4 38 #define ME_HFS_MODE_NORMAL 0 39 #define ME_HFS_MODE_DEBUG 2 40 #define ME_HFS_MODE_DIS 3 41 #define ME_HFS_MODE_OVER_JMPR 4 42 #define ME_HFS_MODE_OVER_MEI 5 43 #define ME_HFS_BIOS_DRAM_ACK 1 44 #define ME_HFS_ACK_NO_DID 0 45 #define ME_HFS_ACK_RESET 1 46 #define ME_HFS_ACK_PWR_CYCLE 2 47 #define ME_HFS_ACK_S3 3 48 #define ME_HFS_ACK_S4 4 49 #define ME_HFS_ACK_S5 5 50 #define ME_HFS_ACK_GBL_RESET 6 51 #define ME_HFS_ACK_CONTINUE 7 52 53 union me_hfs { 54 struct { 55 u32 working_state: 4; 56 u32 mfg_mode: 1; 57 u32 fpt_bad: 1; 58 u32 operation_state: 3; 59 u32 fw_init_complete: 1; 60 u32 ft_bup_ld_flr: 1; 61 u32 update_in_progress: 1; 62 u32 error_code: 4; 63 u32 operation_mode: 4; 64 u32 reserved: 4; 65 u32 boot_options_present: 1; 66 u32 ack_data: 3; 67 u32 bios_msg_ack: 4; 68 }; 69 u32 raw; 70 } __packed; 71 72 #define PCI_ME_UMA 0x44 73 74 union me_uma { 75 struct { 76 u32 size: 6; 77 u32 reserved_1: 10; 78 u32 valid: 1; 79 u32 reserved_0: 14; 80 u32 set_to_one: 1; 81 }; 82 u32 raw; 83 } __packed; 84 85 #define PCI_ME_H_GS 0x4c 86 #define ME_INIT_DONE 1 87 #define ME_INIT_STATUS_SUCCESS 0 88 #define ME_INIT_STATUS_NOMEM 1 89 #define ME_INIT_STATUS_ERROR 2 90 91 union me_did { 92 struct { 93 u32 uma_base: 16; 94 u32 reserved: 8; 95 u32 status: 4; 96 u32 init_done: 4; 97 }; 98 u32 raw; 99 } __packed; 100 101 #define PCI_ME_GMES 0x48 102 #define ME_GMES_PHASE_ROM 0 103 #define ME_GMES_PHASE_BUP 1 104 #define ME_GMES_PHASE_UKERNEL 2 105 #define ME_GMES_PHASE_POLICY 3 106 #define ME_GMES_PHASE_MODULE 4 107 #define ME_GMES_PHASE_UNKNOWN 5 108 #define ME_GMES_PHASE_HOST 6 109 110 union me_gmes { 111 struct { 112 u32 bist_in_prog : 1; 113 u32 icc_prog_sts : 2; 114 u32 invoke_mebx : 1; 115 u32 cpu_replaced_sts : 1; 116 u32 mbp_rdy : 1; 117 u32 mfs_failure : 1; 118 u32 warm_rst_req_for_df : 1; 119 u32 cpu_replaced_valid : 1; 120 u32 reserved_1 : 2; 121 u32 fw_upd_ipu : 1; 122 u32 reserved_2 : 4; 123 u32 current_state: 8; 124 u32 current_pmevent: 4; 125 u32 progress_code: 4; 126 }; 127 u32 raw; 128 } __packed; 129 130 #define PCI_ME_HERES 0xbc 131 #define PCI_ME_EXT_SHA1 0x00 132 #define PCI_ME_EXT_SHA256 0x02 133 #define PCI_ME_HER(x) (0xc0+(4*(x))) 134 135 union me_heres { 136 struct { 137 u32 extend_reg_algorithm: 4; 138 u32 reserved: 26; 139 u32 extend_feature_present: 1; 140 u32 extend_reg_valid: 1; 141 }; 142 u32 raw; 143 } __packed; 144 145 /* 146 * Management Engine MEI registers 147 */ 148 149 #define MEI_H_CB_WW 0x00 150 #define MEI_H_CSR 0x04 151 #define MEI_ME_CB_RW 0x08 152 #define MEI_ME_CSR_HA 0x0c 153 154 struct mei_csr { 155 u32 interrupt_enable: 1; 156 u32 interrupt_status: 1; 157 u32 interrupt_generate: 1; 158 u32 ready: 1; 159 u32 reset: 1; 160 u32 reserved: 3; 161 u32 buffer_read_ptr: 8; 162 u32 buffer_write_ptr: 8; 163 u32 buffer_depth: 8; 164 } __packed; 165 166 #define MEI_ADDRESS_CORE 0x01 167 #define MEI_ADDRESS_AMT 0x02 168 #define MEI_ADDRESS_RESERVED 0x03 169 #define MEI_ADDRESS_WDT 0x04 170 #define MEI_ADDRESS_MKHI 0x07 171 #define MEI_ADDRESS_ICC 0x08 172 #define MEI_ADDRESS_THERMAL 0x09 173 174 #define MEI_HOST_ADDRESS 0 175 176 struct mei_header { 177 u32 client_address: 8; 178 u32 host_address: 8; 179 u32 length: 9; 180 u32 reserved: 6; 181 u32 is_complete: 1; 182 } __packed; 183 184 #define MKHI_GROUP_ID_CBM 0x00 185 #define MKHI_GROUP_ID_FWCAPS 0x03 186 #define MKHI_GROUP_ID_MDES 0x08 187 #define MKHI_GROUP_ID_GEN 0xff 188 189 #define MKHI_GLOBAL_RESET 0x0b 190 191 #define MKHI_FWCAPS_GET_RULE 0x02 192 #define MKHI_FWCAPS_SET_RULE 0x03 193 194 #define MKHI_DISABLE_RULE_ID 0x06 195 196 #define CMOS_ME_STATE(state) ((state) & 0x1) 197 #define CMOS_ME_CHANGED(state) (((state) & 0x2) >> 1) 198 #define CMOS_ME_STATE_NORMAL 0 199 #define CMOS_ME_STATE_DISABLED 1 200 #define CMOS_ME_STATE_CHANGED 2 201 202 #define ME_ENABLE_TIMEOUT 20000 203 204 struct me_disable { 205 u32 rule_id; 206 u16 data; 207 } __packed; 208 209 #define MKHI_MDES_ENABLE 0x09 210 211 #define MKHI_GET_FW_VERSION 0x02 212 #define MKHI_END_OF_POST 0x0c 213 #define MKHI_FEATURE_OVERRIDE 0x14 214 215 struct mkhi_header { 216 u32 group_id: 8; 217 u32 command: 7; 218 u32 is_response: 1; 219 u32 reserved: 8; 220 u32 result: 8; 221 } __packed; 222 223 struct me_fw_version { 224 u16 code_minor; 225 u16 code_major; 226 u16 code_build_number; 227 u16 code_hot_fix; 228 u16 recovery_minor; 229 u16 recovery_major; 230 u16 recovery_build_number; 231 u16 recovery_hot_fix; 232 } __packed; 233 234 #define HECI_EOP_STATUS_SUCCESS 0x0 235 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 236 237 #define CBM_RR_GLOBAL_RESET 0x01 238 239 #define GLOBAL_RESET_BIOS_MRC 0x01 240 #define GLOBAL_RESET_BIOS_POST 0x02 241 #define GLOBAL_RESET_MEBX 0x03 242 243 struct me_global_reset { 244 u8 request_origin; 245 u8 reset_type; 246 } __packed; 247 248 typedef enum { 249 ME_NORMAL_BIOS_PATH, 250 ME_S3WAKE_BIOS_PATH, 251 ME_ERROR_BIOS_PATH, 252 ME_RECOVERY_BIOS_PATH, 253 ME_DISABLE_BIOS_PATH, 254 ME_FIRMWARE_UPDATE_BIOS_PATH, 255 } me_bios_path; 256 257 /* Defined in me_common.c for both ramstage and smm */ 258 const char *const me_get_bios_path_string(int path); 259 260 void mei_read_dword_ptr(void *ptr, int offset); 261 void mei_write_dword_ptr(void *ptr, int offset); 262 263 #ifndef __SIMPLE_DEVICE__ 264 bool enter_soft_temp_disable(void); 265 void enter_soft_temp_disable_wait(void); 266 void exit_soft_temp_disable(struct device *dev); 267 void exit_soft_temp_disable_wait(struct device *dev); 268 #endif 269 270 void read_host_csr(struct mei_csr *csr); 271 void write_host_csr(struct mei_csr *csr); 272 273 void read_me_csr(struct mei_csr *csr); 274 275 void write_cb(u32 dword); 276 u32 read_cb(void); 277 278 int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, 279 void *req_data, void *rsp_data, int rsp_bytes); 280 281 void update_mei_base_address(void); 282 bool is_mei_base_address_valid(void); 283 int intel_mei_setup(struct device *dev); 284 int intel_me_extend_valid(struct device *dev); 285 void intel_me_hide(struct device *dev); 286 287 /* Defined in me_status.c for both romstage and ramstage */ 288 void intel_me_status(union me_hfs *hfs, union me_gmes *gmes); 289 290 void intel_early_me_status(void); 291 int intel_early_me_init(void); 292 int intel_early_me_uma_size(void); 293 int intel_early_me_init_done(u8 status); 294 295 void intel_me_finalize_smm(void); 296 297 typedef struct { 298 u32 major_version : 16; 299 u32 minor_version : 16; 300 u32 hotfix_version : 16; 301 u32 build_version : 16; 302 } __packed mbp_fw_version_name; 303 304 typedef struct { 305 u8 num_icc_profiles; 306 u8 icc_profile_soft_strap; 307 u8 icc_profile_index; 308 u8 reserved; 309 u32 register_lock_mask[3]; 310 } __packed mbp_icc_profile; 311 312 typedef struct { 313 u32 full_net : 1; 314 u32 std_net : 1; 315 u32 manageability : 1; 316 u32 small_business : 1; 317 u32 l3manageability : 1; 318 u32 intel_at : 1; 319 u32 intel_cls : 1; 320 u32 reserved : 3; 321 u32 intel_mpc : 1; 322 u32 icc_over_clocking : 1; 323 u32 pavp : 1; 324 u32 reserved_1 : 4; 325 u32 ipv6 : 1; 326 u32 kvm : 1; 327 u32 och : 1; 328 u32 vlan : 1; 329 u32 tls : 1; 330 u32 reserved_4 : 1; 331 u32 wlan : 1; 332 u32 reserved_5 : 8; 333 } __packed mefwcaps_sku; 334 335 typedef struct { 336 u16 lock_state : 1; 337 u16 authenticate_module : 1; 338 u16 s3authentication : 1; 339 u16 flash_wear_out : 1; 340 u16 flash_variable_security : 1; 341 u16 wwan3gpresent : 1; 342 u16 wwan3goob : 1; 343 u16 reserved : 9; 344 } __packed tdt_state_flag; 345 346 typedef struct { 347 u8 state; 348 u8 last_theft_trigger; 349 tdt_state_flag flags; 350 } __packed tdt_state_info; 351 352 typedef struct { 353 u32 platform_target_usage_type : 4; 354 u32 platform_target_market_type : 2; 355 u32 super_sku : 1; 356 u32 reserved : 1; 357 u32 intel_me_fw_image_type : 4; 358 u32 platform_brand : 4; 359 u32 reserved_1 : 16; 360 } __packed platform_type_rule_data; 361 362 typedef struct { 363 mefwcaps_sku fw_capabilities; 364 u8 available; 365 } mbp_fw_caps; 366 367 typedef struct { 368 u16 device_id; 369 u16 fuse_test_flags; 370 u32 umchid[4]; 371 } __packed mbp_rom_bist_data; 372 373 typedef struct { 374 u32 key[8]; 375 } mbp_platform_key; 376 377 typedef struct { 378 platform_type_rule_data rule_data; 379 u8 available; 380 } mbp_plat_type; 381 382 typedef struct { 383 mbp_fw_version_name fw_version_name; 384 mbp_fw_caps fw_caps_sku; 385 mbp_rom_bist_data rom_bist_data; 386 mbp_platform_key platform_key; 387 mbp_plat_type fw_plat_type; 388 mbp_icc_profile icc_profile; 389 tdt_state_info at_state; 390 u32 mfsintegrity; 391 } me_bios_payload; 392 393 typedef struct { 394 u32 mbp_size : 8; 395 u32 num_entries : 8; 396 u32 rsvd : 16; 397 } __packed mbp_header; 398 399 typedef struct { 400 u32 app_id : 8; 401 u32 item_id : 8; 402 u32 length : 8; 403 u32 rsvd : 8; 404 } __packed mbp_item_header; 405 406 struct me_fwcaps { 407 u32 id; 408 u8 length; 409 mefwcaps_sku caps_sku; 410 u8 reserved[3]; 411 } __packed; 412 413 #endif /* _INTEL_ME_H */ 414