1## SPDX-License-Identifier: GPL-2.0-only 2 3menu "Console" 4 5config NO_BOOTBLOCK_CONSOLE 6 bool 7 depends on SEPARATE_ROMSTAGE 8 9config BOOTBLOCK_CONSOLE 10 bool "Enable early (bootblock) console output." 11 depends on !NO_BOOTBLOCK_CONSOLE 12 default y 13 help 14 Use console during the bootblock if supported 15 16config POSTCAR_CONSOLE 17 bool "Enable console output during postcar." 18 depends on POSTCAR_STAGE 19 default y 20 help 21 Use console during the postcar if supported 22 23config SQUELCH_EARLY_SMP 24 bool "Squelch AP CPUs from early console." 25 default y 26 depends on SMP 27 help 28 When selected only the BSP CPU will output to early console. 29 30 Console drivers have unpredictable behaviour if multiple threads 31 attempt to share the same resources without a spinlock. 32 33 If unsure, say Y. 34 35config CONSOLE_SERIAL 36 bool "Serial port console output" 37 default y 38 depends on DRIVERS_UART 39 help 40 Send coreboot debug output to a serial port. 41 42 The type of serial port driver selected based on your configuration is 43 shown on the following menu line. Supporting multiple different types 44 of UARTs in one build is not supported. 45 46config FIXED_UART_FOR_CONSOLE 47 bool 48 help 49 Select to remove the prompt from UART_FOR_CONSOLE in case a 50 specific UART has to be used (e.g. when the platform code 51 performs dangerous configurations). 52 53if CONSOLE_SERIAL || CONSOLE_CBMEM_DUMP_TO_UART 54 55 comment "I/O mapped, 8250-compatible" 56 depends on DRIVERS_UART_8250IO 57 58 comment "memory mapped, 8250-compatible" 59 depends on DRIVERS_UART_8250MEM 60 61 comment "device-specific UART" 62 depends on HAVE_UART_SPECIAL 63 64config OVERRIDE_UART_FOR_CONSOLE 65 bool 66 help 67 Set to "y" when the platform overrides the index of uart port by providing 68 a get_uart_for_console routine. 69 70if !OVERRIDE_UART_FOR_CONSOLE 71 72config UART_FOR_CONSOLE 73 int 74 prompt "Index for UART port to use for console" if !FIXED_UART_FOR_CONSOLE 75 default 0 76 help 77 Select an I/O port to use for serial console: 78 0 = 0x3f8, 1 = 0x2f8, 2 = 0x3e8, 3 = 0x2e8 79 80# FIXME: Early programming in romstage is incorrect as we should 81# program different LDN to actually change the physical port. 82config TTYS0_BASE 83 hex 84 depends on DRIVERS_UART 85 default 0x3f8 if UART_FOR_CONSOLE = 0 86 default 0x2f8 if UART_FOR_CONSOLE = 1 87 default 0x3e8 if UART_FOR_CONSOLE = 2 88 default 0x2e8 if UART_FOR_CONSOLE = 3 89 help 90 Map the COM port number to the respective I/O port. 91 92comment "Serial port base address = 0x3f8" 93depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 0 94comment "Serial port base address = 0x2f8" 95depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 1 96comment "Serial port base address = 0x3e8" 97depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 2 98comment "Serial port base address = 0x2e8" 99depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 3 100 101endif 102 103config UART_OVERRIDE_BAUDRATE 104 bool 105 help 106 Set to "y" when the platform overrides the baudrate by providing 107 a get_uart_baudrate routine. 108 109if !UART_OVERRIDE_BAUDRATE 110 111choice 112 prompt "Baud rate" 113 default CONSOLE_SERIAL_115200 114 115config CONSOLE_SERIAL_921600 116 bool "921600" 117 help 118 Set serial port Baud rate to 921600. 119config CONSOLE_SERIAL_460800 120 bool "460800" 121 help 122 Set serial port Baud rate to 460800. 123config CONSOLE_SERIAL_230400 124 bool "230400" 125 help 126 Set serial port Baud rate to 230400. 127config CONSOLE_SERIAL_115200 128 bool "115200" 129 help 130 Set serial port Baud rate to 115200. 131config CONSOLE_SERIAL_57600 132 bool "57600" 133 help 134 Set serial port Baud rate to 57600. 135config CONSOLE_SERIAL_38400 136 bool "38400" 137 help 138 Set serial port Baud rate to 38400. 139config CONSOLE_SERIAL_19200 140 bool "19200" 141 help 142 Set serial port Baud rate to 19200. 143config CONSOLE_SERIAL_9600 144 bool "9600" 145 help 146 Set serial port Baud rate to 9600. 147 148endchoice 149 150#FIXME(dhendrix): Change name to SERIAL_BAUD? (Stefan sayz: yes!!) 151config TTYS0_BAUD 152 int 153 default 921600 if CONSOLE_SERIAL_921600 154 default 460800 if CONSOLE_SERIAL_460800 155 default 230400 if CONSOLE_SERIAL_230400 156 default 115200 if CONSOLE_SERIAL_115200 157 default 57600 if CONSOLE_SERIAL_57600 158 default 38400 if CONSOLE_SERIAL_38400 159 default 19200 if CONSOLE_SERIAL_19200 160 default 9600 if CONSOLE_SERIAL_9600 161 help 162 Map the Baud rates to an integer. 163 164endif 165 166# TODO: Allow user-friendly selection of settings other than 8n1. 167config TTYS0_LCS 168 int 169 default 3 170 depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM 171 172endif # CONSOLE_SERIAL 173 174config SPKMODEM 175 bool "spkmodem (console on speaker) console output" 176 default n 177 depends on ARCH_X86 178 help 179 Send coreboot debug output through speaker 180 181config CONSOLE_USB 182 bool "USB dongle console output" 183 depends on USBDEBUG 184 default y 185 help 186 Send coreboot debug output to USB. 187 188 Configuration for USB hardware is under menu Generic Drivers. 189 190# TODO: Deps? 191# TODO: Improve description. 192config CONSOLE_NE2K 193 bool "Network console over NE2000 compatible Ethernet adapter" 194 default n 195 depends on PCI 196 help 197 Send coreboot debug output to a Ethernet console, it works 198 same way as Linux netconsole, packets are received to UDP 199 port 6666 on IP/MAC specified with options below. 200 Use following netcat command: nc -u -l -p 6666 201 202config CONSOLE_NE2K_DST_MAC 203 depends on CONSOLE_NE2K 204 string "Destination MAC address of remote system" 205 default "00:13:d4:76:a2:ac" 206 help 207 Type in either MAC address of logging system or MAC address 208 of the router. 209 210config CONSOLE_NE2K_DST_IP 211 depends on CONSOLE_NE2K 212 string "Destination IP of logging system" 213 default "10.0.1.27" 214 help 215 This is IP address of the system running for example 216 netcat command to dump the packets. 217 218config CONSOLE_NE2K_SRC_IP 219 depends on CONSOLE_NE2K 220 string "IP address of coreboot system" 221 default "10.0.1.253" 222 help 223 This is the IP of the coreboot system 224 225config CONSOLE_NE2K_IO_PORT 226 depends on CONSOLE_NE2K 227 hex "NE2000 adapter fixed IO port address" 228 default 0xe00 229 help 230 This is the IO port address for the IO port 231 on the card, please select some non-conflicting region, 232 32 bytes of IO spaces will be used (and align on 32 bytes 233 boundary, qemu needs broader align) 234 235config CONSOLE_CBMEM 236 bool "Send console output to a CBMEM buffer" 237 default y 238 help 239 Enable this to save the console output in a CBMEM buffer. This would 240 allow to see coreboot console output from Linux space. 241 242if CONSOLE_CBMEM 243 244config CONSOLE_CBMEM_BUFFER_SIZE 245 hex "Room allocated for console output in CBMEM" 246 default 0x20000 247 help 248 Space allocated for console output storage in CBMEM. The default 249 value (128K or 0x20000 bytes) is large enough to accommodate 250 even the BIOS_SPEW level. 251 252config CONSOLE_CBMEM_DUMP_TO_UART 253 depends on !CONSOLE_SERIAL 254 bool "Dump CBMEM console on resets" 255 default n 256 help 257 Enable this to have CBMEM console buffer contents dumped on the 258 serial output in case serial console is disabled and the device 259 resets itself while trying to boot the payload. 260 261config CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS 262 bool 263 help 264 Pre-bootblock stages (i.e., VBOOT_STARTS_BEFORE_BOOTBLOCK) might not 265 have the ability to log to the UART, so their console messages are 266 inaccessible until the boot processes gets into the payload or OS. 267 This feature will dump the pre-bootblock CBMEM console immediately 268 after the bootblock console is initialized. 269endif 270 271config CONSOLE_SPI_FLASH 272 bool "SPI Flash console output" 273 default n 274 depends on BOOT_DEVICE_SPI_FLASH 275 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if !COMMON_CBFS_SPI_WRAPPER 276 help 277 Send coreboot debug output to the SPI Flash in the FMAP CONSOLE area 278 279 This option can cause premature wear on the SPI flash and should not 280 be used as a normal means of debugging. It is only to be enabled and 281 used when porting a new motherboard which has no other console 282 available (no UART, no POST, no cbmem access(non bootable)). Since 283 a non bootable machine will require the use of an external SPI Flash 284 programmer, the developer can grab the console log at the same time. 285 286 The flash console will not be erased on reboot, so once it is full, 287 the flashconsole driver will stop writing to it. This is to avoid 288 wear on the flash, and to avoid erasing sectors (which may freeze 289 the SPI controller on skylake). 290 291 The 'CONSOLE' area can be extracted from the FMAP with : 292 cbfstool rom.bin read -r CONSOLE -f console.log 293 294config CONSOLE_SPI_FLASH_BUFFER_SIZE 295 hex "Room allocated for console output in FMAP" 296 default 0x20000 297 depends on CONSOLE_SPI_FLASH 298 help 299 Space allocated for console output storage in FMAP. The default 300 value (128K or 0x20000 bytes) is large enough to accommodate 301 even the BIOS_SPEW level. 302 303config CONSOLE_I2C_SMBUS 304 bool "SMBus console output" 305 depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS 306 help 307 Send coreboot debug output to the SMBus. 308 The output can be read with an I2C slave device connected 309 the SMBus. Please refer to the technotes section of the 310 coreboot documentation for more details. 311 312if CONSOLE_I2C_SMBUS 313 comment "Set logging device address and data register address" 314 315config CONSOLE_I2C_SMBUS_SLAVE_ADDRESS 316 hex "I2C slave address of the logging device" 317 default 0x48 if SC16IS7XX_INIT 318 help 319 I2C address of the device which logs the data. 320 321config CONSOLE_I2C_SMBUS_HAVE_DATA_REGISTER 322 bool "Write to a specific data register" 323 default y if SC16IS7XX_INIT 324 help 325 Select this to provide a register address that will 326 be sent before every data byte. 327 328config CONSOLE_I2C_SMBUS_SLAVE_DATA_REGISTER 329 hex "Data register address of the I2C logging device" 330 depends on CONSOLE_I2C_SMBUS_HAVE_DATA_REGISTER 331 default 0x00 if SC16IS7XX_INIT 332 help 333 This an 8-bit data register. 334 335config SC16IS7XX_INIT 336 bool "Initialize SC16IS7XX I2C to UART converter chip" 337 help 338 SC16IS7XX is a slave I2C to UART converter chip. Enabling 339 this option will initialize the chip. 340 341 The default I2C slave address value 0x48 is the address of 342 SC16IS7XX I2C to UART converter chip when the A1 and A0 pins 343 are set to Vcc. 344 345 The default data register address value 0x00 is the data 346 register address of SC16IS7XX I2C to UART converter chip. 347 348endif # CONSOLE_I2C_SMBUS 349 350config CONSOLE_QEMU_DEBUGCON 351 bool "QEMU debug console output" 352 depends on CPU_QEMU_X86 353 default y 354 help 355 Send coreboot debug output to QEMU's isa-debugcon device: 356 357 qemu-system-x86_64 \ 358 -chardev file,id=debugcon,path=/dir/file.log \ 359 -device isa-debugcon,iobase=0x402,chardev=debugcon 360 361config CONSOLE_QEMU_DEBUGCON_PORT 362 hex "QEMU debug console port" 363 depends on CONSOLE_QEMU_DEBUGCON 364 default 0x402 365 366config EM100PRO_SPI_CONSOLE 367 bool "EM100Pro SPI debug console output" 368 depends on HAVE_EM100PRO_SPI_CONSOLE_SUPPORT && !DEBUG_SPI_FLASH 369 help 370 Enable support for the debug console on the Dediprog EM100Pro. 371 This is currently working only in ramstage due to how the spi 372 drivers are written. 373 374config CONSOLE_SYSTEM76_EC 375 bool "System76 EC console output" 376 default n 377 depends on EC_SYSTEM76_EC 378 help 379 Send coreboot debug output to a System76 embedded controller. 380 381config CONSOLE_AMD_SIMNOW 382 bool "AMD SimNow console output" 383 default n 384 depends on SOC_AMD_COMMON && !POST_IO 385 select CONSOLE_POST 386 help 387 Send coreboot debug output to IO ports for SimNow 388 389config CONSOLE_OVERRIDE_LOGLEVEL 390 bool 391 help 392 Set to "y" when the platform overrides the loglevel by providing 393 a get_console_loglevel routine. 394 395if !CONSOLE_OVERRIDE_LOGLEVEL 396 397choice 398 prompt "Default console log level" 399 default DEFAULT_CONSOLE_LOGLEVEL_8 if CHROMEOS 400 default DEFAULT_CONSOLE_LOGLEVEL_7 401 402config DEFAULT_CONSOLE_LOGLEVEL_8 403 bool "8: SPEW" 404 help 405 Way too many details. 406config DEFAULT_CONSOLE_LOGLEVEL_7 407 bool "7: DEBUG" 408 help 409 Debug-level messages. 410config DEFAULT_CONSOLE_LOGLEVEL_6 411 bool "6: INFO" 412 help 413 Informational messages. 414config DEFAULT_CONSOLE_LOGLEVEL_5 415 bool "5: NOTICE" 416 help 417 Normal but significant conditions. 418config DEFAULT_CONSOLE_LOGLEVEL_4 419 bool "4: WARNING" 420 help 421 Warning conditions. 422config DEFAULT_CONSOLE_LOGLEVEL_3 423 bool "3: ERR" 424 help 425 Error conditions. 426config DEFAULT_CONSOLE_LOGLEVEL_2 427 bool "2: CRIT" 428 help 429 Critical conditions. 430config DEFAULT_CONSOLE_LOGLEVEL_1 431 bool "1: ALERT" 432 help 433 Action must be taken immediately. 434config DEFAULT_CONSOLE_LOGLEVEL_0 435 bool "0: EMERG" 436 help 437 System is unusable. 438 439endchoice 440 441config DEFAULT_CONSOLE_LOGLEVEL 442 int 443 default 0 if DEFAULT_CONSOLE_LOGLEVEL_0 444 default 1 if DEFAULT_CONSOLE_LOGLEVEL_1 445 default 2 if DEFAULT_CONSOLE_LOGLEVEL_2 446 default 3 if DEFAULT_CONSOLE_LOGLEVEL_3 447 default 4 if DEFAULT_CONSOLE_LOGLEVEL_4 448 default 5 if DEFAULT_CONSOLE_LOGLEVEL_5 449 default 6 if DEFAULT_CONSOLE_LOGLEVEL_6 450 default 7 if DEFAULT_CONSOLE_LOGLEVEL_7 451 default 8 if DEFAULT_CONSOLE_LOGLEVEL_8 452 help 453 Map the log level config names to an integer. 454 455endif 456 457config CONSOLE_USE_LOGLEVEL_PREFIX 458 bool "Use loglevel prefix to indicate line loglevel" 459 default y 460 help 461 When enabled, if the code contains a: 462 `printk(BIOS_DEBUG, "This is a debug message!\n")`, 463 it will show up as: 464 `[DEBUG] This is a debug message!` 465 466config CONSOLE_USE_ANSI_ESCAPES 467 bool "Use ANSI escape sequences for console highlighting" 468 default y if !CONSOLE_AMD_SIMNOW 469 help 470 If enabled, certain consoles (e.g. UART) that are meant to be read on 471 a terminal will use ANSI escape sequences (like `ESC [1m`) to 472 highlight lines based on their log level. Disable this if your 473 terminal does not support ANSI escape sequences. 474 475config NO_POST 476 bool "Don't show any POST codes" 477 default n 478 479config CMOS_POST 480 bool "Store post codes in CMOS for debugging" 481 depends on !NO_POST && PC80_SYSTEM 482 default n 483 help 484 If enabled, coreboot will store post codes in CMOS and switch between 485 two offsets on each boot so the last post code in the previous boot 486 can be retrieved. This uses 3 bytes of CMOS. 487 488config CMOS_POST_OFFSET 489 hex "Offset into CMOS to store POST codes" 490 depends on CMOS_POST 491 default 0x0 492 help 493 If CMOS_POST is enabled then an offset into CMOS must be provided. 494 If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value 495 defined in the mainboard option table. 496 497config CONSOLE_POST 498 bool "Show POST codes on the debug console" 499 depends on !NO_POST 500 default n 501 help 502 If enabled, coreboot will additionally print POST codes (which are 503 usually displayed using a so-called "POST card" ISA/PCI/PCI-E 504 device) on the debug console. 505 506config POST_DEVICE 507 bool "Send POST codes to an external device" 508 depends on !NO_POST 509 default y 510 511choice 512 prompt "Device to send POST codes to" 513 depends on POST_DEVICE 514 default POST_DEVICE_LPC if DEFAULT_POST_ON_LPC 515 default POST_DEVICE_NONE 516 517config POST_DEVICE_NONE 518 bool "None" 519config POST_DEVICE_LPC 520 bool "LPC" 521 depends on PCI 522config POST_DEVICE_PCI_PCIE 523 bool "PCI/PCIe" 524 depends on PCI 525endchoice 526 527config DEFAULT_POST_ON_LPC 528 bool 529 default n 530 531config POST_IO 532 bool "Send POST codes to an IO port" 533 depends on PC80_SYSTEM && !NO_POST 534 default y 535 help 536 If enabled, POST codes will be written to an IO port. 537 538config POST_IO_PORT 539 depends on POST_IO 540 hex "IO port for POST codes" 541 default 0x80 542 help 543 POST codes on x86 are typically written to the LPC bus on port 544 0x80. However, it may be desirable to change the port number 545 depending on the presence of coprocessors/microcontrollers or if the 546 platform does not support IO in the conventional x86 manner. 547 548config NO_EARLY_BOOTBLOCK_POSTCODES 549 def_bool n 550 help 551 Some chipsets require that the routing for the port 80h POST 552 code be configured before any POST codes are sent out. If this is 553 not done, the system can hang on the first POST code. This 554 initialization can be done in the boot block, but there are a couple 555 of POST codes that go out before the chipset's C bootblock 556 initialization can happen. This option suppresses all postcodes in 557 the early assembly code. 558 559config HWBASE_DEBUG_CB 560 bool 561 default y if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 562 default n 563 564config HWBASE_DEBUG_NULL 565 def_bool y 566 depends on !HWBASE_DEBUG_CB 567 568endmenu 569