1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file cm_def.h 24 //! \brief Contains CM definitions 25 //! 26 27 #ifndef MEDIADRIVER_AGNOSTIC_COMMON_CM_CMDEF_H_ 28 #define MEDIADRIVER_AGNOSTIC_COMMON_CM_CMDEF_H_ 29 30 #include "cm_def_os.h" 31 #include "cm_common.h" 32 33 //! Map CM_SURFACE_FORMAT to MOS_FORMAT 34 #define CM_SURFACE_FORMAT MOS_FORMAT 35 #define CM_SURFACE_FORMAT_INVALID Format_Invalid 36 #define CM_SURFACE_FORMAT_A8R8G8B8 Format_A8R8G8B8 37 #define CM_SURFACE_FORMAT_X8R8G8B8 Format_X8R8G8B8 38 #define CM_SURFACE_FORMAT_A8B8G8R8 Format_A8B8G8R8 39 #define CM_SURFACE_FORMAT_A8 Format_A8 40 #define CM_SURFACE_FORMAT_P8 Format_P8 41 #define CM_SURFACE_FORMAT_R32F Format_R32F 42 #define CM_SURFACE_FORMAT_NV12 Format_NV12 43 #define CM_SURFACE_FORMAT_P016 Format_P016 44 #define CM_SURFACE_FORMAT_P010 Format_P010 45 #define CM_SURFACE_FORMAT_P208 Format_P208 46 #define CM_SURFACE_FORMAT_V8U8 Format_V8U8 47 #define CM_SURFACE_FORMAT_A8L8 Format_A8L8 48 #define CM_SURFACE_FORMAT_D16 Format_D16 49 #define CM_SURFACE_FORMAT_A16B16G16R16F Format_A16B16G16R16F 50 #define CM_SURFACE_FORMAT_R10G10B10A2 Format_R10G10B10A2 51 #define CM_SURFACE_FORMAT_A16B16G16R16 Format_A16B16G16R16 52 #define CM_SURFACE_FORMAT_IRW0 Format_IRW0 53 #define CM_SURFACE_FORMAT_IRW1 Format_IRW1 54 #define CM_SURFACE_FORMAT_IRW2 Format_IRW2 55 #define CM_SURFACE_FORMAT_IRW3 Format_IRW3 56 #define CM_SURFACE_FORMAT_R32_SINT Format_R32S 57 #define CM_SURFACE_FORMAT_R16_FLOAT Format_R16F 58 #define CM_SURFACE_FORMAT_A8P8 Format_A8P8 59 #define CM_SURFACE_FORMAT_I420 Format_I420 60 #define CM_SURFACE_FORMAT_IMC3 Format_IMC3 61 #define CM_SURFACE_FORMAT_IA44 Format_IA44 62 #define CM_SURFACE_FORMAT_AI44 Format_AI44 63 #define CM_SURFACE_FORMAT_Y410 Format_Y410 64 #define CM_SURFACE_FORMAT_Y416 Format_Y416 65 #define CM_SURFACE_FORMAT_Y210 Format_Y210 66 #define CM_SURFACE_FORMAT_Y216 Format_Y216 67 #define CM_SURFACE_FORMAT_AYUV Format_AYUV 68 #define CM_SURFACE_FORMAT_YV12 Format_YV12 69 #define CM_SURFACE_FORMAT_400P Format_400P 70 #define CM_SURFACE_FORMAT_411P Format_411P 71 #define CM_SURFACE_FORMAT_411R Format_411R 72 #define CM_SURFACE_FORMAT_422H Format_422H 73 #define CM_SURFACE_FORMAT_422V Format_422V 74 #define CM_SURFACE_FORMAT_444P Format_444P 75 #define CM_SURFACE_FORMAT_RGBP Format_RGBP 76 #define CM_SURFACE_FORMAT_BGRP Format_BGRP 77 #define CM_SURFACE_FORMAT_R8_UINT Format_R8U 78 #define CM_SURFACE_FORMAT_R32_UINT Format_R32U 79 #define CM_SURFACE_FORMAT_R16_SINT Format_R16S 80 #define CM_SURFACE_FORMAT_R16_UNORM Format_R16UN 81 #define CM_SURFACE_FORMAT_R8G8_UNORM Format_R8G8UN 82 #define CM_SURFACE_FORMAT_R16_UINT Format_R16U 83 #define CM_SURFACE_FORMAT_R16_TYPELESS Format_R16 84 #define CM_SURFACE_FORMAT_R16G16_UNORM Format_R16G16UN 85 #define CM_SURFACE_FORMAT_L16 Format_L16 86 #define CM_SURFACE_FORMAT_YUY2 Format_YUY2 87 #define CM_SURFACE_FORMAT_L8 Format_L8 88 #define CM_SURFACE_FORMAT_UYVY Format_UYVY 89 #define CM_SURFACE_FORMAT_VYUY Format_VYUY 90 #define CM_SURFACE_FORMAT_R8G8_SNORM Format_R8G8SN 91 #define CM_SURFACE_FORMAT_Y16_SNORM Format_Y16S 92 #define CM_SURFACE_FORMAT_Y16_UNORM Format_Y16U 93 #define CM_SURFACE_FORMAT_Y8_UNORM Format_Y8 94 #define CM_SURFACE_FORMAT_BUFFER_2D Format_Buffer_2D 95 #define CM_SURFACE_FORMAT_D32F Format_D32F 96 #define CM_SURFACE_FORMAT_D24_UNORM_S8_UINT Format_D24S8UN 97 #define CM_SURFACE_FORMAT_D32F_S8X24_UINT Format_D32S8X24_FLOAT 98 #define CM_SURFACE_FORMAT_R16G16_SINT Format_R16G16S 99 #define CM_SURFACE_FORMAT_R24G8_TYPELESS Format_R24G8 100 #define CM_SURFACE_FORMAT_R32_TYPELESS Format_R32 101 #define CM_SURFACE_FORMAT_R32G8X24_TYPELESS Format_R32G8X24 102 #define CM_SURFACE_FORMAT_R8_UNORM Format_R8UN 103 #define CM_SURFACE_FORMAT_R32G32B32A32F Format_R32G32B32A32F 104 105 #define CM_RT_API 106 #define CMRT_UMD_API 107 108 #define CISA_MAGIC_NUMBER 0x41534943 //"CISA" 109 #define CM_MIN_SURF_WIDTH 1 110 #define CM_MIN_SURF_HEIGHT 1 111 #define CM_MIN_SURF_DEPTH 2 112 113 #define CM_MAX_1D_SURF_WIDTH 0x80000000 // 2^31, 2 GB 114 115 #define CM_PAGE_ALIGNMENT 0x1000 116 #define CM_PAGE_ALIGNMENT_MASK 0x0FFF 117 118 #define CM_MAX_3D_SURF_WIDTH 2048 119 #define CM_MAX_3D_SURF_HEIGHT 2048 120 #define CM_MAX_3D_SURF_DEPTH 2048 121 122 #define CM_INIT_PROGRAM_COUNT 16 123 #define CM_INIT_KERNEL_COUNT 64 124 #define CM_INIT_SAMPLER_COUNT 32 125 #define CM_INIT_TASK_COUNT 16 126 #define CM_INIT_THREADGROUPSPACE_COUNT 8 127 #define CM_INIT_SAMPLER_8X8_STATE_COUNT 8 128 #define CM_INIT_EVENT_COUNT 128 129 #define CM_INIT_THREADSPACE_COUNT 8 130 #define CM_INIT_VEBOX_COUNT 16 131 132 #define CM_NO_EVENT ((CmEvent *)(-1)) // Magic Number for invisible event. 133 134 #define _NAME(...) #__VA_ARGS__ 135 // hard ceiling 136 #define CM_MAX_OPTION_SIZE_IN_BYTE 512 137 #define CM_MAX_KERNEL_NAME_SIZE_IN_BYTE 256 138 #define CM_MAX_ISA_FILE_NAME_SIZE_IN_BYTE 256 139 #define CM_MAX_KERNEL_STRING_IN_BYTE 512 140 141 //Time in seconds before kernel should timeout 142 #define CM_MAX_TIMEOUT 2 143 //Time in milliseconds before kernel should timeout 144 #define CM_MAX_TIMEOUT_MS CM_MAX_TIMEOUT*1000 145 146 #define CM_INVALID_KERNEL_INDEX 0xFFFFFFFF 147 148 #define CM_VME_FORWARD_ARRAY_LENGTH 16 149 #define CM_VME_BACKWARD_ARRAY_LENGTH 16 150 151 #define CM_INVALID_VME_SURFACE 0xFFFFFFFF 152 153 #define CM_INVALID_GLOBAL_SURFACE 0xFFFFFFFF 154 155 //GT-PIN 156 #define CM_MAX_ENTRY_FOR_A_SURFACE 6 //maxium planes(3)*dual state(2) 157 #define CM_GTPIN_BUFFER_NUM 3 158 159 #define CM_INIT_KERNEL_PER_PROGRAM 64 // 160 161 #define CM_MAX_SURFACE3D_FORMAT_COUNT 3 162 163 #define CM_RT_PLATFORM "CM_RT_PLATFORM" 164 #define INCLUDE_GTENVVAR_NAME "CM_DYNGT_INCLUDE" 165 #define CM_RT_SKU "CM_RT_SKU" 166 #define CM_RT_MAX_THREADS "CM_RT_MAX_THREADS" 167 #define CM_RT_AUB_PARAM "CM_RT_AUB_PARAM" 168 #define CM_RT_MUL_FRAME_FILE_BEGIN 0 169 #define CM_RT_MUL_FRAME_FILE_MIDDLE 1 170 #define CM_RT_MUL_FRAME_FILE_END 2 171 172 #define CM_RT_USER_FEATURE_FORCE_COHERENT_STATELESSBTI "ForceCoherentStatelessBTI" 173 174 // need to sync with driver code 175 #define CM_HAL_LOCKFLAG_READONLY 0x00000001 176 #define CM_HAL_LOCKFLAG_WRITEONLY 0x00000002 177 178 #define CM_MAX_DEPENDENCY_COUNT 8 179 #define CM_MAX_THREADSPACE_WIDTH_FOR_MW 511 180 #define CM_MAX_THREADSPACE_HEIGHT_FOR_MW 511 181 #define CM_MAX_THREADSPACE_WIDTH_SKLUP_FOR_MW 2047 182 #define CM_MAX_THREADSPACE_HEIGHT_SKLUP_FOR_MW 2047 183 184 #define MAX_SLM_SIZE_PER_GROUP_IN_1K 64 // 64KB PER Group on Gen7+ 185 #define CM_MAX_THREAD_GROUP 64 186 187 #define COMMON_ISA_NUM_PREDEFINED_SURF_VER_2 1 188 #define COMMON_ISA_NUM_PREDEFINED_SURF_VER_2_1 5 189 #define COMMON_ISA_NUM_PREDEFINED_SURF_VER_3_1 6 190 191 #define CM_FLAG_CURBE_ENABLED 0x00000001 //bit 0 192 #define CM_FLAG_NONSTALLING_SCOREBOARD_ENABLED 0x00000002 //bit 1 193 194 #define GT_PIN_MSG_SIZE 1024 195 196 #define CM_GLOBAL_SURFACE_NUMBER 4 197 #define CM_GTPIN_SURFACE_NUMBER 3 198 199 #define GT_RESERVED_INDEX_START 250 200 #define GT_RESERVED_INDEX_START_GEN9_PLUS 240 201 #define CM_GLOBAL_SURFACE_INDEX_START 243 202 #define CM_GLOBAL_SURFACE_INDEX_START_GEN9_PLUS 1 203 #define CM_NULL_SURFACE_BINDING_INDEX 0 //Reserve 0 for NULL surface 204 205 #define GTPIN_BINDING_TABLE_INDEX_BUFF0_GEN9_PLUS (CM_GLOBAL_SURFACE_INDEX_START_GEN9_PLUS + CM_GLOBAL_SURFACE_NUMBER) 206 #define GTPIN_BINDING_TABLE_INDEX_BUFF1_GEN9_PLUS (GTPIN_BINDING_TABLE_INDEX_BUFF0_GEN9_PLUS + 1) 207 #define GTPIN_BINDING_TABLE_INDEX_BUFF2_GEN9_PLUS (GTPIN_BINDING_TABLE_INDEX_BUFF0_GEN9_PLUS + 2) 208 209 #define CM_NULL_SURFACE 0xFFFF 210 211 #define R64_OFFSET 32*64 212 #define CM_MOVE_INSTRUCTION_SIZE 16 // 16 bytes per move instruction 213 214 #define CM_SAMPLER_MAX_BINDING_INDEX 15 215 216 // For EnqueueWithHints using media objects 217 // hard code add instruction to adjust y coordinate 218 // just need to replace DW3 with constant value 219 // add (1) r0.3<1>:uw r0.3<0;1,0>:uw 0x0:w 220 #define CM_BDW_ADJUST_Y_SCOREBOARD_DW0 0x00000040 221 #define CM_BDW_ADJUST_Y_SCOREBOARD_DW1 0x20061248 222 #define CM_BDW_ADJUST_Y_SCOREBOARD_DW2 0x1e000006 223 224 #define CM_MINIMUM_NUM_KERNELS_ENQWHINTS 2 225 226 #define CM_DEFAULT_PRINT_BUFFER_SIZE (1*1024*1024) // 1M print buffer size 227 #define PRINT_BUFFER_HEADER_SIZE 32 228 #define CM_PRINTF_STATIC_BUFFER_ID 1 229 230 #define CM_INVALID_COLOR_COUNT 0 231 232 #define CM_INIT_GPUCOPY_KERNL_COUNT 16 233 234 #define CM_NUM_VME_HEVC_REFS 4 235 236 #define PLATFORM_INTEL_UNKNOWN 0 237 238 #define PLATFORM_INTEL_GT_UNKNOWN 0 239 #define PLATFORM_INTEL_GT1 1 240 #define PLATFORM_INTEL_GT2 2 241 #define PLATFORM_INTEL_GT3 3 242 #define PLATFORM_INTEL_GT4 4 243 #define PLATFORM_INTEL_GT1_5 10 244 245 #define BDW_GT1_MAX_NUM_SLICES (1) 246 #define BDW_GT1_MAX_NUM_SUBSLICES (2) 247 #define BDW_GT1_5_MAX_NUM_SLICES (1) 248 #define BDW_GT1_5_MAX_NUM_SUBSLICES (3) 249 #define BDW_GT2_MAX_NUM_SLICES (1) 250 #define BDW_GT2_MAX_NUM_SUBSLICES (3) 251 #define BDW_GT3_MAX_NUM_SLICES (2) 252 #define BDW_GT3_MAX_NUM_SUBSLICES (6) 253 254 #define SKL_GT1_MAX_NUM_SLICES (1) 255 #define SKL_GT1_MAX_NUM_SUBSLICES (2) 256 #define SKL_GT1_5_MAX_NUM_SLICES (1) 257 #define SKL_GT1_5_MAX_NUM_SUBSLICES (3) 258 #define SKL_GT2_MAX_NUM_SLICES (1) 259 #define SKL_GT2_MAX_NUM_SUBSLICES (3) 260 #define SKL_GT3_MAX_NUM_SLICES (2) 261 #define SKL_GT3_MAX_NUM_SUBSLICES (6) 262 #define SKL_GT4_MAX_NUM_SLICES (3) 263 #define SKL_GT4_MAX_NUM_SUBSLICES (9) 264 265 #define CNL_GT1_4X8_MAX_NUM_SLICES (2) 266 #define CNL_GT1_4X8_MAX_NUM_SUBSLICES (4) 267 #define CNL_GT2_7X8_MAX_NUM_SLICES (3) 268 #define CNL_GT2_7X8_MAX_NUM_SUBSLICES (7) 269 #define CNL_GT3_9X8_MAX_NUM_SLICES (4) 270 #define CNL_GT3_9_8MAX_NUM_SUBSLICES (9) 271 272 typedef enum _CM_DEVICE_CAP_NAME 273 { 274 CAP_KERNEL_COUNT_PER_TASK, 275 CAP_KERNEL_BINARY_SIZE, 276 CAP_SAMPLER_COUNT , 277 CAP_SAMPLER_COUNT_PER_KERNEL, 278 CAP_BUFFER_COUNT , 279 CAP_SURFACE2D_COUNT, 280 CAP_SURFACE3D_COUNT, 281 CAP_SURFACE_COUNT_PER_KERNEL, 282 CAP_ARG_COUNT_PER_KERNEL, 283 CAP_ARG_SIZE_PER_KERNEL , 284 CAP_USER_DEFINED_THREAD_COUNT_PER_TASK, 285 CAP_HW_THREAD_COUNT, 286 CAP_SURFACE2D_FORMAT_COUNT, 287 CAP_SURFACE2D_FORMATS, 288 CAP_SURFACE3D_FORMAT_COUNT, 289 CAP_SURFACE3D_FORMATS, 290 CAP_VME_STATE_COUNT, 291 CAP_GPU_PLATFORM, 292 CAP_GT_PLATFORM, 293 CAP_MIN_FREQUENCY, 294 CAP_MAX_FREQUENCY, 295 CAP_L3_CONFIG, 296 CAP_GPU_CURRENT_FREQUENCY, 297 CAP_USER_DEFINED_THREAD_COUNT_PER_TASK_NO_THREAD_ARG, 298 CAP_USER_DEFINED_THREAD_COUNT_PER_MEDIA_WALKER, 299 CAP_USER_DEFINED_THREAD_COUNT_PER_THREAD_GROUP, 300 CAP_SURFACE2DUP_COUNT, 301 CAP_PLATFORM_INFO, 302 CAP_MAX_BUFFER_SIZE 303 } CM_DEVICE_CAP_NAME; 304 305 // BDW stepping sequence: // A0 306 // HSW stepping sequence: // A0, A1, B0, C0, D0 307 #define HW_GT_STEPPING_A0 "A0" 308 #define HW_GT_STEPPING_A1 "A1" 309 #define HW_GT_STEPPING_B0 "B0" 310 #define HW_GT_STEPPING_C0 "C0" 311 #define HW_GT_STEPPING_D0 "D0" 312 313 /**************** L3/Cache ***************/ 314 typedef enum _MEMORY_OBJECT_CONTROL{ 315 // SNB 316 MEMORY_OBJECT_CONTROL_USE_GTT_ENTRY, 317 MEMORY_OBJECT_CONTROL_NEITHER_LLC_NOR_MLC, 318 MEMORY_OBJECT_CONTROL_LLC_NOT_MLC, 319 MEMORY_OBJECT_CONTROL_LLC_AND_MLC, 320 321 // IVB 322 MEMORY_OBJECT_CONTROL_FROM_GTT_ENTRY = MEMORY_OBJECT_CONTROL_USE_GTT_ENTRY, // Caching dependent on pte 323 MEMORY_OBJECT_CONTROL_L3, // Cached in L3$ 324 MEMORY_OBJECT_CONTROL_LLC, // Cached in LLC 325 MEMORY_OBJECT_CONTROL_LLC_L3, // Cached in LLC & L3$ 326 327 // HSW 328 MEMORY_OBJECT_CONTROL_USE_PTE = MEMORY_OBJECT_CONTROL_FROM_GTT_ENTRY, // Caching dependent on pte 329 MEMORY_OBJECT_CONTROL_L3_USE_PTE, 330 MEMORY_OBJECT_CONTROL_UC, // Uncached 331 MEMORY_OBJECT_CONTROL_L3_UC, 332 MEMORY_OBJECT_CONTROL_LLC_ELLC, 333 MEMORY_OBJECT_CONTROL_L3_LLC_ELLC, 334 MEMORY_OBJECT_CONTROL_ELLC, 335 MEMORY_OBJECT_CONTROL_L3_ELLC, 336 337 // BDW 338 MEMORY_OBJECT_CONTROL_BDW_ELLC_ONLY = 0, 339 MEMORY_OBJECT_CONTROL_BDW_LLC_ONLY, 340 MEMORY_OBJECT_CONTROL_BDW_LLC_ELLC_ALLOWED, 341 MEMORY_OBJECT_CONTROL_BDW_L3_LLC_ELLC_ALLOWED, 342 343 // SKL 344 // CNL 345 // ICL 346 MEMORY_OBJECT_CONTROL_SKL_DEFAULT = 0, 347 MEMORY_OBJECT_CONTROL_SKL_NO_L3, 348 MEMORY_OBJECT_CONTROL_SKL_NO_LLC_ELLC, 349 MEMORY_OBJECT_CONTROL_SKL_NO_LLC, 350 MEMORY_OBJECT_CONTROL_SKL_NO_ELLC, 351 MEMORY_OBJECT_CONTROL_SKL_NO_LLC_L3, 352 MEMORY_OBJECT_CONTROL_SKL_NO_ELLC_L3, 353 MEMORY_OBJECT_CONTROL_SKL_NO_CACHE, 354 355 // Unified memory object control type for SKL+ 356 MEMORY_OBJECT_CONTROL_DEFAULT = 0x0, 357 MEMORY_OBJECT_CONTROL_NO_L3, 358 MEMORY_OBJECT_CONTROL_NO_LLC_ELLC, 359 MEMORY_OBJECT_CONTROL_NO_LLC, 360 MEMORY_OBJECT_CONTROL_NO_ELLC, 361 MEMORY_OBJECT_CONTROL_NO_LLC_L3, 362 MEMORY_OBJECT_CONTROL_NO_ELLC_L3, 363 MEMORY_OBJECT_CONTROL_NO_CACHE, 364 MEMORY_OBJECT_CONTROL_L1_ENABLED, 365 366 MEMORY_OBJECT_CONTROL_TOTAL, 367 // 368 MEMORY_OBJECT_CONTROL_UNKNOW = 0xff 369 } MEMORY_OBJECT_CONTROL; 370 371 typedef enum _MEMORY_TYPE { 372 CM_USE_PTE, 373 CM_UN_CACHEABLE, 374 CM_WRITE_THROUGH, 375 CM_WRITE_BACK, 376 377 // BDW 378 MEMORY_TYPE_BDW_UC_WITH_FENCE = 0, 379 MEMORY_TYPE_BDW_UC, 380 MEMORY_TYPE_BDW_WT, 381 MEMORY_TYPE_BDW_WB 382 383 } MEMORY_TYPE; 384 385 typedef struct _CM_SURFACE_MEM_OBJ_CTRL { 386 int32_t mem_ctrl; 387 MEMORY_TYPE mem_type; 388 int32_t age; 389 } CM_SURFACE_MEM_OBJ_CTRL; 390 391 //GT-PIN 392 #define CM_MAX_ENTRY_FOR_A_SURFACE 6 //maxium planes(3)*dual state(2) 393 #define CM_GTPIN_BUFFER_NUM 3 394 395 typedef enum _CM_SAMPLER8x8_SURFACE_ 396 { 397 CM_AVS_SURFACE = 0, 398 CM_VA_SURFACE = 1 399 }CM_SAMPLER8x8_SURFACE; 400 401 typedef enum _CM_SURFACE_ADDRESS_CONTROL_MODE_ 402 { 403 CM_SURFACE_CLAMP = 0, 404 CM_SURFACE_MIRROR = 1 405 }CM_SURFACE_ADDRESS_CONTROL_MODE; 406 407 typedef struct _CM_SAMPLER_STATE 408 { 409 CM_TEXTURE_FILTER_TYPE minFilterType; 410 CM_TEXTURE_FILTER_TYPE magFilterType; 411 CM_TEXTURE_ADDRESS_TYPE addressU; 412 CM_TEXTURE_ADDRESS_TYPE addressV; 413 CM_TEXTURE_ADDRESS_TYPE addressW; 414 } CM_SAMPLER_STATE; 415 416 typedef enum _CM_PIXEL_TYPE 417 { 418 CM_PIXEL_UINT, 419 CM_PIXEL_SINT, 420 CM_PIXEL_OTHER 421 } CM_PIXEL_TYPE; 422 423 typedef struct _CM_SAMPLER_STATE_EX 424 { 425 CM_TEXTURE_FILTER_TYPE minFilterType; 426 CM_TEXTURE_FILTER_TYPE magFilterType; 427 CM_TEXTURE_ADDRESS_TYPE addressU; 428 CM_TEXTURE_ADDRESS_TYPE addressV; 429 CM_TEXTURE_ADDRESS_TYPE addressW; 430 431 CM_PIXEL_TYPE SurfaceFormat; 432 union { 433 uint32_t BorderColorRedU; 434 int32_t BorderColorRedS; 435 float BorderColorRedF; 436 }; 437 438 union { 439 uint32_t BorderColorGreenU; 440 int32_t BorderColorGreenS; 441 float BorderColorGreenF; 442 }; 443 444 union { 445 uint32_t BorderColorBlueU; 446 int32_t BorderColorBlueS; 447 float BorderColorBlueF; 448 }; 449 450 union { 451 uint32_t BorderColorAlphaU; 452 int32_t BorderColorAlphaS; 453 float BorderColorAlphaF; 454 }; 455 } CM_SAMPLER_STATE_EX; 456 457 typedef struct _CM_AVS_INTERNEL_COEFF_TABLE{ 458 float FilterCoeff_0_0; 459 float FilterCoeff_0_1; 460 float FilterCoeff_0_2; 461 float FilterCoeff_0_3; 462 float FilterCoeff_0_4; 463 float FilterCoeff_0_5; 464 float FilterCoeff_0_6; 465 float FilterCoeff_0_7; 466 }CM_AVS_INTERNEL_COEFF_TABLE; 467 468 #define CM_NUM_COEFF_ROWS 17 469 #define CM_NUM_COEFF_ROWS_SKL 32 470 471 typedef struct _CM_AVS_NONPIPLINED_STATE{ 472 bool BypassXAF; 473 bool BypassYAF; 474 uint8_t DefaultSharpLvl; 475 uint8_t maxDerivative4Pixels; 476 uint8_t maxDerivative8Pixels; 477 uint8_t transitionArea4Pixels; 478 uint8_t transitionArea8Pixels; 479 CM_AVS_COEFF_TABLE Tbl0X[ CM_NUM_COEFF_ROWS_SKL ]; 480 CM_AVS_COEFF_TABLE Tbl0Y[ CM_NUM_COEFF_ROWS_SKL ]; 481 CM_AVS_COEFF_TABLE Tbl1X[ CM_NUM_COEFF_ROWS_SKL ]; 482 CM_AVS_COEFF_TABLE Tbl1Y[ CM_NUM_COEFF_ROWS_SKL ]; 483 bool bEnableRGBAdaptive; 484 bool bAdaptiveFilterAllChannels; 485 }CM_AVS_NONPIPLINED_STATE; 486 487 typedef struct _CM_AVS_INTERNEL_NONPIPLINED_STATE{ 488 bool BypassXAF; 489 bool BypassYAF; 490 uint8_t DefaultSharpLvl; 491 uint8_t maxDerivative4Pixels; 492 uint8_t maxDerivative8Pixels; 493 uint8_t transitionArea4Pixels; 494 uint8_t transitionArea8Pixels; 495 CM_AVS_INTERNEL_COEFF_TABLE Tbl0X[ CM_NUM_COEFF_ROWS_SKL ]; 496 CM_AVS_INTERNEL_COEFF_TABLE Tbl0Y[ CM_NUM_COEFF_ROWS_SKL ]; 497 CM_AVS_INTERNEL_COEFF_TABLE Tbl1X[ CM_NUM_COEFF_ROWS_SKL ]; 498 CM_AVS_INTERNEL_COEFF_TABLE Tbl1Y[ CM_NUM_COEFF_ROWS_SKL ]; 499 bool bEnableRGBAdaptive; 500 bool bAdaptiveFilterAllChannels; 501 }CM_AVS_INTERNEL_NONPIPLINED_STATE, *PCM_AVS_INTERNEL_NONPIPLINED_STATE; 502 503 typedef struct _CM_AVS_STATE_MSG{ 504 bool AVSTYPE; //true nearest, false adaptive 505 bool EightTapAFEnable; //HSW+ 506 bool BypassIEF; //ignored for BWL, moved to sampler8x8 payload. 507 bool ShuffleOutputWriteback; //SKL mode only to be set when AVS msg sequence is 4x4 or 8x4 508 bool HDCDirectWriteEnable; 509 unsigned short GainFactor; 510 unsigned char GlobalNoiseEstm; 511 unsigned char StrongEdgeThr; 512 unsigned char WeakEdgeThr; 513 unsigned char StrongEdgeWght; 514 unsigned char RegularWght; 515 unsigned char NonEdgeWght; 516 unsigned short wR3xCoefficient; 517 unsigned short wR3cCoefficient; 518 unsigned short wR5xCoefficient; 519 unsigned short wR5cxCoefficient; 520 unsigned short wR5cCoefficient; 521 //For Non-piplined states 522 unsigned short stateID; 523 CM_AVS_NONPIPLINED_STATE * AvsState; 524 } CM_AVS_STATE_MSG; 525 526 /* 527 * CONVOLVE STATE DATA STRUCTURES 528 */ 529 typedef struct _CM_CONVOLVE_COEFF_TABLE{ 530 float FilterCoeff_0_0; 531 float FilterCoeff_0_1; 532 float FilterCoeff_0_2; 533 float FilterCoeff_0_3; 534 float FilterCoeff_0_4; 535 float FilterCoeff_0_5; 536 float FilterCoeff_0_6; 537 float FilterCoeff_0_7; 538 float FilterCoeff_0_8; 539 float FilterCoeff_0_9; 540 float FilterCoeff_0_10; 541 float FilterCoeff_0_11; 542 float FilterCoeff_0_12; 543 float FilterCoeff_0_13; 544 float FilterCoeff_0_14; 545 float FilterCoeff_0_15; 546 float FilterCoeff_0_16; 547 float FilterCoeff_0_17; 548 float FilterCoeff_0_18; 549 float FilterCoeff_0_19; 550 float FilterCoeff_0_20; 551 float FilterCoeff_0_21; 552 float FilterCoeff_0_22; 553 float FilterCoeff_0_23; 554 float FilterCoeff_0_24; 555 float FilterCoeff_0_25; 556 float FilterCoeff_0_26; 557 float FilterCoeff_0_27; 558 float FilterCoeff_0_28; 559 float FilterCoeff_0_29; 560 float FilterCoeff_0_30; 561 float FilterCoeff_0_31; 562 }CM_CONVOLVE_COEFF_TABLE; 563 564 #define CM_NUM_CONVOLVE_ROWS_SKL 31 565 typedef struct _CM_CONVOLVE_STATE_MSG{ 566 bool CoeffSize; //true 16-bit, false 8-bit 567 int8_t SclDwnValue; //Scale down value 568 int8_t Width; //Kernel Width 569 int8_t Height; //Kernel Height 570 //SKL mode 571 bool isVertical32Mode; 572 bool isHorizontal32Mode; 573 bool skl_mode; // new added 574 CM_CONVOLVE_SKL_TYPE nConvolveType; 575 CM_CONVOLVE_COEFF_TABLE Table[ CM_NUM_CONVOLVE_ROWS_SKL ]; 576 } CM_CONVOLVE_STATE_MSG; 577 578 /* 579 * MISC SAMPLER8x8 State 580 */ 581 typedef struct _CM_MISC_STATE { 582 //uint32_t 0 583 union{ 584 struct{ 585 uint32_t Row0 : 16; 586 uint32_t Reserved : 8; 587 uint32_t Width : 4; 588 uint32_t Height : 4; 589 }; 590 struct{ 591 uint32_t value; 592 }; 593 }DW0; 594 595 //uint32_t 1 596 union{ 597 struct{ 598 uint32_t Row1 : 16; 599 uint32_t Row2 : 16; 600 }; 601 struct{ 602 uint32_t value; 603 }; 604 }DW1; 605 606 //uint32_t 2 607 union{ 608 struct{ 609 uint32_t Row3 : 16; 610 uint32_t Row4 : 16; 611 }; 612 struct{ 613 uint32_t value; 614 }; 615 }DW2; 616 617 //uint32_t 3 618 union{ 619 struct{ 620 uint32_t Row5 : 16; 621 uint32_t Row6 : 16; 622 }; 623 struct{ 624 uint32_t value; 625 }; 626 }DW3; 627 628 //uint32_t 4 629 union{ 630 struct{ 631 uint32_t Row7 : 16; 632 uint32_t Row8 : 16; 633 }; 634 struct{ 635 uint32_t value; 636 }; 637 }DW4; 638 639 //uint32_t 5 640 union{ 641 struct{ 642 uint32_t Row9 : 16; 643 uint32_t Row10 : 16; 644 }; 645 struct{ 646 uint32_t value; 647 }; 648 }DW5; 649 650 //uint32_t 6 651 union{ 652 struct{ 653 uint32_t Row11 : 16; 654 uint32_t Row12 : 16; 655 }; 656 struct{ 657 uint32_t value; 658 }; 659 }DW6; 660 661 //uint32_t 7 662 union{ 663 struct{ 664 uint32_t Row13 : 16; 665 uint32_t Row14 : 16; 666 }; 667 struct{ 668 uint32_t value; 669 }; 670 }DW7; 671 } CM_MISC_STATE; 672 673 typedef struct _CM_MISC_STATE_MSG{ 674 //uint32_t 0 675 union{ 676 struct{ 677 uint32_t Row0 : 16; 678 uint32_t Reserved : 8; 679 uint32_t Width : 4; 680 uint32_t Height : 4; 681 }; 682 struct{ 683 uint32_t value; 684 }; 685 }DW0; 686 687 //uint32_t 1 688 union{ 689 struct{ 690 uint32_t Row1 : 16; 691 uint32_t Row2 : 16; 692 }; 693 struct{ 694 uint32_t value; 695 }; 696 }DW1; 697 698 //uint32_t 2 699 union{ 700 struct{ 701 uint32_t Row3 : 16; 702 uint32_t Row4 : 16; 703 }; 704 struct{ 705 uint32_t value; 706 }; 707 }DW2; 708 709 //uint32_t 3 710 union{ 711 struct{ 712 uint32_t Row5 : 16; 713 uint32_t Row6 : 16; 714 }; 715 struct{ 716 uint32_t value; 717 }; 718 }DW3; 719 720 //uint32_t 4 721 union{ 722 struct{ 723 uint32_t Row7 : 16; 724 uint32_t Row8 : 16; 725 }; 726 struct{ 727 uint32_t value; 728 }; 729 }DW4; 730 731 //uint32_t 5 732 union{ 733 struct{ 734 uint32_t Row9 : 16; 735 uint32_t Row10 : 16; 736 }; 737 struct{ 738 uint32_t value; 739 }; 740 }DW5; 741 742 //uint32_t 6 743 union{ 744 struct{ 745 uint32_t Row11 : 16; 746 uint32_t Row12 : 16; 747 }; 748 struct{ 749 uint32_t value; 750 }; 751 }DW6; 752 753 //uint32_t 7 754 union{ 755 struct{ 756 uint32_t Row13 : 16; 757 uint32_t Row14 : 16; 758 }; 759 struct{ 760 uint32_t value; 761 }; 762 }DW7; 763 } CM_MISC_STATE_MSG; 764 765 typedef CM_HAL_SAMPLER_8X8_TYPE CM_SAMPLER_STATE_TYPE; 766 767 typedef struct _CM_SAMPLER_8X8_DESCR{ 768 CM_SAMPLER_STATE_TYPE stateType; 769 union 770 { 771 CM_AVS_STATE_MSG * avs; 772 CM_CONVOLVE_STATE_MSG * conv; 773 CM_MISC_STATE_MSG * misc; //ERODE/DILATE/MINMAX 774 }; 775 } CM_SAMPLER_8X8_DESCR; 776 777 typedef enum _CM_ROTATION 778 { 779 CM_ROTATION_IDENTITY = 0, //!< Rotation 0 degrees 780 CM_ROTATION_90, //!< Rotation 90 degrees 781 CM_ROTATION_180, //!< Rotation 180 degrees 782 CM_ROTATION_270, //!< Rotation 270 degrees 783 } CM_ROTATION; 784 785 // to support new flag with current API 786 // new flag/field could be add to the end of this structure 787 // 788 struct CM_FLAG { 789 CM_FLAG(); 790 CM_ROTATION rotationFlag; 791 int32_t chromaSiting; 792 }; 793 794 // parameters used to set the surface state of the CmSurface 795 struct CM_VME_SURFACE_STATE_PARAM 796 { 797 uint32_t width; 798 uint32_t height; 799 }; 800 801 // parameters used to set the surface state of the CmSurface 802 typedef struct _CM_SURFACE2D_STATE_PARAM 803 { 804 uint32_t format; //[IN] MOS_FORMAT 805 uint32_t width; 806 uint32_t height; 807 uint32_t depth; 808 uint32_t pitch; 809 uint16_t memory_object_control; 810 uint32_t surface_x_offset; // Horizontal offset to the origin of the surface, in columns of pixels. 811 uint32_t surface_y_offset; // Vertical offset to the origin of the surface, in rows of pixels. 812 uint32_t surface_offset; // Offset to the origin of the surface, in bytes. 813 uint32_t reserved[3]; // for future usage 814 } CM_SURFACE2D_STATE_PARAM; 815 816 #endif // #ifndef MEDIADRIVER_AGNOSTIC_COMMON_CM_CMDEF_H_ 817