1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CACHE_LINE_SIZE if OF 9 select ARCH_HAS_CPU_CACHE_ALIASING 10 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 11 select ARCH_HAS_CRC32 if KERNEL_MODE_NEON 12 select ARCH_HAS_CRC_T10DIF if KERNEL_MODE_NEON 13 select ARCH_HAS_CURRENT_STACK_POINTER 14 select ARCH_HAS_DEBUG_VIRTUAL if MMU 15 select ARCH_HAS_DMA_ALLOC if MMU 16 select ARCH_HAS_DMA_OPS 17 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 18 select ARCH_HAS_ELF_RANDOMIZE 19 select ARCH_HAS_FORTIFY_SOURCE 20 select ARCH_HAS_KEEPINITRD 21 select ARCH_HAS_KCOV 22 select ARCH_HAS_MEMBARRIER_SYNC_CORE 23 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 24 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 25 select ARCH_HAS_SETUP_DMA_OPS 26 select ARCH_HAS_SET_MEMORY 27 select ARCH_STACKWALK 28 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 29 select ARCH_HAS_STRICT_MODULE_RWX if MMU 30 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 31 select ARCH_HAS_SYNC_DMA_FOR_CPU 32 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 33 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 34 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 35 select ARCH_HAS_GCOV_PROFILE_ALL 36 select ARCH_KEEP_MEMBLOCK 37 select ARCH_HAS_UBSAN 38 select ARCH_MIGHT_HAVE_PC_PARPORT 39 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 40 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 41 select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6 42 select ARCH_SUPPORTS_ATOMIC_RMW 43 select ARCH_SUPPORTS_CFI_CLANG 44 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 45 select ARCH_SUPPORTS_PER_VMA_LOCK 46 select ARCH_USE_BUILTIN_BSWAP 47 select ARCH_USE_CMPXCHG_LOCKREF 48 select ARCH_USE_MEMTEST 49 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 50 select ARCH_WANT_GENERAL_HUGETLB 51 select ARCH_WANT_IPC_PARSE_VERSION 52 select ARCH_WANT_LD_ORPHAN_WARN 53 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 54 select BUILDTIME_TABLE_SORT if MMU 55 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 56 select CLONE_BACKWARDS 57 select CPU_PM if SUSPEND || CPU_IDLE 58 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 59 select DMA_DECLARE_COHERENT 60 select DMA_GLOBAL_POOL if !MMU 61 select DMA_NONCOHERENT_MMAP if MMU 62 select EDAC_SUPPORT 63 select EDAC_ATOMIC_SCRUB 64 select GENERIC_ALLOCATOR 65 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 66 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 67 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 68 select GENERIC_IRQ_IPI if SMP 69 select GENERIC_CPU_AUTOPROBE 70 select GENERIC_CPU_DEVICES 71 select GENERIC_EARLY_IOREMAP 72 select GENERIC_IDLE_POLL_SETUP 73 select GENERIC_IRQ_MULTI_HANDLER 74 select GENERIC_IRQ_PROBE 75 select GENERIC_IRQ_SHOW 76 select GENERIC_IRQ_SHOW_LEVEL 77 select GENERIC_LIB_DEVMEM_IS_ALLOWED 78 select GENERIC_PCI_IOMAP 79 select GENERIC_SCHED_CLOCK 80 select GENERIC_SMP_IDLE_THREAD 81 select HARDIRQS_SW_RESEND 82 select HAS_IOPORT 83 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 84 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 85 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 86 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 87 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 88 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 89 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 90 select HAVE_ARCH_MMAP_RND_BITS if MMU 91 select HAVE_ARCH_PFN_VALID 92 select HAVE_ARCH_SECCOMP 93 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 94 select HAVE_ARCH_STACKLEAK 95 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 96 select HAVE_ARCH_TRACEHOOK 97 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 98 select HAVE_ARM_SMCCC if CPU_V7 99 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 100 select HAVE_CONTEXT_TRACKING_USER 101 select HAVE_C_RECORDMCOUNT 102 select HAVE_BUILDTIME_MCOUNT_SORT 103 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 104 select HAVE_DMA_CONTIGUOUS if MMU 105 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 106 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 107 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 108 select HAVE_EXIT_THREAD 109 select HAVE_GUP_FAST if ARM_LPAE 110 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 111 select HAVE_FUNCTION_ERROR_INJECTION 112 select HAVE_FUNCTION_GRAPH_TRACER 113 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 114 select HAVE_GCC_PLUGINS 115 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 116 select HAVE_IRQ_TIME_ACCOUNTING 117 select HAVE_KERNEL_GZIP 118 select HAVE_KERNEL_LZ4 119 select HAVE_KERNEL_LZMA 120 select HAVE_KERNEL_LZO 121 select HAVE_KERNEL_XZ 122 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 123 select HAVE_KRETPROBES if HAVE_KPROBES 124 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_CAN_USE_KEEP_IN_OVERLAY) 125 select HAVE_MOD_ARCH_SPECIFIC 126 select HAVE_NMI 127 select HAVE_OPTPROBES if !THUMB2_KERNEL 128 select HAVE_PAGE_SIZE_4KB 129 select HAVE_PCI if MMU 130 select HAVE_PERF_EVENTS 131 select HAVE_PERF_REGS 132 select HAVE_PERF_USER_STACK_DUMP 133 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 134 select HAVE_REGS_AND_STACK_ACCESS_API 135 select HAVE_RSEQ 136 select HAVE_STACKPROTECTOR 137 select HAVE_SYSCALL_TRACEPOINTS 138 select HAVE_UID16 139 select HAVE_VIRT_CPU_ACCOUNTING_GEN 140 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 141 select IRQ_FORCED_THREADING 142 select LOCK_MM_AND_FIND_VMA 143 select MODULES_USE_ELF_REL 144 select NEED_DMA_MAP_STATE 145 select OF_EARLY_FLATTREE if OF 146 select OLD_SIGACTION 147 select OLD_SIGSUSPEND3 148 select PCI_DOMAINS_GENERIC if PCI 149 select PCI_SYSCALL if PCI 150 select PERF_USE_VMALLOC 151 select RTC_LIB 152 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 153 select SYS_SUPPORTS_APM_EMULATION 154 select THREAD_INFO_IN_TASK 155 select TIMER_OF if OF 156 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 157 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 158 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 159 # Above selects are sorted alphabetically; please add new ones 160 # according to that. Thanks. 161 help 162 The ARM series is a line of low-power-consumption RISC chip designs 163 licensed by ARM Ltd and targeted at embedded applications and 164 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 165 manufactured, but legacy ARM-based PC hardware remains popular in 166 Europe. There is an ARM Linux project with a web page at 167 <http://www.arm.linux.org.uk/>. 168 169config ARM_HAS_GROUP_RELOCS 170 def_bool y 171 depends on !LD_IS_LLD || LLD_VERSION >= 140000 172 depends on !COMPILE_TEST 173 help 174 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 175 relocations, which have been around for a long time, but were not 176 supported in LLD until version 14. The combined range is -/+ 256 MiB, 177 which is usually sufficient, but not for allyesconfig, so we disable 178 this feature when doing compile testing. 179 180config ARM_DMA_USE_IOMMU 181 bool 182 select NEED_SG_DMA_LENGTH 183 184if ARM_DMA_USE_IOMMU 185 186config ARM_DMA_IOMMU_ALIGNMENT 187 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 188 range 4 9 189 default 8 190 help 191 DMA mapping framework by default aligns all buffers to the smallest 192 PAGE_SIZE order which is greater than or equal to the requested buffer 193 size. This works well for buffers up to a few hundreds kilobytes, but 194 for larger buffers it just a waste of address space. Drivers which has 195 relatively small addressing window (like 64Mib) might run out of 196 virtual space with just a few allocations. 197 198 With this parameter you can specify the maximum PAGE_SIZE order for 199 DMA IOMMU buffers. Larger buffers will be aligned only to this 200 specified order. The order is expressed as a power of two multiplied 201 by the PAGE_SIZE. 202 203endif 204 205config SYS_SUPPORTS_APM_EMULATION 206 bool 207 208config HAVE_TCM 209 bool 210 select GENERIC_ALLOCATOR 211 212config HAVE_PROC_CPU 213 bool 214 215config NO_IOPORT_MAP 216 bool 217 218config SBUS 219 bool 220 221config STACKTRACE_SUPPORT 222 bool 223 default y 224 225config LOCKDEP_SUPPORT 226 bool 227 default y 228 229config ARCH_HAS_ILOG2_U32 230 bool 231 232config ARCH_HAS_ILOG2_U64 233 bool 234 235config ARCH_HAS_BANDGAP 236 bool 237 238config FIX_EARLYCON_MEM 239 def_bool y if MMU 240 241config GENERIC_HWEIGHT 242 bool 243 default y 244 245config GENERIC_CALIBRATE_DELAY 246 bool 247 default y 248 249config ARCH_MAY_HAVE_PC_FDC 250 bool 251 252config ARCH_SUPPORTS_UPROBES 253 def_bool y 254 255config GENERIC_ISA_DMA 256 bool 257 258config FIQ 259 bool 260 261config ARCH_MTD_XIP 262 bool 263 264config ARM_PATCH_PHYS_VIRT 265 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 266 default y 267 depends on MMU 268 help 269 Patch phys-to-virt and virt-to-phys translation functions at 270 boot and module load time according to the position of the 271 kernel in system memory. 272 273 This can only be used with non-XIP MMU kernels where the base 274 of physical memory is at a 2 MiB boundary. 275 276 Only disable this option if you know that you do not require 277 this feature (eg, building a kernel for a single machine) and 278 you need to shrink the kernel to the minimal size. 279 280config NEED_MACH_IO_H 281 bool 282 help 283 Select this when mach/io.h is required to provide special 284 definitions for this platform. The need for mach/io.h should 285 be avoided when possible. 286 287config NEED_MACH_MEMORY_H 288 bool 289 help 290 Select this when mach/memory.h is required to provide special 291 definitions for this platform. The need for mach/memory.h should 292 be avoided when possible. 293 294config PHYS_OFFSET 295 hex "Physical address of main memory" if MMU 296 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 297 default DRAM_BASE if !MMU 298 default 0x00000000 if ARCH_FOOTBRIDGE 299 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 300 default 0xa0000000 if ARCH_PXA 301 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 302 default 0 303 help 304 Please provide the physical address corresponding to the 305 location of main memory in your system. 306 307config GENERIC_BUG 308 def_bool y 309 depends on BUG 310 311config PGTABLE_LEVELS 312 int 313 default 3 if ARM_LPAE 314 default 2 315 316menu "System Type" 317 318config MMU 319 bool "MMU-based Paged Memory Management Support" 320 default y 321 help 322 Select if you want MMU-based virtualised addressing space 323 support by paged memory management. If unsure, say 'Y'. 324 325config ARM_SINGLE_ARMV7M 326 def_bool !MMU 327 select ARM_NVIC 328 select CPU_V7M 329 select NO_IOPORT_MAP 330 331config ARCH_MMAP_RND_BITS_MIN 332 default 8 333 334config ARCH_MMAP_RND_BITS_MAX 335 default 14 if PAGE_OFFSET=0x40000000 336 default 15 if PAGE_OFFSET=0x80000000 337 default 16 338 339config ARCH_MULTIPLATFORM 340 bool "Require kernel to be portable to multiple machines" if EXPERT 341 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 342 default y 343 help 344 In general, all Arm machines can be supported in a single 345 kernel image, covering either Armv4/v5 or Armv6/v7. 346 347 However, some configuration options require hardcoding machine 348 specific physical addresses or enable errata workarounds that may 349 break other machines. 350 351 Selecting N here allows using those options, including 352 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 353 354source "arch/arm/Kconfig.platforms" 355 356# 357# This is sorted alphabetically by mach-* pathname. However, plat-* 358# Kconfigs may be included either alphabetically (according to the 359# plat- suffix) or along side the corresponding mach-* source. 360# 361source "arch/arm/mach-actions/Kconfig" 362 363source "arch/arm/mach-alpine/Kconfig" 364 365source "arch/arm/mach-artpec/Kconfig" 366 367source "arch/arm/mach-aspeed/Kconfig" 368 369source "arch/arm/mach-at91/Kconfig" 370 371source "arch/arm/mach-axxia/Kconfig" 372 373source "arch/arm/mach-bcm/Kconfig" 374 375source "arch/arm/mach-berlin/Kconfig" 376 377source "arch/arm/mach-clps711x/Kconfig" 378 379source "arch/arm/mach-davinci/Kconfig" 380 381source "arch/arm/mach-digicolor/Kconfig" 382 383source "arch/arm/mach-dove/Kconfig" 384 385source "arch/arm/mach-ep93xx/Kconfig" 386 387source "arch/arm/mach-exynos/Kconfig" 388 389source "arch/arm/mach-footbridge/Kconfig" 390 391source "arch/arm/mach-gemini/Kconfig" 392 393source "arch/arm/mach-highbank/Kconfig" 394 395source "arch/arm/mach-hisi/Kconfig" 396 397source "arch/arm/mach-hpe/Kconfig" 398 399source "arch/arm/mach-imx/Kconfig" 400 401source "arch/arm/mach-ixp4xx/Kconfig" 402 403source "arch/arm/mach-keystone/Kconfig" 404 405source "arch/arm/mach-lpc32xx/Kconfig" 406 407source "arch/arm/mach-mediatek/Kconfig" 408 409source "arch/arm/mach-meson/Kconfig" 410 411source "arch/arm/mach-milbeaut/Kconfig" 412 413source "arch/arm/mach-mmp/Kconfig" 414 415source "arch/arm/mach-mstar/Kconfig" 416 417source "arch/arm/mach-mv78xx0/Kconfig" 418 419source "arch/arm/mach-mvebu/Kconfig" 420 421source "arch/arm/mach-mxs/Kconfig" 422 423source "arch/arm/mach-nomadik/Kconfig" 424 425source "arch/arm/mach-npcm/Kconfig" 426 427source "arch/arm/mach-omap1/Kconfig" 428 429source "arch/arm/mach-omap2/Kconfig" 430 431source "arch/arm/mach-orion5x/Kconfig" 432 433source "arch/arm/mach-pxa/Kconfig" 434 435source "arch/arm/mach-qcom/Kconfig" 436 437source "arch/arm/mach-realtek/Kconfig" 438 439source "arch/arm/mach-rpc/Kconfig" 440 441source "arch/arm/mach-rockchip/Kconfig" 442 443source "arch/arm/mach-s3c/Kconfig" 444 445source "arch/arm/mach-s5pv210/Kconfig" 446 447source "arch/arm/mach-sa1100/Kconfig" 448 449source "arch/arm/mach-shmobile/Kconfig" 450 451source "arch/arm/mach-socfpga/Kconfig" 452 453source "arch/arm/mach-spear/Kconfig" 454 455source "arch/arm/mach-sti/Kconfig" 456 457source "arch/arm/mach-stm32/Kconfig" 458 459source "arch/arm/mach-sunxi/Kconfig" 460 461source "arch/arm/mach-tegra/Kconfig" 462 463source "arch/arm/mach-ux500/Kconfig" 464 465source "arch/arm/mach-versatile/Kconfig" 466 467source "arch/arm/mach-vt8500/Kconfig" 468 469source "arch/arm/mach-zynq/Kconfig" 470 471# ARMv7-M architecture 472config ARCH_LPC18XX 473 bool "NXP LPC18xx/LPC43xx" 474 depends on ARM_SINGLE_ARMV7M 475 select ARCH_HAS_RESET_CONTROLLER 476 select ARM_AMBA 477 select CLKSRC_LPC32XX 478 select PINCTRL 479 help 480 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 481 high performance microcontrollers. 482 483config ARCH_MPS2 484 bool "ARM MPS2 platform" 485 depends on ARM_SINGLE_ARMV7M 486 select ARM_AMBA 487 select CLKSRC_MPS2 488 help 489 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 490 with a range of available cores like Cortex-M3/M4/M7. 491 492 Please, note that depends which Application Note is used memory map 493 for the platform may vary, so adjustment of RAM base might be needed. 494 495# Definitions to make life easier 496config ARCH_ACORN 497 bool 498 499config PLAT_ORION 500 bool 501 select CLKSRC_MMIO 502 select GENERIC_IRQ_CHIP 503 select IRQ_DOMAIN 504 505config PLAT_ORION_LEGACY 506 bool 507 select PLAT_ORION 508 509config PLAT_VERSATILE 510 bool 511 512source "arch/arm/mm/Kconfig" 513 514config IWMMXT 515 bool "Enable iWMMXt support" 516 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK 517 default y if PXA27x || PXA3xx || ARCH_MMP 518 help 519 Enable support for iWMMXt context switching at run time if 520 running on a CPU that supports it. 521 522if !MMU 523source "arch/arm/Kconfig-nommu" 524endif 525 526config PJ4B_ERRATA_4742 527 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 528 depends on CPU_PJ4B && MACH_ARMADA_370 529 default y 530 help 531 When coming out of either a Wait for Interrupt (WFI) or a Wait for 532 Event (WFE) IDLE states, a specific timing sensitivity exists between 533 the retiring WFI/WFE instructions and the newly issued subsequent 534 instructions. This sensitivity can result in a CPU hang scenario. 535 Workaround: 536 The software must insert either a Data Synchronization Barrier (DSB) 537 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 538 instruction 539 540config ARM_ERRATA_326103 541 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 542 depends on CPU_V6 543 help 544 Executing a SWP instruction to read-only memory does not set bit 11 545 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 546 treat the access as a read, preventing a COW from occurring and 547 causing the faulting task to livelock. 548 549config ARM_ERRATA_411920 550 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 551 depends on CPU_V6 || CPU_V6K 552 help 553 Invalidation of the Instruction Cache operation can 554 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 555 It does not affect the MPCore. This option enables the ARM Ltd. 556 recommended workaround. 557 558config ARM_ERRATA_430973 559 bool "ARM errata: Stale prediction on replaced interworking branch" 560 depends on CPU_V7 561 help 562 This option enables the workaround for the 430973 Cortex-A8 563 r1p* erratum. If a code sequence containing an ARM/Thumb 564 interworking branch is replaced with another code sequence at the 565 same virtual address, whether due to self-modifying code or virtual 566 to physical address re-mapping, Cortex-A8 does not recover from the 567 stale interworking branch prediction. This results in Cortex-A8 568 executing the new code sequence in the incorrect ARM or Thumb state. 569 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 570 and also flushes the branch target cache at every context switch. 571 Note that setting specific bits in the ACTLR register may not be 572 available in non-secure mode. 573 574config ARM_ERRATA_458693 575 bool "ARM errata: Processor deadlock when a false hazard is created" 576 depends on CPU_V7 577 depends on !ARCH_MULTIPLATFORM 578 help 579 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 580 erratum. For very specific sequences of memory operations, it is 581 possible for a hazard condition intended for a cache line to instead 582 be incorrectly associated with a different cache line. This false 583 hazard might then cause a processor deadlock. The workaround enables 584 the L1 caching of the NEON accesses and disables the PLD instruction 585 in the ACTLR register. Note that setting specific bits in the ACTLR 586 register may not be available in non-secure mode and thus is not 587 available on a multiplatform kernel. This should be applied by the 588 bootloader instead. 589 590config ARM_ERRATA_460075 591 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 592 depends on CPU_V7 593 depends on !ARCH_MULTIPLATFORM 594 help 595 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 596 erratum. Any asynchronous access to the L2 cache may encounter a 597 situation in which recent store transactions to the L2 cache are lost 598 and overwritten with stale memory contents from external memory. The 599 workaround disables the write-allocate mode for the L2 cache via the 600 ACTLR register. Note that setting specific bits in the ACTLR register 601 may not be available in non-secure mode and thus is not available on 602 a multiplatform kernel. This should be applied by the bootloader 603 instead. 604 605config ARM_ERRATA_742230 606 bool "ARM errata: DMB operation may be faulty" 607 depends on CPU_V7 && SMP 608 depends on !ARCH_MULTIPLATFORM 609 help 610 This option enables the workaround for the 742230 Cortex-A9 611 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 612 between two write operations may not ensure the correct visibility 613 ordering of the two writes. This workaround sets a specific bit in 614 the diagnostic register of the Cortex-A9 which causes the DMB 615 instruction to behave as a DSB, ensuring the correct behaviour of 616 the two writes. Note that setting specific bits in the diagnostics 617 register may not be available in non-secure mode and thus is not 618 available on a multiplatform kernel. This should be applied by the 619 bootloader instead. 620 621config ARM_ERRATA_742231 622 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 623 depends on CPU_V7 && SMP 624 depends on !ARCH_MULTIPLATFORM 625 help 626 This option enables the workaround for the 742231 Cortex-A9 627 (r2p0..r2p2) erratum. Under certain conditions, specific to the 628 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 629 accessing some data located in the same cache line, may get corrupted 630 data due to bad handling of the address hazard when the line gets 631 replaced from one of the CPUs at the same time as another CPU is 632 accessing it. This workaround sets specific bits in the diagnostic 633 register of the Cortex-A9 which reduces the linefill issuing 634 capabilities of the processor. Note that setting specific bits in the 635 diagnostics register may not be available in non-secure mode and thus 636 is not available on a multiplatform kernel. This should be applied by 637 the bootloader instead. 638 639config ARM_ERRATA_643719 640 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 641 depends on CPU_V7 && SMP 642 default y 643 help 644 This option enables the workaround for the 643719 Cortex-A9 (prior to 645 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 646 register returns zero when it should return one. The workaround 647 corrects this value, ensuring cache maintenance operations which use 648 it behave as intended and avoiding data corruption. 649 650config ARM_ERRATA_720789 651 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 652 depends on CPU_V7 653 help 654 This option enables the workaround for the 720789 Cortex-A9 (prior to 655 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 656 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 657 As a consequence of this erratum, some TLB entries which should be 658 invalidated are not, resulting in an incoherency in the system page 659 tables. The workaround changes the TLB flushing routines to invalidate 660 entries regardless of the ASID. 661 662config ARM_ERRATA_743622 663 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 664 depends on CPU_V7 665 depends on !ARCH_MULTIPLATFORM 666 help 667 This option enables the workaround for the 743622 Cortex-A9 668 (r2p*) erratum. Under very rare conditions, a faulty 669 optimisation in the Cortex-A9 Store Buffer may lead to data 670 corruption. This workaround sets a specific bit in the diagnostic 671 register of the Cortex-A9 which disables the Store Buffer 672 optimisation, preventing the defect from occurring. This has no 673 visible impact on the overall performance or power consumption of the 674 processor. Note that setting specific bits in the diagnostics register 675 may not be available in non-secure mode and thus is not available on a 676 multiplatform kernel. This should be applied by the bootloader instead. 677 678config ARM_ERRATA_751472 679 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 680 depends on CPU_V7 681 depends on !ARCH_MULTIPLATFORM 682 help 683 This option enables the workaround for the 751472 Cortex-A9 (prior 684 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 685 completion of a following broadcasted operation if the second 686 operation is received by a CPU before the ICIALLUIS has completed, 687 potentially leading to corrupted entries in the cache or TLB. 688 Note that setting specific bits in the diagnostics register may 689 not be available in non-secure mode and thus is not available on 690 a multiplatform kernel. This should be applied by the bootloader 691 instead. 692 693config ARM_ERRATA_754322 694 bool "ARM errata: possible faulty MMU translations following an ASID switch" 695 depends on CPU_V7 696 help 697 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 698 r3p*) erratum. A speculative memory access may cause a page table walk 699 which starts prior to an ASID switch but completes afterwards. This 700 can populate the micro-TLB with a stale entry which may be hit with 701 the new ASID. This workaround places two dsb instructions in the mm 702 switching code so that no page table walks can cross the ASID switch. 703 704config ARM_ERRATA_754327 705 bool "ARM errata: no automatic Store Buffer drain" 706 depends on CPU_V7 && SMP 707 help 708 This option enables the workaround for the 754327 Cortex-A9 (prior to 709 r2p0) erratum. The Store Buffer does not have any automatic draining 710 mechanism and therefore a livelock may occur if an external agent 711 continuously polls a memory location waiting to observe an update. 712 This workaround defines cpu_relax() as smp_mb(), preventing correctly 713 written polling loops from denying visibility of updates to memory. 714 715config ARM_ERRATA_364296 716 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 717 depends on CPU_V6 718 help 719 This options enables the workaround for the 364296 ARM1136 720 r0p2 erratum (possible cache data corruption with 721 hit-under-miss enabled). It sets the undocumented bit 31 in 722 the auxiliary control register and the FI bit in the control 723 register, thus disabling hit-under-miss without putting the 724 processor into full low interrupt latency mode. ARM11MPCore 725 is not affected. 726 727config ARM_ERRATA_764369 728 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 729 depends on CPU_V7 && SMP 730 help 731 This option enables the workaround for erratum 764369 732 affecting Cortex-A9 MPCore with two or more processors (all 733 current revisions). Under certain timing circumstances, a data 734 cache line maintenance operation by MVA targeting an Inner 735 Shareable memory region may fail to proceed up to either the 736 Point of Coherency or to the Point of Unification of the 737 system. This workaround adds a DSB instruction before the 738 relevant cache maintenance functions and sets a specific bit 739 in the diagnostic control register of the SCU. 740 741config ARM_ERRATA_764319 742 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 743 depends on CPU_V7 744 help 745 This option enables the workaround for the 764319 Cortex-A9 erratum. 746 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 747 unexpected Undefined Instruction exception when the DBGSWENABLE 748 external pin is set to 0, even when the CP14 accesses are performed 749 from a privileged mode. This work around catches the exception in a 750 way the kernel does not stop execution. 751 752config ARM_ERRATA_775420 753 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 754 depends on CPU_V7 755 help 756 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 757 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 758 operation aborts with MMU exception, it might cause the processor 759 to deadlock. This workaround puts DSB before executing ISB if 760 an abort may occur on cache maintenance. 761 762config ARM_ERRATA_798181 763 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 764 depends on CPU_V7 && SMP 765 help 766 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 767 adequately shooting down all use of the old entries. This 768 option enables the Linux kernel workaround for this erratum 769 which sends an IPI to the CPUs that are running the same ASID 770 as the one being invalidated. 771 772config ARM_ERRATA_773022 773 bool "ARM errata: incorrect instructions may be executed from loop buffer" 774 depends on CPU_V7 775 help 776 This option enables the workaround for the 773022 Cortex-A15 777 (up to r0p4) erratum. In certain rare sequences of code, the 778 loop buffer may deliver incorrect instructions. This 779 workaround disables the loop buffer to avoid the erratum. 780 781config ARM_ERRATA_818325_852422 782 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 783 depends on CPU_V7 784 help 785 This option enables the workaround for: 786 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 787 instruction might deadlock. Fixed in r0p1. 788 - Cortex-A12 852422: Execution of a sequence of instructions might 789 lead to either a data corruption or a CPU deadlock. Not fixed in 790 any Cortex-A12 cores yet. 791 This workaround for all both errata involves setting bit[12] of the 792 Feature Register. This bit disables an optimisation applied to a 793 sequence of 2 instructions that use opposing condition codes. 794 795config ARM_ERRATA_821420 796 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 797 depends on CPU_V7 798 help 799 This option enables the workaround for the 821420 Cortex-A12 800 (all revs) erratum. In very rare timing conditions, a sequence 801 of VMOV to Core registers instructions, for which the second 802 one is in the shadow of a branch or abort, can lead to a 803 deadlock when the VMOV instructions are issued out-of-order. 804 805config ARM_ERRATA_825619 806 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 807 depends on CPU_V7 808 help 809 This option enables the workaround for the 825619 Cortex-A12 810 (all revs) erratum. Within rare timing constraints, executing a 811 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 812 and Device/Strongly-Ordered loads and stores might cause deadlock 813 814config ARM_ERRATA_857271 815 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 816 depends on CPU_V7 817 help 818 This option enables the workaround for the 857271 Cortex-A12 819 (all revs) erratum. Under very rare timing conditions, the CPU might 820 hang. The workaround is expected to have a < 1% performance impact. 821 822config ARM_ERRATA_852421 823 bool "ARM errata: A17: DMB ST might fail to create order between stores" 824 depends on CPU_V7 825 help 826 This option enables the workaround for the 852421 Cortex-A17 827 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 828 execution of a DMB ST instruction might fail to properly order 829 stores from GroupA and stores from GroupB. 830 831config ARM_ERRATA_852423 832 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 833 depends on CPU_V7 834 help 835 This option enables the workaround for: 836 - Cortex-A17 852423: Execution of a sequence of instructions might 837 lead to either a data corruption or a CPU deadlock. Not fixed in 838 any Cortex-A17 cores yet. 839 This is identical to Cortex-A12 erratum 852422. It is a separate 840 config option from the A12 erratum due to the way errata are checked 841 for and handled. 842 843config ARM_ERRATA_857272 844 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 845 depends on CPU_V7 846 help 847 This option enables the workaround for the 857272 Cortex-A17 erratum. 848 This erratum is not known to be fixed in any A17 revision. 849 This is identical to Cortex-A12 erratum 857271. It is a separate 850 config option from the A12 erratum due to the way errata are checked 851 for and handled. 852 853endmenu 854 855source "arch/arm/common/Kconfig" 856 857menu "Bus support" 858 859config ISA 860 bool 861 help 862 Find out whether you have ISA slots on your motherboard. ISA is the 863 name of a bus system, i.e. the way the CPU talks to the other stuff 864 inside your box. Other bus systems are PCI, EISA, MicroChannel 865 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 866 newer boards don't support it. If you have ISA, say Y, otherwise N. 867 868# Select ISA DMA interface 869config ISA_DMA_API 870 bool 871 872config ARM_ERRATA_814220 873 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 874 depends on CPU_V7 875 help 876 The v7 ARM states that all cache and branch predictor maintenance 877 operations that do not specify an address execute, relative to 878 each other, in program order. 879 However, because of this erratum, an L2 set/way cache maintenance 880 operation can overtake an L1 set/way cache maintenance operation. 881 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 882 r0p4, r0p5. 883 884endmenu 885 886menu "Kernel Features" 887 888config HAVE_SMP 889 bool 890 help 891 This option should be selected by machines which have an SMP- 892 capable CPU. 893 894 The only effect of this option is to make the SMP-related 895 options available to the user for configuration. 896 897config SMP 898 bool "Symmetric Multi-Processing" 899 depends on CPU_V6K || CPU_V7 900 depends on HAVE_SMP 901 depends on MMU || ARM_MPU 902 select IRQ_WORK 903 help 904 This enables support for systems with more than one CPU. If you have 905 a system with only one CPU, say N. If you have a system with more 906 than one CPU, say Y. 907 908 If you say N here, the kernel will run on uni- and multiprocessor 909 machines, but will use only one CPU of a multiprocessor machine. If 910 you say Y here, the kernel will run on many, but not all, 911 uniprocessor machines. On a uniprocessor machine, the kernel 912 will run faster if you say N here. 913 914 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 915 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 916 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 917 918 If you don't know what to do here, say N. 919 920config SMP_ON_UP 921 bool "Allow booting SMP kernel on uniprocessor systems" 922 depends on SMP && MMU 923 default y 924 help 925 SMP kernels contain instructions which fail on non-SMP processors. 926 Enabling this option allows the kernel to modify itself to make 927 these instructions safe. Disabling it allows about 1K of space 928 savings. 929 930 If you don't know what to do here, say Y. 931 932 933config CURRENT_POINTER_IN_TPIDRURO 934 def_bool y 935 depends on CPU_32v6K && !CPU_V6 936 937config IRQSTACKS 938 def_bool y 939 select HAVE_IRQ_EXIT_ON_IRQ_STACK 940 select HAVE_SOFTIRQ_ON_OWN_STACK 941 942config ARM_CPU_TOPOLOGY 943 bool "Support cpu topology definition" 944 depends on SMP && CPU_V7 945 default y 946 help 947 Support ARM cpu topology definition. The MPIDR register defines 948 affinity between processors which is then used to describe the cpu 949 topology of an ARM System. 950 951config SCHED_MC 952 bool "Multi-core scheduler support" 953 depends on ARM_CPU_TOPOLOGY 954 help 955 Multi-core scheduler support improves the CPU scheduler's decision 956 making when dealing with multi-core CPU chips at a cost of slightly 957 increased overhead in some places. If unsure say N here. 958 959config SCHED_SMT 960 bool "SMT scheduler support" 961 depends on ARM_CPU_TOPOLOGY 962 help 963 Improves the CPU scheduler's decision making when dealing with 964 MultiThreading at a cost of slightly increased overhead in some 965 places. If unsure say N here. 966 967config HAVE_ARM_SCU 968 bool 969 help 970 This option enables support for the ARM snoop control unit 971 972config HAVE_ARM_ARCH_TIMER 973 bool "Architected timer support" 974 depends on CPU_V7 975 select ARM_ARCH_TIMER 976 help 977 This option enables support for the ARM architected timer 978 979config HAVE_ARM_TWD 980 bool 981 help 982 This options enables support for the ARM timer and watchdog unit 983 984config MCPM 985 bool "Multi-Cluster Power Management" 986 depends on CPU_V7 && SMP 987 help 988 This option provides the common power management infrastructure 989 for (multi-)cluster based systems, such as big.LITTLE based 990 systems. 991 992config MCPM_QUAD_CLUSTER 993 bool 994 depends on MCPM 995 help 996 To avoid wasting resources unnecessarily, MCPM only supports up 997 to 2 clusters by default. 998 Platforms with 3 or 4 clusters that use MCPM must select this 999 option to allow the additional clusters to be managed. 1000 1001config BIG_LITTLE 1002 bool "big.LITTLE support (Experimental)" 1003 depends on CPU_V7 && SMP 1004 select MCPM 1005 help 1006 This option enables support selections for the big.LITTLE 1007 system architecture. 1008 1009config BL_SWITCHER 1010 bool "big.LITTLE switcher support" 1011 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1012 select CPU_PM 1013 help 1014 The big.LITTLE "switcher" provides the core functionality to 1015 transparently handle transition between a cluster of A15's 1016 and a cluster of A7's in a big.LITTLE system. 1017 1018config BL_SWITCHER_DUMMY_IF 1019 tristate "Simple big.LITTLE switcher user interface" 1020 depends on BL_SWITCHER && DEBUG_KERNEL 1021 help 1022 This is a simple and dummy char dev interface to control 1023 the big.LITTLE switcher core code. It is meant for 1024 debugging purposes only. 1025 1026choice 1027 prompt "Memory split" 1028 depends on MMU 1029 default VMSPLIT_3G 1030 help 1031 Select the desired split between kernel and user memory. 1032 1033 If you are not absolutely sure what you are doing, leave this 1034 option alone! 1035 1036 config VMSPLIT_3G 1037 bool "3G/1G user/kernel split" 1038 config VMSPLIT_3G_OPT 1039 depends on !ARM_LPAE 1040 bool "3G/1G user/kernel split (for full 1G low memory)" 1041 config VMSPLIT_2G 1042 bool "2G/2G user/kernel split" 1043 config VMSPLIT_1G 1044 bool "1G/3G user/kernel split" 1045endchoice 1046 1047config PAGE_OFFSET 1048 hex 1049 default PHYS_OFFSET if !MMU 1050 default 0x40000000 if VMSPLIT_1G 1051 default 0x80000000 if VMSPLIT_2G 1052 default 0xB0000000 if VMSPLIT_3G_OPT 1053 default 0xC0000000 1054 1055config KASAN_SHADOW_OFFSET 1056 hex 1057 depends on KASAN 1058 default 0x1f000000 if PAGE_OFFSET=0x40000000 1059 default 0x5f000000 if PAGE_OFFSET=0x80000000 1060 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1061 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1062 default 0xffffffff 1063 1064config NR_CPUS 1065 int "Maximum number of CPUs (2-32)" 1066 range 2 16 if DEBUG_KMAP_LOCAL 1067 range 2 32 if !DEBUG_KMAP_LOCAL 1068 depends on SMP 1069 default "4" 1070 help 1071 The maximum number of CPUs that the kernel can support. 1072 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1073 debugging is enabled, which uses half of the per-CPU fixmap 1074 slots as guard regions. 1075 1076config HOTPLUG_CPU 1077 bool "Support for hot-pluggable CPUs" 1078 depends on SMP 1079 select GENERIC_IRQ_MIGRATION 1080 help 1081 Say Y here to experiment with turning CPUs off and on. CPUs 1082 can be controlled through /sys/devices/system/cpu. 1083 1084config ARM_PSCI 1085 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1086 depends on HAVE_ARM_SMCCC 1087 select ARM_PSCI_FW 1088 help 1089 Say Y here if you want Linux to communicate with system firmware 1090 implementing the PSCI specification for CPU-centric power 1091 management operations described in ARM document number ARM DEN 1092 0022A ("Power State Coordination Interface System Software on 1093 ARM processors"). 1094 1095config HZ_FIXED 1096 int 1097 default 128 if SOC_AT91RM9200 1098 default 0 1099 1100choice 1101 depends on HZ_FIXED = 0 1102 prompt "Timer frequency" 1103 1104config HZ_100 1105 bool "100 Hz" 1106 1107config HZ_200 1108 bool "200 Hz" 1109 1110config HZ_250 1111 bool "250 Hz" 1112 1113config HZ_300 1114 bool "300 Hz" 1115 1116config HZ_500 1117 bool "500 Hz" 1118 1119config HZ_1000 1120 bool "1000 Hz" 1121 1122endchoice 1123 1124config HZ 1125 int 1126 default HZ_FIXED if HZ_FIXED != 0 1127 default 100 if HZ_100 1128 default 200 if HZ_200 1129 default 250 if HZ_250 1130 default 300 if HZ_300 1131 default 500 if HZ_500 1132 default 1000 1133 1134config SCHED_HRTICK 1135 def_bool HIGH_RES_TIMERS 1136 1137config THUMB2_KERNEL 1138 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1139 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1140 default y if CPU_THUMBONLY 1141 select ARM_UNWIND 1142 help 1143 By enabling this option, the kernel will be compiled in 1144 Thumb-2 mode. 1145 1146 If unsure, say N. 1147 1148config ARM_PATCH_IDIV 1149 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1150 depends on CPU_32v7 1151 default y 1152 help 1153 The ARM compiler inserts calls to __aeabi_idiv() and 1154 __aeabi_uidiv() when it needs to perform division on signed 1155 and unsigned integers. Some v7 CPUs have support for the sdiv 1156 and udiv instructions that can be used to implement those 1157 functions. 1158 1159 Enabling this option allows the kernel to modify itself to 1160 replace the first two instructions of these library functions 1161 with the sdiv or udiv plus "bx lr" instructions when the CPU 1162 it is running on supports them. Typically this will be faster 1163 and less power intensive than running the original library 1164 code to do integer division. 1165 1166config AEABI 1167 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1168 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1169 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1170 help 1171 This option allows for the kernel to be compiled using the latest 1172 ARM ABI (aka EABI). This is only useful if you are using a user 1173 space environment that is also compiled with EABI. 1174 1175 Since there are major incompatibilities between the legacy ABI and 1176 EABI, especially with regard to structure member alignment, this 1177 option also changes the kernel syscall calling convention to 1178 disambiguate both ABIs and allow for backward compatibility support 1179 (selected with CONFIG_OABI_COMPAT). 1180 1181 To use this you need GCC version 4.0.0 or later. 1182 1183config OABI_COMPAT 1184 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1185 depends on AEABI && !THUMB2_KERNEL 1186 help 1187 This option preserves the old syscall interface along with the 1188 new (ARM EABI) one. It also provides a compatibility layer to 1189 intercept syscalls that have structure arguments which layout 1190 in memory differs between the legacy ABI and the new ARM EABI 1191 (only for non "thumb" binaries). This option adds a tiny 1192 overhead to all syscalls and produces a slightly larger kernel. 1193 1194 The seccomp filter system will not be available when this is 1195 selected, since there is no way yet to sensibly distinguish 1196 between calling conventions during filtering. 1197 1198 If you know you'll be using only pure EABI user space then you 1199 can say N here. If this option is not selected and you attempt 1200 to execute a legacy ABI binary then the result will be 1201 UNPREDICTABLE (in fact it can be predicted that it won't work 1202 at all). If in doubt say N. 1203 1204config ARCH_SELECT_MEMORY_MODEL 1205 def_bool y 1206 1207config ARCH_FLATMEM_ENABLE 1208 def_bool !(ARCH_RPC || ARCH_SA1100) 1209 1210config ARCH_SPARSEMEM_ENABLE 1211 def_bool !ARCH_FOOTBRIDGE 1212 select SPARSEMEM_STATIC if SPARSEMEM 1213 1214config HIGHMEM 1215 bool "High Memory Support" 1216 depends on MMU 1217 select KMAP_LOCAL 1218 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1219 help 1220 The address space of ARM processors is only 4 Gigabytes large 1221 and it has to accommodate user address space, kernel address 1222 space as well as some memory mapped IO. That means that, if you 1223 have a large amount of physical memory and/or IO, not all of the 1224 memory can be "permanently mapped" by the kernel. The physical 1225 memory that is not permanently mapped is called "high memory". 1226 1227 Depending on the selected kernel/user memory split, minimum 1228 vmalloc space and actual amount of RAM, you may not need this 1229 option which should result in a slightly faster kernel. 1230 1231 If unsure, say n. 1232 1233config HIGHPTE 1234 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1235 depends on HIGHMEM 1236 default y 1237 help 1238 The VM uses one page of physical memory for each page table. 1239 For systems with a lot of processes, this can use a lot of 1240 precious low memory, eventually leading to low memory being 1241 consumed by page tables. Setting this option will allow 1242 user-space 2nd level page tables to reside in high memory. 1243 1244config ARM_PAN 1245 bool "Enable privileged no-access" 1246 depends on MMU 1247 default y 1248 help 1249 Increase kernel security by ensuring that normal kernel accesses 1250 are unable to access userspace addresses. This can help prevent 1251 use-after-free bugs becoming an exploitable privilege escalation 1252 by ensuring that magic values (such as LIST_POISON) will always 1253 fault when dereferenced. 1254 1255 The implementation uses CPU domains when !CONFIG_ARM_LPAE and 1256 disabling of TTBR0 page table walks with CONFIG_ARM_LPAE. 1257 1258config CPU_SW_DOMAIN_PAN 1259 def_bool y 1260 depends on ARM_PAN && !ARM_LPAE 1261 help 1262 Enable use of CPU domains to implement privileged no-access. 1263 1264 CPUs with low-vector mappings use a best-efforts implementation. 1265 Their lower 1MB needs to remain accessible for the vectors, but 1266 the remainder of userspace will become appropriately inaccessible. 1267 1268config CPU_TTBR0_PAN 1269 def_bool y 1270 depends on ARM_PAN && ARM_LPAE 1271 help 1272 Enable privileged no-access by disabling TTBR0 page table walks when 1273 running in kernel mode. 1274 1275config HW_PERF_EVENTS 1276 def_bool y 1277 depends on ARM_PMU 1278 1279config ARM_MODULE_PLTS 1280 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1281 depends on MODULES 1282 select KASAN_VMALLOC if KASAN 1283 default y 1284 help 1285 Allocate PLTs when loading modules so that jumps and calls whose 1286 targets are too far away for their relative offsets to be encoded 1287 in the instructions themselves can be bounced via veneers in the 1288 module's PLT. This allows modules to be allocated in the generic 1289 vmalloc area after the dedicated module memory area has been 1290 exhausted. The modules will use slightly more memory, but after 1291 rounding up to page size, the actual memory footprint is usually 1292 the same. 1293 1294 Disabling this is usually safe for small single-platform 1295 configurations. If unsure, say y. 1296 1297config ARCH_FORCE_MAX_ORDER 1298 int "Order of maximal physically contiguous allocations" 1299 default "11" if SOC_AM33XX 1300 default "8" if SA1111 1301 default "10" 1302 help 1303 The kernel page allocator limits the size of maximal physically 1304 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1305 defines the maximal power of two of number of pages that can be 1306 allocated as a single contiguous block. This option allows 1307 overriding the default setting when ability to allocate very 1308 large blocks of physically contiguous memory is required. 1309 1310 Don't change if unsure. 1311 1312config ALIGNMENT_TRAP 1313 def_bool CPU_CP15_MMU 1314 select HAVE_PROC_CPU if PROC_FS 1315 help 1316 ARM processors cannot fetch/store information which is not 1317 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1318 address divisible by 4. On 32-bit ARM processors, these non-aligned 1319 fetch/store instructions will be emulated in software if you say 1320 here, which has a severe performance impact. This is necessary for 1321 correct operation of some network protocols. With an IP-only 1322 configuration it is safe to say N, otherwise say Y. 1323 1324config UACCESS_WITH_MEMCPY 1325 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1326 depends on MMU 1327 default y if CPU_FEROCEON 1328 help 1329 Implement faster copy_to_user and clear_user methods for CPU 1330 cores where a 8-word STM instruction give significantly higher 1331 memory write throughput than a sequence of individual 32bit stores. 1332 1333 A possible side effect is a slight increase in scheduling latency 1334 between threads sharing the same address space if they invoke 1335 such copy operations with large buffers. 1336 1337 However, if the CPU data cache is using a write-allocate mode, 1338 this option is unlikely to provide any performance gain. 1339 1340config PARAVIRT 1341 bool "Enable paravirtualization code" 1342 help 1343 This changes the kernel so it can modify itself when it is run 1344 under a hypervisor, potentially improving performance significantly 1345 over full virtualization. 1346 1347config PARAVIRT_TIME_ACCOUNTING 1348 bool "Paravirtual steal time accounting" 1349 select PARAVIRT 1350 help 1351 Select this option to enable fine granularity task steal time 1352 accounting. Time spent executing other tasks in parallel with 1353 the current vCPU is discounted from the vCPU power. To account for 1354 that, there can be a small performance impact. 1355 1356 If in doubt, say N here. 1357 1358config XEN_DOM0 1359 def_bool y 1360 depends on XEN 1361 1362config XEN 1363 bool "Xen guest support on ARM" 1364 depends on ARM && AEABI && OF 1365 depends on CPU_V7 && !CPU_V6 1366 depends on !GENERIC_ATOMIC64 1367 depends on MMU 1368 select ARCH_DMA_ADDR_T_64BIT 1369 select ARM_PSCI 1370 select SWIOTLB 1371 select SWIOTLB_XEN 1372 select PARAVIRT 1373 help 1374 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1375 1376config CC_HAVE_STACKPROTECTOR_TLS 1377 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1378 1379config STACKPROTECTOR_PER_TASK 1380 bool "Use a unique stack canary value for each task" 1381 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1382 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1383 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1384 default y 1385 help 1386 Due to the fact that GCC uses an ordinary symbol reference from 1387 which to load the value of the stack canary, this value can only 1388 change at reboot time on SMP systems, and all tasks running in the 1389 kernel's address space are forced to use the same canary value for 1390 the entire duration that the system is up. 1391 1392 Enable this option to switch to a different method that uses a 1393 different canary value for each task. 1394 1395endmenu 1396 1397menu "Boot options" 1398 1399config USE_OF 1400 bool "Flattened Device Tree support" 1401 select IRQ_DOMAIN 1402 select OF 1403 help 1404 Include support for flattened device tree machine descriptions. 1405 1406config ARCH_WANT_FLAT_DTB_INSTALL 1407 def_bool y 1408 1409config ATAGS 1410 bool "Support for the traditional ATAGS boot data passing" 1411 default y 1412 help 1413 This is the traditional way of passing data to the kernel at boot 1414 time. If you are solely relying on the flattened device tree (or 1415 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1416 to remove ATAGS support from your kernel binary. 1417 1418config DEPRECATED_PARAM_STRUCT 1419 bool "Provide old way to pass kernel parameters" 1420 depends on ATAGS 1421 help 1422 This was deprecated in 2001 and announced to live on for 5 years. 1423 Some old boot loaders still use this way. 1424 1425# Compressed boot loader in ROM. Yes, we really want to ask about 1426# TEXT and BSS so we preserve their values in the config files. 1427config ZBOOT_ROM_TEXT 1428 hex "Compressed ROM boot loader base address" 1429 default 0x0 1430 help 1431 The physical address at which the ROM-able zImage is to be 1432 placed in the target. Platforms which normally make use of 1433 ROM-able zImage formats normally set this to a suitable 1434 value in their defconfig file. 1435 1436 If ZBOOT_ROM is not enabled, this has no effect. 1437 1438config ZBOOT_ROM_BSS 1439 hex "Compressed ROM boot loader BSS address" 1440 default 0x0 1441 help 1442 The base address of an area of read/write memory in the target 1443 for the ROM-able zImage which must be available while the 1444 decompressor is running. It must be large enough to hold the 1445 entire decompressed kernel plus an additional 128 KiB. 1446 Platforms which normally make use of ROM-able zImage formats 1447 normally set this to a suitable value in their defconfig file. 1448 1449 If ZBOOT_ROM is not enabled, this has no effect. 1450 1451config ZBOOT_ROM 1452 bool "Compressed boot loader in ROM/flash" 1453 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1454 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1455 help 1456 Say Y here if you intend to execute your compressed kernel image 1457 (zImage) directly from ROM or flash. If unsure, say N. 1458 1459config ARM_APPENDED_DTB 1460 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1461 depends on OF 1462 help 1463 With this option, the boot code will look for a device tree binary 1464 (DTB) appended to zImage 1465 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1466 1467 This is meant as a backward compatibility convenience for those 1468 systems with a bootloader that can't be upgraded to accommodate 1469 the documented boot protocol using a device tree. 1470 1471 Beware that there is very little in terms of protection against 1472 this option being confused by leftover garbage in memory that might 1473 look like a DTB header after a reboot if no actual DTB is appended 1474 to zImage. Do not leave this option active in a production kernel 1475 if you don't intend to always append a DTB. Proper passing of the 1476 location into r2 of a bootloader provided DTB is always preferable 1477 to this option. 1478 1479config ARM_ATAG_DTB_COMPAT 1480 bool "Supplement the appended DTB with traditional ATAG information" 1481 depends on ARM_APPENDED_DTB 1482 help 1483 Some old bootloaders can't be updated to a DTB capable one, yet 1484 they provide ATAGs with memory configuration, the ramdisk address, 1485 the kernel cmdline string, etc. Such information is dynamically 1486 provided by the bootloader and can't always be stored in a static 1487 DTB. To allow a device tree enabled kernel to be used with such 1488 bootloaders, this option allows zImage to extract the information 1489 from the ATAG list and store it at run time into the appended DTB. 1490 1491choice 1492 prompt "Kernel command line type" 1493 depends on ARM_ATAG_DTB_COMPAT 1494 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1495 1496config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1497 bool "Use bootloader kernel arguments if available" 1498 help 1499 Uses the command-line options passed by the boot loader instead of 1500 the device tree bootargs property. If the boot loader doesn't provide 1501 any, the device tree bootargs property will be used. 1502 1503config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1504 bool "Extend with bootloader kernel arguments" 1505 help 1506 The command-line arguments provided by the boot loader will be 1507 appended to the the device tree bootargs property. 1508 1509endchoice 1510 1511config CMDLINE 1512 string "Default kernel command string" 1513 default "" 1514 help 1515 On some architectures (e.g. CATS), there is currently no way 1516 for the boot loader to pass arguments to the kernel. For these 1517 architectures, you should supply some command-line options at build 1518 time by entering them here. As a minimum, you should specify the 1519 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1520 1521choice 1522 prompt "Kernel command line type" 1523 depends on CMDLINE != "" 1524 default CMDLINE_FROM_BOOTLOADER 1525 1526config CMDLINE_FROM_BOOTLOADER 1527 bool "Use bootloader kernel arguments if available" 1528 help 1529 Uses the command-line options passed by the boot loader. If 1530 the boot loader doesn't provide any, the default kernel command 1531 string provided in CMDLINE will be used. 1532 1533config CMDLINE_EXTEND 1534 bool "Extend bootloader kernel arguments" 1535 help 1536 The command-line arguments provided by the boot loader will be 1537 appended to the default kernel command string. 1538 1539config CMDLINE_FORCE 1540 bool "Always use the default kernel command string" 1541 help 1542 Always use the default kernel command string, even if the boot 1543 loader passes other arguments to the kernel. 1544 This is useful if you cannot or don't want to change the 1545 command-line options your boot loader passes to the kernel. 1546endchoice 1547 1548config XIP_KERNEL 1549 bool "Kernel Execute-In-Place from ROM" 1550 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1551 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1552 help 1553 Execute-In-Place allows the kernel to run from non-volatile storage 1554 directly addressable by the CPU, such as NOR flash. This saves RAM 1555 space since the text section of the kernel is not loaded from flash 1556 to RAM. Read-write sections, such as the data section and stack, 1557 are still copied to RAM. The XIP kernel is not compressed since 1558 it has to run directly from flash, so it will take more space to 1559 store it. The flash address used to link the kernel object files, 1560 and for storing it, is configuration dependent. Therefore, if you 1561 say Y here, you must know the proper physical address where to 1562 store the kernel image depending on your own flash memory usage. 1563 1564 Also note that the make target becomes "make xipImage" rather than 1565 "make zImage" or "make Image". The final kernel binary to put in 1566 ROM memory will be arch/arm/boot/xipImage. 1567 1568 If unsure, say N. 1569 1570config XIP_PHYS_ADDR 1571 hex "XIP Kernel Physical Location" 1572 depends on XIP_KERNEL 1573 default "0x00080000" 1574 help 1575 This is the physical address in your flash memory the kernel will 1576 be linked for and stored to. This address is dependent on your 1577 own flash usage. 1578 1579config XIP_DEFLATED_DATA 1580 bool "Store kernel .data section compressed in ROM" 1581 depends on XIP_KERNEL 1582 select ZLIB_INFLATE 1583 help 1584 Before the kernel is actually executed, its .data section has to be 1585 copied to RAM from ROM. This option allows for storing that data 1586 in compressed form and decompressed to RAM rather than merely being 1587 copied, saving some precious ROM space. A possible drawback is a 1588 slightly longer boot delay. 1589 1590config ARCH_SUPPORTS_KEXEC 1591 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1592 1593config ATAGS_PROC 1594 bool "Export atags in procfs" 1595 depends on ATAGS && KEXEC 1596 default y 1597 help 1598 Should the atags used to boot the kernel be exported in an "atags" 1599 file in procfs. Useful with kexec. 1600 1601config ARCH_SUPPORTS_CRASH_DUMP 1602 def_bool y 1603 1604config ARCH_DEFAULT_CRASH_DUMP 1605 def_bool y 1606 1607config AUTO_ZRELADDR 1608 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1609 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1610 help 1611 ZRELADDR is the physical address where the decompressed kernel 1612 image will be placed. If AUTO_ZRELADDR is selected, the address 1613 will be determined at run-time, either by masking the current IP 1614 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1615 This assumes the zImage being placed in the first 128MB from 1616 start of memory. 1617 1618config EFI_STUB 1619 bool 1620 1621config EFI 1622 bool "UEFI runtime support" 1623 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1624 select UCS2_STRING 1625 select EFI_PARAMS_FROM_FDT 1626 select EFI_STUB 1627 select EFI_GENERIC_STUB 1628 select EFI_RUNTIME_WRAPPERS 1629 help 1630 This option provides support for runtime services provided 1631 by UEFI firmware (such as non-volatile variables, realtime 1632 clock, and platform reset). A UEFI stub is also provided to 1633 allow the kernel to be booted as an EFI application. This 1634 is only useful for kernels that may run on systems that have 1635 UEFI firmware. 1636 1637config DMI 1638 bool "Enable support for SMBIOS (DMI) tables" 1639 depends on EFI 1640 default y 1641 help 1642 This enables SMBIOS/DMI feature for systems. 1643 1644 This option is only useful on systems that have UEFI firmware. 1645 However, even with this option, the resultant kernel should 1646 continue to boot on existing non-UEFI platforms. 1647 1648 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1649 i.e., the the practice of identifying the platform via DMI to 1650 decide whether certain workarounds for buggy hardware and/or 1651 firmware need to be enabled. This would require the DMI subsystem 1652 to be enabled much earlier than we do on ARM, which is non-trivial. 1653 1654endmenu 1655 1656menu "CPU Power Management" 1657 1658source "drivers/cpufreq/Kconfig" 1659 1660source "drivers/cpuidle/Kconfig" 1661 1662endmenu 1663 1664menu "Floating point emulation" 1665 1666comment "At least one emulation must be selected" 1667 1668config FPE_NWFPE 1669 bool "NWFPE math emulation" 1670 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1671 help 1672 Say Y to include the NWFPE floating point emulator in the kernel. 1673 This is necessary to run most binaries. Linux does not currently 1674 support floating point hardware so you need to say Y here even if 1675 your machine has an FPA or floating point co-processor podule. 1676 1677 You may say N here if you are going to load the Acorn FPEmulator 1678 early in the bootup. 1679 1680config FPE_NWFPE_XP 1681 bool "Support extended precision" 1682 depends on FPE_NWFPE 1683 help 1684 Say Y to include 80-bit support in the kernel floating-point 1685 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1686 Note that gcc does not generate 80-bit operations by default, 1687 so in most cases this option only enlarges the size of the 1688 floating point emulator without any good reason. 1689 1690 You almost surely want to say N here. 1691 1692config FPE_FASTFPE 1693 bool "FastFPE math emulation (EXPERIMENTAL)" 1694 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1695 help 1696 Say Y here to include the FAST floating point emulator in the kernel. 1697 This is an experimental much faster emulator which now also has full 1698 precision for the mantissa. It does not support any exceptions. 1699 It is very simple, and approximately 3-6 times faster than NWFPE. 1700 1701 It should be sufficient for most programs. It may be not suitable 1702 for scientific calculations, but you have to check this for yourself. 1703 If you do not feel you need a faster FP emulation you should better 1704 choose NWFPE. 1705 1706config VFP 1707 bool "VFP-format floating point maths" 1708 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1709 help 1710 Say Y to include VFP support code in the kernel. This is needed 1711 if your hardware includes a VFP unit. 1712 1713 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1714 release notes and additional status information. 1715 1716 Say N if your target does not have VFP hardware. 1717 1718config VFPv3 1719 bool 1720 depends on VFP 1721 default y if CPU_V7 1722 1723config NEON 1724 bool "Advanced SIMD (NEON) Extension support" 1725 depends on VFPv3 && CPU_V7 1726 help 1727 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1728 Extension. 1729 1730config KERNEL_MODE_NEON 1731 bool "Support for NEON in kernel mode" 1732 depends on NEON && AEABI 1733 help 1734 Say Y to include support for NEON in kernel mode. 1735 1736endmenu 1737 1738menu "Power management options" 1739 1740source "kernel/power/Kconfig" 1741 1742config ARCH_SUSPEND_POSSIBLE 1743 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1744 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1745 def_bool y 1746 1747config ARM_CPU_SUSPEND 1748 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1749 depends on ARCH_SUSPEND_POSSIBLE 1750 1751config ARCH_HIBERNATION_POSSIBLE 1752 bool 1753 depends on MMU 1754 default y if ARCH_SUSPEND_POSSIBLE 1755 1756endmenu 1757