1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_INTEL_ALDERLAKE 4 bool 5 select ACPI_INTEL_HARDWARE_SLEEP_VALUES 6 select ARCH_X86 7 select BOOT_DEVICE_SUPPORTS_WRITES 8 select CACHE_MRC_SETTINGS 9 select CPU_INTEL_COMMON 10 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE 11 select CPU_SUPPORTS_INTEL_TME 12 select CPU_SUPPORTS_PM_TIMER_EMULATION 13 select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS 14 select DISPLAY_FSP_VERSION_INFO 15 select DRIVERS_USB_ACPI 16 select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 17 select FSP_COMPRESS_FSP_S_LZ4 18 select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW 19 select FSP_M_XIP 20 select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN 21 select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 22 select FSP_USES_CB_DEBUG_EVENT_HANDLER 23 select FSPS_HAS_ARCH_UPD 24 select GENERIC_GPIO_LIB 25 select HAVE_DEBUG_RAM_SETUP 26 select HAVE_FSP_GOP 27 select HAVE_HYPERTHREADING 28 select INTEL_DESCRIPTOR_MODE_CAPABLE 29 select HAVE_SMI_HANDLER 30 select IDT_IN_EVERY_STAGE 31 select INTEL_GMA_ACPI 32 select INTEL_GMA_ADD_VBT if RUN_FSP_GOP 33 select INTEL_GMA_OPREGION_2_1 34 select INTEL_GMA_VERSION_2 35 select INTEL_TXT_LIB 36 select MP_SERVICES_PPI_V2 37 select MRC_CACHE_USING_MRC_VERSION if SOC_INTEL_ALDERLAKE_PCH_N && !FSP_TYPE_IOT 38 select MRC_SETTINGS_PROTECT 39 select PARALLEL_MP_AP_WORK 40 select PLATFORM_USES_FSP2_2 41 select PMC_GLOBAL_RESET_ENABLE_LOCK 42 select SOC_INTEL_COMMON 43 select CPU_INTEL_COMMON_VOLTAGE 44 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE 45 select SOC_INTEL_COMMON_BASECODE 46 select SOC_INTEL_COMMON_BASECODE_RAMTOP 47 select SOC_INTEL_COMMON_BLOCK 48 select SOC_INTEL_COMMON_BLOCK_ACPI 49 select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC 50 select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID 51 select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO 52 select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT 53 select SOC_INTEL_COMMON_BLOCK_ACPI_PEP 54 select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ 55 select SOC_INTEL_COMMON_BLOCK_CAR 56 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG 57 select SOC_INTEL_COMMON_BLOCK_CNVI 58 select SOC_INTEL_COMMON_BLOCK_CPU 59 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT 60 select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE 61 select SOC_INTEL_COMMON_BLOCK_DTT 62 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT 63 select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI 64 select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 65 select SOC_INTEL_COMMON_BLOCK_SCS if SOC_INTEL_ALDERLAKE_PCH_N 66 select SOC_INTEL_COMMON_BLOCK_HDA 67 select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC 68 select SOC_INTEL_COMMON_BLOCK_IPU if !SOC_INTEL_ALDERLAKE_PCH_S 69 select SOC_INTEL_COMMON_BLOCK_IRQ 70 select SOC_INTEL_COMMON_BLOCK_ME_SPEC_16 71 select SOC_INTEL_COMMON_BLOCK_MEMINIT 72 select SOC_INTEL_COMMON_BLOCK_OC_WDT 73 select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 74 select SOC_INTEL_COMMON_BLOCK_PMC_EPOC 75 select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT 76 select SOC_INTEL_COMMON_BLOCK_SA 77 select SOC_INTEL_COMMON_BLOCK_SMM 78 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP 79 select SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE 80 select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC 81 select SOC_INTEL_COMMON_BLOCK_VTD 82 select SOC_INTEL_COMMON_BLOCK_XHCI 83 select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG 84 select SOC_INTEL_COMMON_FSP_RESET 85 select SOC_INTEL_COMMON_PCH_CLIENT 86 select SOC_INTEL_COMMON_RESET 87 select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON && !BOARD_GOOGLE_BROX_COMMON 88 select SOC_INTEL_CSE_SET_EOP 89 select SOC_INTEL_GFX_MBUS_JOIN if MAINBOARD_HAS_CHROMEOS && BMP_LOGO 90 select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION 91 select HAVE_INTEL_COMPLIANCE_TEST_MODE 92 select SSE2 93 select SUPPORT_CPU_UCODE_IN_CBFS 94 select TSC_MONOTONIC_TIMER 95 select UDELAY_TSC 96 select UDK_202111_BINDING if SOC_INTEL_ALDERLAKE_PCH_N 97 select UDK_202005_BINDING if !SOC_INTEL_ALDERLAKE_PCH_N 98 select VBOOT_LIB 99 select X86_CLFLUSH_CAR 100 help 101 Intel Alderlake support. Mainboards should specify the PCH 102 type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead 103 of selecting this option directly. 104 105config SOC_INTEL_RAPTORLAKE 106 bool 107 select X86_INIT_NEED_1_SIPI 108 help 109 Intel Raptorlake support. Mainboards using RPL should select 110 SOC_INTEL_RAPTORLAKE and SOC_INTEL_ALDERLAKE_PCH_* together. 111 112config SOC_INTEL_TWINLAKE 113 bool 114 select SOC_INTEL_ALDERLAKE_PCH_N 115 help 116 Intel Twinlake support. Mainboards using TWL should select 117 SOC_INTEL_TWINLAKE. 118 119config SOC_INTEL_ALDERLAKE_PCH_N 120 bool 121 select HAVE_INTEL_FSP_REPO if FSP_TYPE_IOT 122 select SOC_INTEL_ALDERLAKE 123 help 124 Choose this option if your mainboard has a PCH-N chipset. 125 126config SOC_INTEL_ALDERLAKE_PCH_P 127 bool 128 select SOC_INTEL_ALDERLAKE 129 select HAVE_INTEL_FSP_REPO 130 select PLATFORM_USES_FSP2_3 131 help 132 Choose this option if your mainboard has a PCH-P chipset. 133 134config SOC_INTEL_ALDERLAKE_PCH_S 135 bool 136 select SOC_INTEL_ALDERLAKE 137 select HAVE_INTEL_FSP_REPO 138 select PLATFORM_USES_FSP2_3 139 help 140 Choose this option if your mainboard has a PCH-S chipset. 141 142config SOC_INTEL_RAPTORLAKE_PCH_S 143 bool 144 select SOC_INTEL_ALDERLAKE_PCH_S 145 select SOC_INTEL_RAPTORLAKE 146 help 147 Choose this option if your mainboard has a Raptor Lake PCH-S chipset. 148 149if SOC_INTEL_ALDERLAKE 150 151config DIMM_SPD_SIZE 152 default 512 153 154config SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT 155 bool 156 default n if SOC_INTEL_ALDERLAKE_PCH_S 157 default y 158 select SOC_INTEL_COMMON_BLOCK_TCSS 159 select SOC_INTEL_COMMON_BLOCK_USB4 160 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE 161 select SOC_INTEL_COMMON_BLOCK_USB4_XHCI 162 163config ALDERLAKE_CONFIGURE_DESCRIPTOR 164 bool 165 help 166 Select this if the descriptor needs to be updated at runtime. This 167 can only be done if the descriptor region is writable, and should only 168 be used as a temporary workaround. 169 170config ALDERLAKE_CAR_ENHANCED_NEM 171 bool 172 default y if !INTEL_CAR_NEM 173 select INTEL_CAR_NEM_ENHANCED 174 select CAR_HAS_SF_MASKS 175 select COS_MAPPED_TO_MSB 176 select CAR_HAS_L3_PROTECTED_WAYS 177 178config MAX_CPUS 179 int 180 default 32 if SOC_INTEL_RAPTORLAKE 181 default 24 182 183config DCACHE_RAM_BASE 184 default 0xfef00000 185 186config DCACHE_RAM_SIZE 187 default 0xc0000 188 help 189 The size of the cache-as-ram region required during bootblock 190 and/or romstage. 191 192config DCACHE_BSP_STACK_SIZE 193 hex 194 default 0x80400 195 help 196 The amount of anticipated stack usage in CAR by bootblock and 197 other stages. In the case of FSP_USES_CB_STACK default value will be 198 sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement 199 (~1KiB). 200 201config FSP_TEMP_RAM_SIZE 202 hex 203 default 0x20000 204 help 205 The amount of anticipated heap usage in CAR by FSP. 206 Refer to Platform FSP integration guide document to know 207 the exact FSP requirement for Heap setup. 208 209config CHIPSET_DEVICETREE 210 string 211 default "soc/intel/alderlake/chipset_pch_s.cb" if SOC_INTEL_ALDERLAKE_PCH_S 212 default "soc/intel/alderlake/chipset.cb" 213 214config EXT_BIOS_WIN_BASE 215 default 0xf8000000 216 217config EXT_BIOS_WIN_SIZE 218 default 0x2000000 219 220config IFD_CHIPSET 221 string 222 default "adl" 223 224config IED_REGION_SIZE 225 hex 226 default 0x400000 227 228config GFX_GMA_DEFAULT_MMIO 229 default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT 230 231# Intel recommends reserving the following resources per PCIe TBT root port, 232# from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5 233# - 42 buses 234# - 194 MiB Non-prefetchable memory 235# - 448 MiB Prefetchable memory 236if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES 237 238config PCIEXP_HOTPLUG_BUSES 239 int 240 default 42 241 242config PCIEXP_HOTPLUG_MEM 243 hex 244 default 0xc200000 245 246config PCIEXP_HOTPLUG_PREFETCH_MEM 247 hex 248 default 0x1c000000 249 250endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES 251 252config MAX_PCH_ROOT_PORTS 253 int 254 default 12 if SOC_INTEL_ALDERLAKE_PCH_N 255 default 12 if SOC_INTEL_ALDERLAKE_PCH_P 256 default 28 if SOC_INTEL_ALDERLAKE_PCH_S 257 258config MAX_CPU_ROOT_PORTS 259 int 260 default 0 if SOC_INTEL_ALDERLAKE_PCH_N 261 default 3 if SOC_INTEL_ALDERLAKE_PCH_P || SOC_INTEL_ALDERLAKE_PCH_S 262 263config MAX_TBT_ROOT_PORTS 264 int 265 default 0 if SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_ALDERLAKE_PCH_S 266 default 4 if SOC_INTEL_ALDERLAKE_PCH_P 267 268config MAX_ROOT_PORTS 269 int 270 default MAX_PCH_ROOT_PORTS 271 272config MAX_PCIE_CLOCK_SRC 273 int 274 default 5 if SOC_INTEL_ALDERLAKE_PCH_N 275 default 10 if SOC_INTEL_ALDERLAKE_PCH_P 276 default 18 if SOC_INTEL_ALDERLAKE_PCH_S 277 help 278 With external clock buffer, Alderlake-P can support up to three additional source clocks. 279 This is done by setting the corresponding GPIO pin(s) to native function to use as 280 SRCCLK_OE[6..9]. In addition, SRCCLK6 does not need to be set to free running clock. 281 If any of SRCCLKReq 6..9 is asserted, SRCCLK6 will be turned on. 282 283config MAX_PCIE_CLOCK_REQ 284 int 285 default 5 if SOC_INTEL_ALDERLAKE_PCH_N 286 default 10 if SOC_INTEL_ALDERLAKE_PCH_P 287 default 18 if SOC_INTEL_ALDERLAKE_PCH_S 288 289config SMM_TSEG_SIZE 290 hex 291 default 0x800000 292 293config SMM_RESERVED_SIZE 294 hex 295 default 0x200000 296 297config PCR_BASE_ADDRESS 298 hex 299 default 0xe0000000 if SOC_INTEL_ALDERLAKE_PCH_S 300 default 0xfd000000 301 help 302 This option allows you to select MMIO Base Address of sideband bus. 303 304config ECAM_MMCONF_BASE_ADDRESS 305 default 0xc0000000 306 307config CPU_BCLK_MHZ 308 int 309 default 100 310 311config SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR 312 int 313 default 127 314 315config SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR 316 int 317 default 100 318 319config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ 320 int 321 default 120 322 323config CPU_XTAL_HZ 324 default 38400000 325 326config SOC_INTEL_UFS_CLK_FREQ_HZ 327 int 328 default 19200000 329 330config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ 331 int 332 default 133 333 334config SOC_INTEL_COMMON_BLOCK_GSPI_MAX 335 int 336 default 7 337 338config SOC_INTEL_I2C_DEV_MAX 339 int 340 default 8 341 342config ENABLE_SATA_TEST_MODE 343 bool "Enable test mode for SATA margining" 344 default n 345 help 346 Enable SATA test mode in FSP-S. 347 348config SOC_INTEL_UART_DEV_MAX 349 int 350 default 7 351 352config CONSOLE_UART_BASE_ADDRESS 353 hex 354 default 0xfe03e000 355 depends on INTEL_LPSS_UART_FOR_CONSOLE 356 357# Clock divider parameters for 115200 baud rate 358# Baudrate = (UART source clock * M) /(N *16) 359# ADL UART source clock: 100MHz 360config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL 361 hex 362 default 0x25a 363 364config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL 365 hex 366 default 0x7fff 367 368config VBOOT 369 select VBOOT_MUST_REQUEST_DISPLAY 370 select VBOOT_STARTS_IN_BOOTBLOCK 371 select VBOOT_VBNV_CMOS 372 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH 373 select VBOOT_X86_SHA256_ACCELERATION 374 375# Default hash block size is 1KiB. Increasing it to 4KiB to improve 376# hashing time as well as read time. This helps in improving 377# boot time for Alder Lake. 378config VBOOT_HASH_BLOCK_SIZE 379 hex 380 default 0x1000 381 382config CBFS_SIZE 383 default 0x400000 384 385config PRERAM_CBMEM_CONSOLE_SIZE 386 hex 387 default 0x4000 388 389config CONSOLE_CBMEM_BUFFER_SIZE 390 hex 391 default 0x100000 if BUILDING_WITH_DEBUG_FSP 392 default 0x40000 393 394config FSP_TYPE_IOT 395 bool 396 default n 397 help 398 This option allows to select FSP IOT type from 3rdparty/fsp repo 399 400config FSP_HEADER_PATH 401 string "Location of FSP headers" 402 default "src/vendorcode/intel/fsp/fsp2_0/twinlake/" if SOC_INTEL_TWINLAKE && !FSP_USE_REPO 403 default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N && !FSP_USE_REPO 404 default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if SOC_INTEL_RAPTORLAKE && !FSP_USE_REPO 405 default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE && FSP_TYPE_IOT 406 default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/Include/" if SOC_INTEL_RAPTORLAKE_PCH_S && FSP_TYPE_IOT 407 default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE 408 default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && SOC_INTEL_RAPTORLAKE 409 default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT 410 default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT 411 default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && !SOC_INTEL_RAPTORLAKE 412 default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S 413 default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Include/" if SOC_INTEL_ALDERLAKE_PCH_N && FSP_TYPE_IOT 414 default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" if !FSP_USE_REPO 415 416config FSP_FD_PATH 417 string 418 depends on FSP_USE_REPO 419 default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/FSP.fd" if SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE && FSP_TYPE_IOT 420 default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if SOC_INTEL_RAPTORLAKE_PCH_S && FSP_TYPE_IOT 421 default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE 422 default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S && SOC_INTEL_RAPTORLAKE 423 default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT 424 default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT 425 default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && !SOC_INTEL_RAPTORLAKE 426 default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S 427 default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_N && FSP_TYPE_IOT 428 429config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT 430 int "Debug Consent for ADL" 431 # USB DBC is more common for developers so make this default to 2 if 432 # SOC_INTEL_DEBUG_CONSENT=y 433 default 2 if SOC_INTEL_DEBUG_CONSENT 434 default 0 435 help 436 This is to control debug interface on SOC. 437 Setting non-zero value will allow to use DBC or DCI to debug SOC. 438 PlatformDebugConsent in FspmUpd.h has the details. 439 440 Desired platform debug type are 441 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), 442 7:Manual 443 444config DATA_BUS_WIDTH 445 int 446 default 128 447 448config DIMMS_PER_CHANNEL 449 int 450 default 2 451 452config MRC_CHANNEL_WIDTH 453 int 454 default 16 455 456config ALDERLAKE_ENABLE_SOC_WORKAROUND 457 bool 458 default y 459 select SOC_INTEL_UFS_LTR_DISQUALIFY 460 select SOC_INTEL_UFS_OCP_TIMER_DISABLE 461 help 462 Selects the workarounds applicable for Alder Lake SoC. 463 464config USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS 465 bool 466 help 467 Alder Lake SoC based OEM board design with UFS and non-UFS planned to use an 468 unified AP firmware which demanded to have a unified descriptor. It means UFS 469 controller needs to default fuse enabled to let UFS SKU to boot. 470 471 On such design with non-UFS SKU is exhibiting S0ix failure due to UFS remain 472 enabled in the strap although FSP-S is making the UFS controller function 473 disabled. The potential root cause of this behaviour is although the UFS 474 controller is function disabled but MPHY clock is still in active state. 475 476 A possible solution to this problem is to issue a warm reboot (if boot path is 477 S5->S0 or G3->S0) after disabling the UFS and let PMC to read the function 478 disable state of the UFS for disabling the MPHY clock. 479 480 Mainboard users with such board design where OEM would like to use an unified AP 481 firmware to support both UFS and non-UFS sku booting might need to choose this 482 config to allow disabling UFS while booting on the non-UFS SKU. 483 Note: selection of this config would introduce an additional warm reset in 484 cold-reset scenarios due to function disabling of the UFS controller. 485 486if STITCH_ME_BIN 487 488config CSE_BPDT_VERSION 489 default "1.7" 490 491endif 492 493config SI_DESC_REGION 494 string "Descriptor Region name" 495 default "SI_DESC" 496 help 497 Name of Descriptor Region in the FMAP 498 499config SI_DESC_REGION_SZ 500 int 501 default 4096 502 help 503 Size of Descriptor Region in the FMAP 504 505config BUILDING_WITH_DEBUG_FSP 506 bool "Debug FSP is used for the build" 507 default n 508 help 509 Set this option if debug build of FSP is used. 510 511config INTEL_GMA_BCLV_OFFSET 512 default 0xc8258 513 514config INTEL_GMA_BCLV_WIDTH 515 default 32 516 517config INTEL_GMA_BCLM_OFFSET 518 default 0xc8254 519 520config INTEL_GMA_BCLM_WIDTH 521 default 32 522 523config FSP_PUBLISH_MBP_HOB 524 bool 525 default n if CHROMEOS && (SOC_INTEL_ALDERLAKE_PCH_N) 526 default y 527 help 528 This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. 529 Disabling it for the platforms, which do not use MBP HOB, can improve the boot time. 530 531 Note: It cannot be disabled for ADL-P based platforms because ADL-P FSP relies on 532 MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't 533 occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the 534 later platforms so creation of MBP HOB can be skipped for ADL-N based platforms. 535 536config INCLUDE_HSPHY_IN_FMAP 537 bool "Include PCIe 5.0 HSPHY firmware in flash" 538 default n 539 help 540 Set this option to cache the PCIe 5.0 HSPHY firmware after it is 541 fetched from ME during boot. By default coreboot will fetch the 542 HSPHY FW from ME, but if for some reason ME is not enabled or 543 visible, the cached blob will be attempted to initialize the PCIe 544 5.0 root port. Select it if ME is soft disabled or disabled with HAP 545 bit. If possible, the HSPHY FW will be saved to flashmap region if 546 the firmware file is not provided directly in the HSPHY_FW_FILE 547 Kconfig. 548 549config HSPHY_FW_FILE 550 string "HSPHY firmware file path" 551 depends on INCLUDE_HSPHY_IN_FMAP 552 help 553 Path pointing to the PCIe 5.0 HSPHY file. The file can be extracted 554 from full firmware image or ME region using UEFITool. If left empty, 555 HSPHY loading procedure will try to save the firmware to the flashmap 556 region if fetched successfully from ME. 557 558config HSPHY_FW_MAX_SIZE 559 hex 560 default 0x8000 561 562config HAVE_BMP_LOGO_COMPRESS_LZMA 563 default n 564 565config SOC_INTEL_COMMON_BLOCK_ACPI_SLP_S0_FREQ_HZ 566 default 0x2005 567 help 568 slp_s0_residency granularity in 122us ticks (i.e. ~8.2KHz). 569 570endif 571