1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_INTEL_COMMON_BLOCK_PMC 4 depends on SOC_INTEL_COMMON_BLOCK_GPIO 5 depends on ACPI_INTEL_HARDWARE_SLEEP_VALUES 6 bool 7 select ACPI_S1_NOT_SUPPORTED 8 select HAVE_POWER_STATE_AFTER_FAILURE 9 select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE 10 help 11 Intel Processor common code for Power Management controller(PMC) 12 subsystem 13 14if SOC_INTEL_COMMON_BLOCK_PMC 15 16config SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION 17 bool 18 help 19 Select this on platforms where the PMC register for PM configuration (i.e., 20 GEN_PMCON_A/B etc. are memory mapped). 21 22config POWER_STATE_DEFAULT_ON_AFTER_FAILURE 23 default y 24 25config SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE 26 bool 27 help 28 Select this on platforms where the PMC device is discoverable 29 when scanning buses. 30 31config SOC_INTEL_COMMON_BLOCK_PMC_EPOC 32 bool 33 help 34 Enable this for PMC devices to perform EPOC (CPU Early Power-on 35 Configuration) related functions. 36 37endif # SOC_INTEL_COMMON_BLOCK_PMC 38 39config PMC_INVALID_READ_AFTER_WRITE 40 bool 41 default n 42 help 43 Enable this for PMC devices where a read back of ACPI BAR and 44 IO access bit does not return the previously written value. 45 46config PMC_IPC_ACPI_INTERFACE 47 bool 48 default n 49 depends on HAVE_ACPI_TABLES 50 help 51 Enable this to have the PMC IPC mailbox ACPI interface added 52 to the SSDT for use by other drivers. 53 54config PMC_GLOBAL_RESET_ENABLE_LOCK 55 bool 56 help 57 Enable this for PMC devices where the reset configuration 58 and lock register is located under PMC BASE at offset ETR. 59 Note that the reset register is still at 0xCF9 this only 60 controls the enable and lock feature. 61 62config NO_PM_ACPI_TIMER 63 bool 64 help 65 Selected by SoCs that do not have a PM ACPI timer. 66 67config USE_PM_ACPI_TIMER 68 bool "Enable ACPI PM timer" 69 default y 70 depends on !NO_PM_ACPI_TIMER 71 help 72 This should be disabled for devices running on battery since 73 it can draw much power. Further, it must be disabled, if S0ix 74 is enabled. 75 76 Disabling this option also stops the hardware TCO timer and makes 77 the TCO watchdog unavailable. 78 79 Note: On platforms without uCode PM Timer emulation, legacy OSes 80 or payloads with ACPI version < 5.0A might not work without 81 PM ACPI timer. 82 83 (Legacy) software requiring `TMR_STS` (for timer overflow 84 interrupts) will not work with this option disabled. 85