1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOUTHBRIDGE_INTEL_COMMON_RESET 4 def_bool n 5 select HAVE_CF9_RESET 6 7config SOUTHBRIDGE_INTEL_COMMON_RTC 8 def_bool n 9 10config SOUTHBRIDGE_INTEL_COMMON_PMCLIB 11 def_bool n 12 depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE 13 14config SOUTHBRIDGE_INTEL_COMMON_PMBASE 15 def_bool n 16 17config SOUTHBRIDGE_INTEL_COMMON_GPIO 18 def_bool n 19 20config SOUTHBRIDGE_INTEL_COMMON_ME 21 def_bool n 22 23config SOUTHBRIDGE_INTEL_COMMON_HPET 24 def_bool n 25 26config SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS 27 def_bool n 28 29config SOUTHBRIDGE_INTEL_COMMON_SMBUS 30 def_bool n 31 select HAVE_DEBUG_SMBUS 32 33config SOUTHBRIDGE_INTEL_COMMON_SPI 34 def_bool n 35 select SPI_FLASH 36 select BOOT_DEVICE_SUPPORTS_WRITES 37 38config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7 39 def_bool n 40 select SOUTHBRIDGE_INTEL_COMMON_SPI 41 42config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 43 def_bool n 44 select SOUTHBRIDGE_INTEL_COMMON_SPI 45 46config SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT 47 def_bool n 48 select SOUTHBRIDGE_INTEL_COMMON_SPI 49 50config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN 51 def_bool n 52 53config SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ 54 def_bool n 55 select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN 56 57config HAVE_INTEL_CHIPSET_LOCKDOWN 58 def_bool n 59 60config SOUTHBRIDGE_INTEL_COMMON_SMM 61 def_bool n 62 select HAVE_POWER_STATE_AFTER_FAILURE 63 select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE 64 depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE 65 66config SOUTHBRIDGE_INTEL_COMMON_FINALIZE 67 bool 68 69config SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG 70 def_bool n 71 select HAVE_USBDEBUG 72 73config INTEL_DESCRIPTOR_MODE_CAPABLE 74 def_bool n 75 help 76 This config simply states that the platform is *capable* of running in 77 descriptor mode (when the descriptor in flash is valid). 78 79config INTEL_DESCRIPTOR_MODE_REQUIRED 80 def_bool y if INTEL_DESCRIPTOR_MODE_CAPABLE 81 help 82 This config states descriptor mode is *required* for the platform to 83 function properly, or to function at all. 84 85config VALIDATE_INTEL_DESCRIPTOR 86 depends on INTEL_DESCRIPTOR_MODE_CAPABLE 87 bool "Validate Intel firmware descriptor" 88 default n 89 help 90 This config enables validating the Intel firmware descriptor against the 91 fmap layout. If the firmware descriptor layout does not match the fmap 92 then the bootimage cannot be built. 93 94config INTEL_CHIPSET_LOCKDOWN 95 depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS 96 #ChromeOS's payload seems to handle finalization on its on. 97 bool "Lock down chipset in coreboot" 98 default y 99 help 100 Some registers within host bridge on particular chipsets should be 101 locked down on each normal boot path (done by either coreboot or payload) 102 and S3 resume (always done by coreboot). Select this to let coreboot 103 to do this on normal boot path. 104 105config TCO_SPACE_NOT_YET_SPLIT 106 bool 107 108config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG 109 bool 110 depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE 111 112config FIXED_RCBA_MMIO_BASE 113 hex 114 default 0xfed1c000 115 116config RCBA_LENGTH 117 hex 118 default 0x4000 119 120config FIXED_SMBUS_IO_BASE 121 hex 122 depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS 123 default 0x400 124