xref: /aosp_15_r20/external/coreboot/src/soc/amd/common/block/spi/Kconfig (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c) 
1## SPDX-License-Identifier: GPL-2.0-only
2
3config SOC_AMD_COMMON_BLOCK_SPI
4	bool
5	help
6	  Select this option to add FCH SPI controller functions to the build.
7	  This overwrites the structure spi_flash_ops to use FCH SPI code
8	  instead of individual SPI specific code.
9
10config SOC_AMD_COMMON_BLOCK_SPI_DEBUG
11	bool "Enable SPI debugging"
12
13config SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST
14	bool
15	depends on !SOC_AMD_STONEYRIDGE
16	help
17	  Select this option to keep the 4 DWORD burst support enabled.
18
19config EFS_SPI_READ_MODE
20	int
21	range 0 7
22	default 0 if EM100
23	default 2
24	help
25	  SPI read mode to be programmed by the PSP.
26	  The numbers in the options below indicate how many wires
27	  are utilized for command, address and data. For instance 1-1-2
28	  means 1 command, 1 address and 2 data wires.
29	    0: Normal Read (up to 33M)
30	    1: Reserved
31	    2: Dual IO (1-1-2)
32	    3: Quad IO (1-1-4)
33	    4: Dual IO (1-2-2)
34	    5: Quad IO (1-4-4)
35	    6: Normal Read (up to 66M)
36	    7: Fast Read
37
38config EFS_SPI_SPEED
39	int
40	range 0 5
41	default 3 if EM100
42	default 1
43	help
44	  SPI Fast Speed to be programmed by the PSP.
45	    0: 66.66Mhz
46	    1: 33.33MHz
47	    2: 22.22MHz
48	    3: 16.66MHz
49	    4: 100MHz
50	    5: 800KHz
51
52config EFS_SPI_MICRON_FLAG
53	int
54	range 0 2
55	default 0
56	help
57	  For Family 17h Model 00h and later SoC the PSP must be aware if a Micron
58	  part is present in EFS. Automatic detection (option 2) is available
59	  for Family 17h Model 30h-3Fh but is unsupported otherwise.
60	    0: Board does not use Micron parts
61	    1: Board always uses Micron parts
62	    2: Micron parts are optional
63
64config NORMAL_READ_SPI_SPEED
65	int
66	range 0 5
67	default 3 if EM100
68	default 1
69	help
70	  SPI Normal Speed to be programmed by coreboot.
71	    0: 66.66Mhz
72	    1: 33.33MHz
73	    2: 22.22MHz
74	    3: 16.66MHz
75	    4: 100MHz
76	    5: 800KHz
77
78config ALT_SPI_SPEED
79	int
80	range 0 5
81	default 3 if EM100
82	default 1
83	help
84	  SPI ALT Speed to be programmed by coreboot.
85	    0: 66.66Mhz
86	    1: 33.33MHz
87	    2: 22.22MHz
88	    3: 16.66MHz
89	    4: 100MHz
90	    5: 800KHz
91
92config TPM_SPI_SPEED
93	int
94	range 0 5
95	default 3 if EM100
96	default 1
97	help
98	  SPI TPM Speed to be programmed by coreboot.
99	    0: 66.66Mhz
100	    1: 33.33MHz
101	    2: 22.22MHz
102	    3: 16.66MHz
103	    4: 100MHz
104	    5: 800KHz
105