1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_INTEL_COMMON_BASECODE_RAMTOP 4 bool 5 default n 6 help 7 Driver code to store the top_of_ram (RAMTOP) address into 8 non-volatile space (CMOS) during the first boot and use 9 it across all consecutive boot. 10 11 Purpose of this driver code is to cache the RAMTOP (with a 12 fixed size) for all consecutive boots even before calling 13 into the FSP. Otherwise, this range remains un-cached until postcar 14 boot stage updates the MTRR programming. FSP-M and late romstage 15 uses this uncached RAMTOP range for various purposes and having the 16 ability to cache this range beforehand would help to optimize the boot 17 time (more than 50ms). 18