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Searched defs:CR1 (Results 1 – 25 of 30) sorted by relevance

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/btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Device/ST/STM32F4xx/Include/
H A Dstm32f410rx.h151 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
317 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
335 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */ member
460 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
478 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
510 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f410tx.h148 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
314 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
332 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */ member
457 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
475 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
507 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f410cx.h151 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
317 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
335 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */ member
460 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
478 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
510 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f411xe.h156 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
298 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
455 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
473 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
505 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f401xe.h155 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
297 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
454 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
472 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
504 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f401xc.h155 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
297 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
454 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
472 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
504 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f412cx.h176 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
420 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
438 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */ member
595 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
613 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
645 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f446xx.h185 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
493 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
511 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */ member
648 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ member
692 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
748 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
780 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f413xx.h193 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
480 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
498 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */ member
635 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ member
679 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
717 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
749 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f423xx.h194 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
481 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
499 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */ member
636 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ member
680 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
718 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
750 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f412zx.h177 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
440 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
458 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */ member
618 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
656 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
688 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f412vx.h177 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
440 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
458 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */ member
618 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
656 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
688 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f412rx.h177 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
440 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
458 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */ member
618 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
656 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
688 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f427xx.h187 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
605 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
739 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ member
783 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
801 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
833 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f437xx.h188 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
606 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
740 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ member
784 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
802 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
834 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f429xx.h189 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
607 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
787 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ member
831 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
849 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
881 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f415xx.h178 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
462 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
616 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
634 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
666 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f405xx.h179 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
463 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
617 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
635 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
667 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f439xx.h190 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
608 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
788 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ member
832 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
850 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
882 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
H A Dstm32f417xx.h181 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
558 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
712 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
730 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
762 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member
/btstack/port/stm32-l073rz-nucleo-em9304/Drivers/CMSIS/Device/ST/STM32L0xx/Include/
H A Dstm32l073xx.h354 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
495 …__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: … member
511 …__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
560 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ member
/btstack/port/stm32-wb55xx-nucleo-freertos/Drivers/CMSIS/Device/ST/STM32WBxx/Include/
H A Dstm32wb50xx.h319 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
365 …__IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset:… member
514 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ member
559 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
592 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ member
H A Dstm32wb55xx.h351 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
397 …__IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset:… member
567 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ member
612 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
645 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ member
860 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ member
/btstack/port/stm32-l451-miromico-sx1280/Drivers/CMSIS/Device/ST/STM32L4xx/Include/
H A Dstm32l451xx.h516 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
580 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ member
748 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ member
794 …__IO uint32_t CR1; /*!< SPI Control register 1, Address offse… member
826 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
883 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ member
/btstack/port/stm32-f4discovery-cc256x/Drivers/CMSIS/Device/ST/STM32F4xx/Include/
H A Dstm32f407xx.h198 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ member
575 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ member
729 …__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset:… member
747 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ member
779 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ member

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