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Searched defs:CTRL (Results 1 – 25 of 96) sorted by relevance

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/btstack/port/stm32-l073rz-nucleo-em9304/Drivers/CMSIS/Include/
H A Dcore_sc000.h533 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
586 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_cm0plus.h522 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
575 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
/btstack/port/renesas-tb-s1ja-cc256x/template/btstack_example/synergy/ssp/inc/bsp/cmsis/Include/
H A Dcore_cm0plus.h474 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_armv8mbl.h557 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
609 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
881 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
980 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
H A Dcore_cm23.h557 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
609 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
881 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
980 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
/btstack/port/stm32-f4discovery-cc256x/Drivers/CMSIS/Include/
H A Dcore_cm0plus.h474 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_sc000.h485 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_armv8mbl.h560 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
612 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
827 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
933 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
/btstack/port/stm32-wb55xx-nucleo-freertos/Drivers/CMSIS/Include/
H A Dcore_sc000.h485 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_cm0plus.h474 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
/btstack/port/stm32-l451-miromico-sx1280/Drivers/CMSIS/Include/
H A Dcore_sc000.h485 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_cm0plus.h474 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_armv8mbl.h560 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
612 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
827 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
933 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
H A Dcore_cm23.h560 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
612 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
902 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1008 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
/btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra/arm/CMSIS_5/CMSIS/Core/Include/
H A Dcore_cm0plus.h474 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_sc000.h490 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
543 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
/btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Core/Include/
H A Dcore_cm0plus.h474 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_sc000.h485 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_armv8mbl.h560 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
612 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
827 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
933 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
/btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Include/
H A Dcore_sc000.h485 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_cm0plus.h474 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_armv8mbl.h560 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
612 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
827 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
933 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
/btstack/port/stm32-l476rg-nucleo-sx1280/Drivers/CMSIS/Include/
H A Dcore_sc000.h485 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_cm0plus.h474 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_armv8mbl.h560 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
612 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
827 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
933 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member

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