1 /*
2 * Copyright (c) 2017-2019, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file codec_def_common_encode.h
24 //! \brief Defines common types and macros shared by CodecHal, MHW, and DDI layer for encode.
25 //! \details All codec_def_encode may include this file which should not contain any DDI specific code.
26 //!
27 #ifndef __CODEC_DEF_COMMON_ENCODE_H__
28 #define __CODEC_DEF_COMMON_ENCODE_H__
29
30 #include "mos_defs.h"
31
32 #define CODEC_NUM_REF_BUFFERS (CODEC_MAX_NUM_REF_FRAME + 1) // Max 16 references (for AVC) + 1 for the current frame
33 #define CODEC_NUM_NON_REF_BUFFERS 3
34 #define CODEC_NUM_TRACKED_BUFFERS (CODEC_NUM_REF_BUFFERS + CODEC_NUM_NON_REF_BUFFERS)
35 #define CODEC_CURR_TRACKED_BUFFER CODEC_NUM_TRACKED_BUFFERS
36
37 //BRC
38 #define BRC_IMG_STATE_SIZE_PER_PASS 128
39 #define BRC_IMG_STATE_SIZE_PER_PASS_G10 144
40 #define BRC_IMG_STATE_SIZE_PER_PASS_G11 192
41 #define BRC_MAX_BITRATE_RATIO 1.5 // maxBitrate = BRC_MAX_BITRATE_RATIO * targetBitrate
42 #define BRC_DEFAULT_CPB_IN_SEC 2 // bufferSize = BRC_DEFAULT_CPB_IN_SEC * maxBitrate
43 #define CODECHAL_ENCODE_SCENE_CHANGE_DETECTED_MASK 0xffff
44
45 // Quality/Performance differentiators for HSW AVC Encode
46 #define NUM_TARGET_USAGE_MODES 8
47 #define NUM_VDENC_TARGET_USAGE_MODES 8
48
49 //weighted prediction
50 #define CODEC_NUM_WP_FRAME 8
51 #define CODEC_MAX_FORWARD_WP_FRAME 6
52 #define CODEC_MAX_BACKWARD_WP_FRAME 2
53 #define CODEC_WP_OUTPUT_L0_START 0
54 #define CODEC_WP_OUTPUT_L1_START 6
55
56 // HME
57 #define SCALE_FACTOR_2x 2
58 #define SCALE_FACTOR_4x 4
59 #define SCALE_FACTOR_16x 16
60 #define SCALE_FACTOR_32x 32
61
62 // Encode Sizes
63 #define CODECHAL_ENCODE_STATUS_NUM 512
64 #define CODECHAL_ENCODE_SLICESIZE_BUF_SIZE (4960 * sizeof(uint16_t))
65
66 typedef struct tagENCODE_RECT
67 {
68 uint16_t Top; // [0..(FrameHeight+ M-1)/M -1]
69 uint16_t Bottom; // [0..(FrameHeight+ M-1)/M -1]
70 uint16_t Left; // [0..(FrameWidth+15)/16-1]
71 uint16_t Right; // [0..(FrameWidth+15)/16-1]
72 } ENCODE_RECT;
73
74 typedef struct tagMOVE_RECT
75 {
76 uint32_t SourcePointX;
77 uint32_t SourcePointY;
78 uint32_t DestRectTop;
79 uint32_t DestRectBottom;
80 uint32_t DestRectLeft;
81 uint32_t DestRectRight;
82 } MOVE_RECT;
83
84 /*! \brief Defines ROI settings.
85 *
86 * {Top, Bottom, Left, Right} defines the ROI boundary. The values are in unit of blocks. The block size M should use LCU size (e.g. sif LCU size is 32x32, M is 32). And its range should be within the frame boundary, so that:
87 * 0 <= Top <= Bottom <= (FrameHeight+ M-1)/M -1
88 * 0 <= Left <= Right <= (FrameWidth+M-1)/M-1
89 * If input range is out of frame boundary, driver should trim it.
90 * ROI alignes with LCU based rectangular blocks and cannot have arbitrary pixel-based location.
91 * Region overlapping is allowed. For MBs reside within more than one ROIs, parameters from ROI with smaller index rules. For example, when ROI[0] and ROI[1] overlap on a certain area, the QP value for the overlapped area will be determined by value of ROI[0]. The order of ROI[] reflects objects’ relative relationship of depth. Foreground objects should have ROI index smaller than background objects.
92 */
93 typedef struct _CODEC_ROI
94 {
95 uint16_t Top; //!< [0..(FrameHeight+15)/16-1]
96 uint16_t Bottom; //!< [0..(FrameHeight+15)/16-1]
97 uint16_t Left; //!< [0..(FrameWidth+15)/16-1]
98 uint16_t Right; //!< [0..(FrameWidth+15)/16-1]
99 /*! \brief For ROIValueInDeltaQP equals CQP case, this parameter gives explicit delta QP value of ROI regional QP vs. frame QP.
100 *
101 * Value range [-51..51]. If regional QP PriorityLevelOfDQp + QpY is out of range of [0..51], driver should crop it. It could be applied on both CQP and BRC cases. For ROIValueInDeltaQP equals 0BRC cases, this parameter describes the priority level of the ROI region. Value range [-3..3]. The higher the absolute value, the bigger range of delta QP is allowed. And it is usually applies on BRC case. BRC will decide the actual delta QP value. Positive priority level means negative delta QP should be applied. And negative priority level means positive delta QP which implies the region should be intentionally blurred. In either case, value Priority level 0 means same as non-ROI region. It is suggested that application does not set value 0. But if it happens, driver will treat that ROI as part of non-ROI background.
102 */
103 char PriorityLevelOrDQp;
104 } CODEC_ROI, *PCODEC_ROI;
105
106 /*! \brief Indicates the uncompressed input color space
107 *
108 * Valid only when input is ARGB format.
109 */
110 typedef enum _CODEC_INPUT_COLORSPACE
111 {
112 ECOLORSPACE_P709 = 0,
113 ECOLORSPACE_P601 = 1,
114 ECOLORSPACE_P2020 = 2
115 } CODEC_INPUT_COLORSPACE, ENCODE_INPUT_COLORSPACE;
116
117 /*! \brief Indicates the tolerance the application has to variations in the frame size.
118 *
119 * For example, wireless display scenarios may require very steady bitrate to reduce buffering time. It affects the BRC algorithm used, but may or may not have an effect based on the combination of other BRC parameters. Only valid when the driver reports support for FrameSizeToleranceSupport.
120 */
121 typedef enum _CODEC_FRAMESIZE_TOLERANCE
122 {
123 EFRAMESIZETOL_NORMAL = 0,
124 EFRAMESIZETOL_LOW = 1, //!< Maps to "sliding window"
125 EFRAMESIZETOL_EXTREMELY_LOW = 2 //!< Maps to "low delay"
126 } CODEC_FRAMESIZE_TOLERANCE, ENCODE_FRAMESIZE_TOLERANCE;
127
128 /*! \brief Provides a hint to encoder about the scenario for the encoding session.
129 *
130 * BRC algorithm may tune differently based on this info.
131 */
132 typedef enum _CODEC_SCENARIO
133 {
134 ESCENARIO_UNKNOWN = 0,
135 ESCENARIO_DISPLAYREMOTING = 1,
136 ESCENARIO_VIDEOCONFERENCE = 2,
137 ESCENARIO_ARCHIVE = 3,
138 ESCENARIO_LIVESTREAMING = 4,
139 ESCENARIO_VIDEOCAPTURE = 5,
140 ESCENARIO_VIDEOSURVEILLANCE = 6,
141 ESCENARIO_GAMESTREAMING = 7,
142 ESCENARIO_REMOTEGAMING = 8
143 } CODEC_SCENARIO, ENCODE_SCENARIO;
144
145 /*! \brief Provides a hint to encoder about the content for the encoding session.
146 */
147 typedef enum _CODEC_CONTENT
148 {
149 ECONTENT_UNKNOWN = 0,
150 ECONTENT_FULLSCREENVIDEO = 1,
151 ECONTENT_NONVIDEOSCREEN = 2
152 } CODEC_CONTENT, ENCODE_CONTENT;
153
154 typedef enum
155 {
156 RATECONTROL_CBR = 1,
157 RATECONTROL_VBR = 2,
158 RATECONTROL_CQP = 3,
159 RATECONTROL_AVBR = 4,
160 RATECONTROL_RESERVED0 = 8, // This is used by MSDK for Lookahead and hence not used here
161 RATECONTROL_ICQ = 9,
162 RATECONTROL_VCM = 10,
163 RATECONTROL_QVBR = 14,
164 RATECONTROL_CQL = 15,
165 RATECONTROL_IWD_VBR = 100
166 } RATE_CONTROL_METHOD;
167
168 //!
169 //! \brief Help function to check if the rate control method is BRC
170 //!
171 //! \param [in] rc
172 //! Rate control method
173 //!
174 //! \return True if using BRC , else return false
175 //!
IsRateControlBrc(uint8_t rc)176 inline bool IsRateControlBrc(uint8_t rc)
177 {
178 return (rc == RATECONTROL_CBR) ||
179 (rc == RATECONTROL_VBR) ||
180 (rc == RATECONTROL_AVBR) ||
181 (rc == RATECONTROL_VCM) ||
182 (rc == RATECONTROL_ICQ) ||
183 (rc == RATECONTROL_CQL) ||
184 (rc == RATECONTROL_QVBR);
185 }
186
187 typedef enum
188 {
189 DEFAULT_WEIGHTED_INTER_PRED_MODE = 0,
190 EXPLICIT_WEIGHTED_INTER_PRED_MODE = 1,
191 IMPLICIT_WEIGHTED_INTER_PRED_MODE = 2,
192 INVALID_WEIGHTED_INTER_PRED_MODE = -1
193 } WEIGHTED_INTER_PRED_MODE;
194
195 // used from MHW & DDI
196 typedef enum
197 {
198 ROLLING_I_DISABLED = 0,
199 ROLLING_I_COLUMN = 1,
200 ROLLING_I_ROW = 2,
201 ROLLING_I_SQUARE = 3
202 } ROLLING_I_SETTING;
203
204 typedef enum
205 {
206 BRC_ROLLING_I_DISABLED = 0,
207 BRC_ROLLING_I_COLUMN = 4,
208 BRC_ROLLING_I_ROW = 8,
209 BRC_ROLLING_I_SQUARE = 12,
210 BRC_ROLLING_I_QP = 13
211 }BRC_ROLLING_I_SETTING;
212
213 typedef enum _CODECHAL_MFX_SURFACE_ID
214 {
215 CODECHAL_MFX_REF_SURFACE_ID = 0,
216 CODECHAL_MFX_SRC_SURFACE_ID = 4,
217 CODECHAL_MFX_DSRECON_SURFACE_ID = 5
218 } CODECHAL_MFX_SURFACE_ID;
219
220 typedef enum _CODECHAL_HCP_SURFACE_ID
221 {
222 CODECHAL_HCP_DECODED_SURFACE_ID = 0,
223 CODECHAL_HCP_SRC_SURFACE_ID = 1, // Encode
224 CODECHAL_HCP_LAST_SURFACE_ID = 2, // VP9
225 CODECHAL_HCP_GOLDEN_SURFACE_ID = 3, // VP9
226 CODECHAL_HCP_ALTREF_SURFACE_ID = 4, // VP9
227 CODECHAL_HCP_REF_SURFACE_ID = 5
228 } CODECHAL_HCP_SURFACE_ID;
229
230 // ---------------------------
231 // Structures
232 // ---------------------------
233 // used from MHW & DDI
234 typedef struct _BSBuffer
235 {
236 uint8_t *pBase;
237 uint8_t *pCurrent;
238 uint32_t SliceOffset; // Slice offset, always byte aligned
239 uint8_t BitOffset; // bit offset for pCurrent.
240 uint32_t BitSize; // bit size per slice, first slice may include SPS & PPS
241 uint32_t BufferSize; // buffer size
242 } BSBuffer, *PBSBuffer;
243
244 typedef struct _CODEC_ENCODER_SLCDATA
245 {
246 uint32_t SliceOffset;
247 uint32_t BitSize;
248 uint32_t CmdOffset;
249 uint32_t SkipEmulationByteCount;
250
251 // MPEG2 only
252 struct
253 {
254 uint8_t SliceGroup;
255 uint16_t NextSgMbXCnt;
256 uint16_t NextSgMbYCnt;
257 };
258 } CODEC_ENCODER_SLCDATA, *PCODEC_ENCODER_SLCDATA;
259
260 typedef struct _CODECHAL_NAL_UNIT_PARAMS
261 {
262 uint32_t uiNalUnitType;
263 uint32_t uiOffset;
264 uint32_t uiSize;
265 bool bInsertEmulationBytes;
266 uint32_t uiSkipEmulationCheckCount;
267 } CODECHAL_NAL_UNIT_PARAMS, *PCODECHAL_NAL_UNIT_PARAMS;
268
269 typedef struct tagFRAMERATE
270 {
271 uint32_t Numerator;
272 uint32_t Denominator;
273 } FRAMERATE;
274
275 /*********************************************************************************\
276 Constants for VDENC costing look-up-tables
277 \*********************************************************************************/
278 typedef enum _CODEC_VDENC_LUTMODE
279 {
280 CODEC_VDENC_LUTMODE_INTRA_SADMPM = 0x00,
281 CODEC_VDENC_LUTMODE_INTRA_32x32 = 0x01,
282 CODEC_VDENC_LUTMODE_INTRA_16x16 = 0x02,
283 CODEC_VDENC_LUTMODE_INTRA_8x8 = 0x03,
284 CODEC_VDENC_LUTMODE_INTER_32x16 = 0x04,
285 CODEC_VDENC_LUTMODE_INTER_16x32 = 0x04,
286 CODEC_VDENC_LUTMODE_INTER_AMP = 0x04, //All asymmetrical shapes
287 CODEC_VDENC_LUTMODE_INTER_16x16 = 0x05,
288 CODEC_VDENC_LUTMODE_INTER_16x8 = 0x06,
289 CODEC_VDENC_LUTMODE_INTER_8x16 = 0x06,
290 CODEC_VDENC_LUTMODE_INTER_8x8 = 0x07,
291 CODEC_VDENC_LUTMODE_INTER_32x32 = 0x08,
292 CODEC_VDENC_LUTMODE_INTER_BIDIR = 0x09,
293 CODEC_VDENC_LUTMODE_REF_ID = 0x0A,
294 CODEC_VDENC_LUTMODE_INTRA_CHROMA = 0x0B,
295 CODEC_VDENC_LUTMODE_INTRA_NxN = 0x0C,
296 CODEC_VDENC_LUTMODE_INTRA_RDEMPM = 0x0D,
297 CODEC_VDENC_LUTMODE_MERGE_32X32 = 0x0E,
298 CODEC_VDENC_LUTMODE_MERGE_16x16 = 0x0F,
299 CODEC_VDENC_LUTMODE_MERGE_8x8 = 0x10,
300 CODEC_VDENC_LUTMODE_SKIP_32X32 = 0x11,
301 CODEC_VDENC_LUTMODE_SKIP_16x16 = 0x12,
302 CODEC_VDENC_LUTMODE_SKIP_8x8 = 0x13,
303 CODEC_VDENC_LUTMODE_INTRA_DC_32x32_SAD = 0x14,
304 CODEC_VDENC_LUTMODE_INTRA_DC_16x16_SAD = 0x15,
305 CODEC_VDENC_LUTMODE_INTRA_DC_8x8_SAD = 0x16,
306 CODEC_VDENC_LUTMODE_INTRA_DC_4x4_SAD = 0x17,
307 CODEC_VDENC_LUTMODE_INTRA_NONDC_32x32_SAD = 0x18,
308 CODEC_VDENC_LUTMODE_INTRA_NONDC_16x16_SAD = 0x19,
309 CODEC_VDENC_LUTMODE_INTRA_NONDC_8x8_SAD = 0x1A,
310 CODEC_VDENC_LUTMODE_INTRA_NONDC_4x4_SAD = 0x1B,
311 CODEC_VDENC_LUTMODE_INTRA_DC_32x32_RD = 0x1C,
312 CODEC_VDENC_LUTMODE_INTRA_DC_8x8_RD = 0x1D,
313 CODEC_VDENC_LUTMODE_INTRA_NONDC_32x32_RD = 0x1E,
314 CODEC_VDENC_LUTMODE_INTRA_NONDC_8x8_RD = 0x1F,
315 CODEC_VDENC_LUTMODE_INTRA_LEFT_BOUNDARY_SAD = 0x20,
316 CODEC_VDENC_LUTMODE_INTRA_TOP_BOUNDARY_SAD = 0x21,
317 CODEC_VDENC_LUTMODE_INTRA_TU_SPLIT = 0x22,
318 CODEC_VDENC_LUTMODE_INTER_TU_SPLIT = 0x23,
319 CODEC_VDENC_LUTMODE_TU_CBF_FLAG = 0x24,
320 CODEC_VDENC_LUTMODE_INTRA_TU_32_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 0,
321 CODEC_VDENC_LUTMODE_INTRA_TU_16_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 1,
322 CODEC_VDENC_LUTMODE_INTRA_TU_8_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 2,
323 CODEC_VDENC_LUTMODE_INTRA_TU_4_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 3,
324 CODEC_VDENC_LUTMODE_INTER_TU_32_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 4,
325 CODEC_VDENC_LUTMODE_INTER_TU_16_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 5,
326 CODEC_VDENC_LUTMODE_INTER_TU_8_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 6,
327 CODEC_VDENC_LUTMODE_INTER_TU_4_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 7,
328
329 CODEC_VDENC_LUTMODE_TU_COEF_EST = 0x2C,
330 CODEC_VDENC_LUTMODE_INTRA_TU_32_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 0,
331 CODEC_VDENC_LUTMODE_INTRA_TU_16_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 1,
332 CODEC_VDENC_LUTMODE_INTRA_TU_8_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 2,
333 CODEC_VDENC_LUTMODE_INTRA_TU_4_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 3,
334 CODEC_VDENC_LUTMODE_INTER_TU_32_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 4,
335 CODEC_VDENC_LUTMODE_INTER_TU_16_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 5,
336 CODEC_VDENC_LUTMODE_INTER_TU_8_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 6,
337 CODEC_VDENC_LUTMODE_INTER_TU_4_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 7,
338
339 CODEC_VDENC_LUTMODE_INTRA_TU_32_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 8,
340 CODEC_VDENC_LUTMODE_INTRA_TU_16_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 9,
341 CODEC_VDENC_LUTMODE_INTRA_TU_8_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 10,
342 CODEC_VDENC_LUTMODE_INTRA_TU_4_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 11,
343 CODEC_VDENC_LUTMODE_INTER_TU_32_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 12,
344 CODEC_VDENC_LUTMODE_INTER_TU_16_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 13,
345 CODEC_VDENC_LUTMODE_INTER_TU_8_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 14,
346 CODEC_VDENC_LUTMODE_INTER_TU_4_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 15,
347
348 CODEC_VDENC_LUTMODE_INTRA_TU_32_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 16,
349 CODEC_VDENC_LUTMODE_INTRA_TU_16_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 17,
350 CODEC_VDENC_LUTMODE_INTRA_TU_8_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 18,
351 CODEC_VDENC_LUTMODE_INTRA_TU_4_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 19,
352 CODEC_VDENC_LUTMODE_INTER_TU_32_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 20,
353 CODEC_VDENC_LUTMODE_INTER_TU_16_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 21,
354 CODEC_VDENC_LUTMODE_INTER_TU_8_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 22,
355 CODEC_VDENC_LUTMODE_INTER_TU_4_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 23,
356
357 CODEC_VDENC_LUTMODE_INTRA_TU_32_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 24,
358 CODEC_VDENC_LUTMODE_INTRA_TU_16_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 25,
359 CODEC_VDENC_LUTMODE_INTRA_TU_8_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 26,
360 CODEC_VDENC_LUTMODE_INTRA_TU_4_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 27,
361 CODEC_VDENC_LUTMODE_INTER_TU_32_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 28,
362 CODEC_VDENC_LUTMODE_INTER_TU_16_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 29,
363 CODEC_VDENC_LUTMODE_INTER_TU_8_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 30,
364 CODEC_VDENC_LUTMODE_INTER_TU_4_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 31,
365
366 // VP9 specific cost
367 CODEC_VDENC_LUTMODE_INTRA_32x16 = 0x4C,
368 CODEC_VDENC_LUTMODE_INTRA_16x8 = 0x4D,
369 CODEC_VDENC_LUTMODE_INTER_NEARESTMV = 0x4E,
370 CODEC_VDENC_LUTMODE_INTER_NEARMV = 0x4F,
371 CODEC_VDENC_LUTMODE_INTER_ZEROMV = 0x50,
372 CODEC_VDENC_LUTMODE_TU_DEPTH0 = 0x51,
373 CODEC_VDENC_LUTMODE_TU_DEPTH1 = 0x52,
374 CODEC_VDENC_LUTMODE_TU_DEPTH2 = 0x53,
375
376 CODEC_VDENC_LUTMODE_INTRA_64X64DC = 0x54,
377 CODEC_VDENC_LUTMODE_MERGE_64X64 = 0x55,
378 CODEC_VDENC_LUTMODE_SKIP_64X64 = 0x56,
379
380 CODEC_VDENC_NUM_MODE_COST = 0x57
381 } CODEC_VDENC_LUTMODE;
382
383 // Batch buffer type
384 enum
385 {
386 MB_ENC_Frame_BB = 0,
387 MB_ENC_Field_BB,
388 //Add new buffer type here
389 NUM_ENCODE_BB_TYPE
390 };
391
392 typedef enum
393 {
394 FRAME_NO_SKIP = 0, // encode as normal, no skip frames
395 FRAME_SKIP_NORMAL = 1 // one or more frames were skipped prior to curr frame. Encode curr frame as normal, update BRC
396 } FRAME_SKIP_FLAG;
397
398 typedef enum _CODEC_SLICE_STRUCTS
399 {
400 CODECHAL_SLICE_STRUCT_ONESLICE = 0, // Once slice for the whole frame
401 CODECHAL_SLICE_STRUCT_POW2ROWS = 1, // Slices are power of 2 number of rows, all slices the same
402 CODECHAL_SLICE_STRUCT_ROWSLICE = 2, // Slices are any number of rows, all slices the same
403 CODECHAL_SLICE_STRUCT_ARBITRARYROWSLICE = 3, // Slices are any number of rows, slices can be different
404 CODECHAL_SLICE_STRUCT_ARBITRARYMBSLICE = 4 // Slices are any number of MBs, slices can be different
405 // 5 - 7 are Reserved
406 } CODEC_SLICE_STRUCTS;
407
408 enum
409 {
410 CODECHAL_ENCODE_PERFTAG_CALL_MBENC_KERNEL,
411 CODECHAL_ENCODE_PERFTAG_CALL_MBENC_PHASE1_KERNEL = CODECHAL_ENCODE_PERFTAG_CALL_MBENC_KERNEL,
412 CODECHAL_ENCODE_PERFTAG_CALL_MBENC_PHASE2_KERNEL,
413 CODECHAL_ENCODE_PERFTAG_CALL_SCALING_KERNEL,
414 CODECHAL_ENCODE_PERFTAG_CALL_INTRA_DIST,
415 CODECHAL_ENCODE_PERFTAG_CALL_ME_KERNEL,
416 CODECHAL_ENCODE_PERFTAG_CALL_BRC_INIT_RESET,
417 CODECHAL_ENCODE_PERFTAG_CALL_BRC_UPDATE,
418 CODECHAL_ENCODE_PERFTAG_CALL_BRC_COPY,
419 CODECHAL_ENCODE_PERFTAG_CALL_PAK_ENGINE,
420 CODECHAL_ENCODE_PERFTAG_CALL_PAK_KERNEL,
421 CODECHAL_ENCODE_PERFTAG_CALL_PAK_PHASE1_KERNEL = CODECHAL_ENCODE_PERFTAG_CALL_PAK_KERNEL,
422 CODECHAL_ENCODE_PERFTAG_CALL_PAK_PHASE2_KERNEL,
423 CODECHAL_ENCODE_PERFTAG_CALL_UPSCALING,
424 CODECHAL_ENCODE_PERFTAG_CALL_DEBLOCKING,
425 CODECHAL_ENCODE_PERFTAG_CALL_WP_KERNEL,
426 CODECHAL_ENCODE_PERFTAG_CALL_32X32_PU_MD,
427 CODECHAL_ENCODE_PERFTAG_CALL_32X32_B_IC,
428 CODECHAL_ENCODE_PERFTAG_CALL_16X16_PU_MD,
429 CODECHAL_ENCODE_PERFTAG_CALL_16X16_SAD,
430 CODECHAL_ENCODE_PERFTAG_CALL_8X8_PU,
431 CODECHAL_ENCODE_PERFTAG_CALL_8X8_FMODE,
432 CODECHAL_ENCODE_PERFTAG_CALL_BRC_UPDATE_LCU,
433 CODECHAL_ENCODE_PERFTAG_CALL_MBENC_I_32x32,
434 CODECHAL_ENCODE_PERFTAG_CALL_MBENC_I_16x16,
435 CODECHAL_ENCODE_PERFTAG_CALL_MBENC_P,
436 CODECHAL_ENCODE_PERFTAG_CALL_MBENC_TX,
437 CODECHAL_ENCODE_PERFTAG_CALL_MBPAK_RECON_LUMA,
438 CODECHAL_ENCODE_PERFTAG_CALL_MBPAK_RECON_CHROMA,
439 CODECHAL_ENCODE_PERFTAG_CALL_MBPAK_RECON_LUMA_32x32,
440 CODECHAL_ENCODE_PERFTAG_CALL_MBPAK_RECON_INTRA_LUMA,
441 CODECHAL_ENCODE_PERFTAG_CALL_MBPAK_RECON_INTRA_CHROMA,
442 CODECHAL_ENCODE_PERFTAG_CALL_MBPAK_DEBLOCK_MASK,
443 CODECHAL_ENCODE_PERFTAG_CALL_MBPAK_DEBLOCK_LUMA,
444 CODECHAL_ENCODE_PERFTAG_CALL_MBPAK_DEBLOCK_CHROMA,
445 CODECHAL_ENCODE_PERFTAG_CALL_MBPAK_MC,
446 CODECHAL_ENCODE_PERFTAG_CALL_PREPROC_KERNEL,
447 CODECHAL_ENCODE_PERFTAG_CALL_DS_CONVERSION_KERNEL,
448 CODECHAL_ENCODE_PERFTAG_CALL_SCOREBOARD,
449 CODECHAL_ENCODE_PERFTAG_CALL_SFD_KERNEL,
450 CODECHAL_ENCODE_PERFTAG_CALL_PAK_ENGINE_SECOND_PASS,
451 CODECHAL_ENCODE_PERFTAG_CALL_BRC_UPDATE_SECOND_PASS,
452 CODECHAL_ENCODE_PERFTAG_CALL_HEVC_LA_UPDATE,
453 CODECHAL_ENCODE_PERFTAG_CALL_VP9_HPU,
454 CODECHAL_ENCODE_PERFTAG_CALL_VP9_HPU_SECOND_PASS
455 };
456
457 typedef enum _CODECHAL_ENCODE_FUNCTION_ID
458 {
459 CODECHAL_ENCODE_ENC_ID = 0x100,
460 CODECHAL_ENCODE_PAK_ID = 0x101,
461 CODECHAL_ENCODE_ENC_PAK_ID = 0x102,
462 CODECHAL_ENCODE_VPP_ID = 0x103,
463 CODECHAL_ENCODE_FORMAT_COUNT_ID = 0x104,
464 CODECHAL_ENCODE_FORMATS_ID = 0x105,
465 CODECHAL_ENCODE_ENC_CTRL_CAPS_ID = 0x106,
466 CODECHAL_ENCODE_ENC_CTRL_GET_ID = 0x107,
467 CODECHAL_ENCODE_ENC_CTRL_SET_ID = 0x108,
468 CODECHAL_ENCODE_MBDATA_LAYOUT_ID = 0x109,
469 CODECHAL_ENCODE_FEI_PRE_ENC_ID = 0x10A,
470 CODECHAL_ENCODE_FEI_ENC_ID = 0x10B,
471 CODECHAL_ENCODE_FEI_PAK_ID = 0x10C,
472 CODECHAL_ENCODE_FEI_ENC_PAK_ID = 0x10D,
473 CODECHAL_ENCODE_QUERY_STATUS_ID = 0x121
474 } CODECHAL_ENCODE_FUNCTION_ID;
475
476 //!
477 //! \struct HwCounter
478 //! \brief Hardware counter
479 //!
480 struct HwCounter
481 {
482 uint64_t IV; // Big-Endian IV
483 uint64_t Count; // Big-Endian Block Count
484 };
485
486 //!
487 //! \struct CodechalTileInfo
488 //! \brief Tile info report to application
489 //!
490 struct CodechalTileInfo
491 {
492 uint16_t TileRowNum;
493 uint16_t TileColNum;
494 uint32_t TileBitStreamOffset;
495 uint32_t TileSizeInBytes;
496
497 uint32_t reserved;
498 HwCounter HWCounterValue;
499 };
500
501 //FEI Encode Macros
502 #define CodecHalIsFeiEncode(codecFunction) \
503 ( codecFunction == CODECHAL_FUNCTION_FEI_PRE_ENC || \
504 codecFunction == CODECHAL_FUNCTION_FEI_ENC || \
505 codecFunction == CODECHAL_FUNCTION_FEI_PAK || \
506 codecFunction == CODECHAL_FUNCTION_FEI_ENC_PAK)
507
508 //Encode Macros
509 #define CodecHalIsEncode(codecFunction) \
510 (codecFunction == CODECHAL_FUNCTION_ENC || \
511 codecFunction == CODECHAL_FUNCTION_PAK || \
512 codecFunction == CODECHAL_FUNCTION_ENC_PAK || \
513 codecFunction == CODECHAL_FUNCTION_ENC_VDENC_PAK ||\
514 codecFunction == CODECHAL_FUNCTION_HYBRIDPAK) || \
515 CodecHalIsFeiEncode(codecFunction)
516
517 #define CodecHalUsesVideoEngine(codecFunction) \
518 (codecFunction == CODECHAL_FUNCTION_PAK || \
519 codecFunction == CODECHAL_FUNCTION_ENC_PAK || \
520 codecFunction == CODECHAL_FUNCTION_ENC_VDENC_PAK || \
521 codecFunction == CODECHAL_FUNCTION_FEI_PAK || \
522 codecFunction == CODECHAL_FUNCTION_FEI_ENC_PAK)
523
524 #define CodecHalUsesRenderEngine(codecFunction, standard) \
525 (codecFunction == CODECHAL_FUNCTION_ENC || \
526 (codecFunction == CODECHAL_FUNCTION_ENC_PAK) || \
527 codecFunction == CODECHAL_FUNCTION_HYBRIDPAK || \
528 ((codecFunction == CODECHAL_FUNCTION_DECODE) && (standard == CODECHAL_VC1)) || \
529 codecFunction == CODECHAL_FUNCTION_ENC_VDENC_PAK || \
530 codecFunction == CODECHAL_FUNCTION_FEI_PRE_ENC || \
531 codecFunction == CODECHAL_FUNCTION_FEI_ENC || \
532 codecFunction == CODECHAL_FUNCTION_FEI_ENC_PAK)
533
534 #define CodecHalUsesOnlyRenderEngine(codecFunction) \
535 (codecFunction == CODECHAL_FUNCTION_ENC || \
536 codecFunction == CODECHAL_FUNCTION_FEI_ENC || \
537 codecFunction == CODECHAL_FUNCTION_HYBRIDPAK)
538
539 #define CodecHalUsesVdencEngine(codecFunction) \
540 (codecFunction == CODECHAL_FUNCTION_ENC_VDENC_PAK)
541
542 #define CodecHalUsesPakEngine(codecFunction) \
543 (codecFunction == CODECHAL_FUNCTION_PAK || \
544 codecFunction == CODECHAL_FUNCTION_ENC_PAK)
545
546 #define CodecHalIsRateControlBrc(rateControl, standard) (\
547 (rateControl == RATECONTROL_CBR) || \
548 (rateControl == RATECONTROL_VBR) || \
549 (rateControl == RATECONTROL_AVBR) || \
550 (rateControl == RATECONTROL_CQL) || \
551 ((( rateControl == RATECONTROL_VCM) || \
552 ( rateControl == RATECONTROL_ICQ) || \
553 ( rateControl == RATECONTROL_QVBR) || \
554 ( rateControl == RATECONTROL_IWD_VBR)) && \
555 ( standard == CODECHAL_AVC )) )
556
557 // The current definition of the first encode mode CODECHAL_ENCODE_MODE_AVC should be used
558 // as a base for subsequent encode modes
559 #define CODECHAL_ENCODE_MODE_BIT_OFFSET ((uint32_t)(log((double)CODECHAL_ENCODE_MODE_AVC)/log(2.)))
560 #define CODECHAL_ENCODE_MODE_BIT_MASK ((( 1L << CODECHAL_ENCODE_MODE_BIT_OFFSET) - 1 ) & 0xF)
561
562 template<typename ValueType>
SwapEndianness(ValueType value)563 static ValueType SwapEndianness(ValueType value)
564 {
565 uint8_t* startLocation = reinterpret_cast<uint8_t*>(&value);
566 uint8_t* endLocation = startLocation + sizeof(ValueType);
567 std::reverse(startLocation, endLocation);
568 return value;
569 }
570
571 #endif // __CODEC_DEF_COMMON_ENCODE_H__
572