1 /*
2 * Copyright (c) 2017-2022, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file codechal_hw_g12_X.cpp
24 //! \brief Implements HW interface layer for Gen12+ used on all OSs.
25 //! \details Implements HW interface layer for CNL+ to be used on on all operating systems/DDIs, across CODECHAL components.
26 //! This module must not contain any OS dependent code.
27 //!
28
29 #include "codechal_hw_g12_X.h"
30 #include "mhw_render_g12_X.h"
31 #include "mhw_mi_hwcmd_g12_X.h"
32 #include "mhw_vdbox_hcp_hwcmd_g12_X.h" // temporary include for calculating size of various hardware commands
33 #include "mhw_vdbox_vdenc_g12_X.h"
34 #include "mhw_vdbox_hcp_g12_X.h"
35 #include "media_interfaces_g12_tgllp.h"
36 #if defined(ENABLE_KERNELS) && !defined(_FULL_OPEN_SOURCE)
37 #include "igcodeckrn_g12.h"
38 #endif
39 #include "codechal_utilities.h"
40 #include "codeckrnheader.h"
41
42 // Currently initialized with dummy values, just as an example. Will be updated later.
43 const CODECHAL_SSEU_SETTING CodechalHwInterfaceG12::m_defaultSsEuLutG12[CODECHAL_NUM_MEDIA_STATES_G12] =
44 {
45 // Slice Sub-Slice EU Rsvd(freq)
46 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_OLP
47 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_NORMAL
48 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_PERFORMANCE
49 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_QUALITY
50 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_I_FRAME_DIST
51 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_32X_SCALING
52 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_16X_SCALING
53 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_4X_SCALING
54 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_32X_ME
55 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_16X_ME
56 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_4X_ME
57 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_BRC_INIT_RESET
58 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_BRC_UPDATE
59 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_BRC_BLOCK_COPY
60 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HYBRID_PAK_P1
61 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HYBRID_PAK_P2
62 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_I_FRAME_CHROMA
63 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_I_FRAME_LUMA
64 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_MPU_FHB
65 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_TPU_FHB
66 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_PA_COPY
67 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_PL2_COPY
68 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_ADV
69 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_2X_SCALING
70 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_32x32_PU_MODE_DECISION
71 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_16x16_PU_SAD
72 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_16x16_PU_MODE_DECISION
73 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_8x8_PU
74 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_8x8_PU_FMODE
75 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_32x32_B_INTRA_CHECK
76 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_B_MBENC
77 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_RESET_VLINE_STRIDE
78 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_B_PAK
79 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_BRC_LCU_UPDATE
80 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ME_VDENC_STREAMIN
81 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_ENC_I_32x32
82 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_ENC_I_16x16
83 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_ENC_P
84 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_ENC_TX
85 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_LUMA_RECON
86 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_CHROMA_RECON
87 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_DEBLOCK_MASK
88 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_LUMA_DEBLOCK
89 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_CHROMA_DEBLOCK
90 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_MC_PRED
91 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_P_FRAME_LUMA_RECON
92 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_P_FRAME_CHROMA_RECON
93 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_LUMA_RECON
94 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_CHROMA_RECON
95 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_PREPROC
96 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_WP
97 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_I_MBENC
98 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_CSC_DS_COPY
99 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_2X_4X_SCALING
100 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_LCU64_B_MBENC
101 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_MB_BRC_UPDATE
102 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_STATIC_FRAME_DETECTION
103 { 1, 0, 8, 0 },
104 { 1, 0, 8, 0 },
105 { 1, 0, 8, 0 },
106 { 1, 0, 8, 0 },
107 { 2, 3, 8, 0 },
108 { 2, 3, 8, 0 },
109 { 2, 3, 8, 0 },
110 { 2, 3, 8, 0 },
111 };
112
InternalInit(CODECHAL_FUNCTION codecFunction)113 void CodechalHwInterfaceG12::InternalInit(CODECHAL_FUNCTION codecFunction)
114 {
115 InitCacheabilityControlSettings(codecFunction);
116 m_isVdencSuperSliceEnabled = true;
117 m_ssEuTable = m_defaultSsEuLutG12;
118 m_numMediaStates = CODECHAL_NUM_MEDIA_STATES_G12;
119
120 PrepareCmdSize(codecFunction);
121 }
122
PrepareCmdSize(CODECHAL_FUNCTION codecFunction)123 void CodechalHwInterfaceG12::PrepareCmdSize(CODECHAL_FUNCTION codecFunction)
124 {
125 // Set platform dependent parameters
126 m_sizeOfCmdBatchBufferEnd = mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
127 m_sizeOfCmdMediaReset = mhw_mi_g12_X::MI_LOAD_REGISTER_IMM_CMD::byteSize * 8;
128 m_vdencBrcImgStateBufferSize = mhw_vdbox_vdenc_g12_X::VDENC_IMG_STATE_CMD::byteSize + mhw_vdbox_mfx_g12_X::MFX_AVC_IMG_STATE_CMD::byteSize +
129 mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;;
130
131 m_vdencBatchBuffer1stGroupSize = mhw_vdbox_hcp_g12_X::HCP_PIPE_MODE_SELECT_CMD::byteSize
132 + mhw_mi_g12_X::MFX_WAIT_CMD::byteSize * 2
133 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
134
135 m_vdencBatchBuffer2ndGroupSize = 124
136 + mhw_vdbox_hcp_g12_X::HCP_PIC_STATE_CMD::byteSize
137 + 204
138 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
139
140 m_vdencReadBatchBufferSize =
141 m_vdenc2ndLevelBatchBufferSize = m_vdencBatchBuffer1stGroupSize
142 + m_vdencBatchBuffer2ndGroupSize
143 + ENCODE_HEVC_VDENC_NUM_MAX_SLICES
144 * (2 * mhw_vdbox_hcp_g12_X::HCP_WEIGHTOFFSET_STATE_CMD::byteSize
145 + mhw_vdbox_hcp_g12_X::HCP_SLICE_STATE_CMD::byteSize
146 + (HEVC_MAX_NAL_UNIT_TYPE + 2) * mhw_vdbox_hcp_g12_X::HCP_PAK_INSERT_OBJECT_CMD::byteSize
147 + mhw_vdbox_vdenc_g12_X::VDENC_WEIGHTSOFFSETS_STATE_CMD::byteSize
148 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize
149 + 4 * ENCODE_VDENC_HEVC_PADDING_DW_SIZE);
150
151 m_HucStitchCmdBatchBufferSize = 7 * 4
152 + 14 * 4
153 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
154
155 // HCP_WEIGHTOFFSET_STATE_CMD cmds is planned to be added in near future
156 m_vdencBatchBufferPerSliceConstSize = mhw_vdbox_hcp_g12_X::HCP_SLICE_STATE_CMD::byteSize
157 + mhw_vdbox_hcp_g12_X::HCP_PAK_INSERT_OBJECT_CMD::byteSize // 1st PakInsertObject cmd is not always inserted for each slice, 2nd PakInsertObject cmd is always inserted for each slice
158 + mhw_vdbox_vdenc_g12_X::VDENC_WEIGHTSOFFSETS_STATE_CMD::byteSize
159 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
160
161 // Set to size of the BRC update command buffer, since it is larger than BRC Init/ PAK integration commands
162 m_hucCommandBufferSize = mhw_vdbox_huc_g12_X::HUC_IMEM_STATE_CMD::byteSize
163 + mhw_vdbox_huc_g12_X::HUC_PIPE_MODE_SELECT_CMD::byteSize
164 + mhw_mi_g12_X::MFX_WAIT_CMD::byteSize * 3
165 + mhw_vdbox_huc_g12_X::HUC_DMEM_STATE_CMD::byteSize
166 + mhw_vdbox_huc_g12_X::HUC_VIRTUAL_ADDR_STATE_CMD::byteSize
167 + mhw_vdbox_huc_g12_X::HUC_STREAM_OBJECT_CMD::byteSize
168 + mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize
169 + mhw_mi_g12_X::MI_STORE_REGISTER_MEM_CMD::byteSize
170 + mhw_vdbox_huc_g12_X::HUC_START_CMD::byteSize
171 + mhw_vdbox_vdenc_g12_X::VD_PIPELINE_FLUSH_CMD::byteSize
172 + mhw_mi_g12_X::MI_FLUSH_DW_CMD::byteSize
173 + mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize * 2
174 + mhw_mi_g12_X::MI_STORE_REGISTER_MEM_CMD::byteSize * 2
175 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
176
177 m_maxKernelLoadCmdSize =
178 mhw_mi_g12_X::PIPE_CONTROL_CMD::byteSize +
179 mhw_render_g12_X::PIPELINE_SELECT_CMD::byteSize +
180 mhw_render_g12_X::MEDIA_OBJECT_CMD::byteSize +
181 mhw_render_g12_X::STATE_BASE_ADDRESS_CMD::byteSize +
182 mhw_render_g12_X::MEDIA_VFE_STATE_CMD::byteSize +
183 mhw_render_g12_X::MEDIA_CURBE_LOAD_CMD::byteSize +
184 mhw_render_g12_X::MEDIA_INTERFACE_DESCRIPTOR_LOAD_CMD::byteSize +
185 mhw_mi_g12_X::MI_BATCH_BUFFER_START_CMD::byteSize +
186 mhw_render_g12_X::MEDIA_OBJECT_WALKER_CMD::byteSize +
187 mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize;
188
189 m_sizeOfCmdMediaObject = mhw_render_g12_X::MEDIA_OBJECT_CMD::byteSize;
190 m_sizeOfCmdMediaStateFlush = mhw_mi_g12_X::MEDIA_STATE_FLUSH_CMD::byteSize;
191 }
192
CodechalHwInterfaceG12(PMOS_INTERFACE osInterface,CODECHAL_FUNCTION codecFunction,MhwInterfaces * mhwInterfaces,bool disableScalability)193 CodechalHwInterfaceG12::CodechalHwInterfaceG12(
194 PMOS_INTERFACE osInterface,
195 CODECHAL_FUNCTION codecFunction,
196 MhwInterfaces *mhwInterfaces,
197 bool disableScalability)
198 : CodechalHwInterface(osInterface, codecFunction, mhwInterfaces, disableScalability)
199 {
200 CODECHAL_HW_FUNCTION_ENTER;
201 m_avpInterface = static_cast<MhwInterfacesG12Tgllp*>(mhwInterfaces)->m_avpInterface;
202 m_mediaSfcItf = std::make_shared<MediaSfcInterfaceLegacy>(m_osInterface);
203
204 InternalInit(codecFunction);
205 }
206
InitL3CacheSettings()207 MOS_STATUS CodechalHwInterfaceG12::InitL3CacheSettings()
208 {
209 // Get default L3 cache settings
210 if (m_renderInterface)
211 {
212 CODECHAL_HW_CHK_STATUS_RETURN(m_renderInterface->EnableL3Caching(nullptr));
213 }
214 else
215 {
216 CODECHAL_HW_CHK_STATUS_RETURN(m_hwInterfaceNext->GetRenderInterfaceNext()->EnableL3Caching(nullptr));
217 }
218
219 #if (_DEBUG || _RELEASE_INTERNAL)
220 // Override default L3 cache settings
221 if (m_renderInterface)
222 {
223 auto l3CacheConfig = m_renderInterface->GetL3CacheConfig();
224 MHW_RENDER_ENGINE_L3_CACHE_SETTINGS_G12 l3Overrides;
225 l3Overrides.dwTcCntlReg =
226 static_cast<MHW_RENDER_ENGINE_L3_CACHE_CONFIG_G12 *>(l3CacheConfig)->dwL3CacheTcCntlReg_Setting;
227 l3Overrides.dwAllocReg =
228 static_cast<MHW_RENDER_ENGINE_L3_CACHE_CONFIG_G12 *>(l3CacheConfig)->dwL3CacheAllocReg_Setting;
229 CODECHAL_HW_CHK_STATUS_RETURN(InitL3ControlUserFeatureSettings(
230 l3CacheConfig,
231 &l3Overrides));
232 CODECHAL_HW_CHK_STATUS_RETURN(m_renderInterface->EnableL3Caching(
233 &l3Overrides));
234 }
235 else
236 {
237 auto l3CacheConfig = m_hwInterfaceNext->GetRenderInterfaceNext()->GetL3CacheConfig();
238 mhw::render::MHW_RENDER_ENGINE_L3_CACHE_SETTINGS l3Overrides;
239 l3Overrides.dwTcCntlReg =
240 static_cast<mhw::render::MHW_RENDER_ENGINE_L3_CACHE_CONFIG *>(l3CacheConfig)->dwL3CacheTcCntlReg_Setting;
241 l3Overrides.dwAllocReg =
242 static_cast<mhw::render::MHW_RENDER_ENGINE_L3_CACHE_CONFIG *>(l3CacheConfig)->dwL3CacheAllocReg_Setting;
243 CODECHAL_HW_CHK_STATUS_RETURN(InitL3ControlUserFeatureSettings(
244 (MHW_RENDER_ENGINE_L3_CACHE_CONFIG *)l3CacheConfig,
245 (MHW_RENDER_ENGINE_L3_CACHE_SETTINGS_G12 *)&l3Overrides));
246 CODECHAL_HW_CHK_STATUS_RETURN(m_hwInterfaceNext->GetRenderInterfaceNext()->EnableL3Caching(
247 &l3Overrides));
248
249 }
250
251 #endif // (_DEBUG || _RELEASE_INTERNAL)
252
253 return MOS_STATUS_SUCCESS;
254 }
255
GetStreamoutCommandSize(uint32_t * commandsSize,uint32_t * patchListSize)256 MOS_STATUS CodechalHwInterfaceG12::GetStreamoutCommandSize(
257 uint32_t *commandsSize,
258 uint32_t *patchListSize)
259 {
260 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
261
262 CODECHAL_HW_FUNCTION_ENTER;
263
264 MHW_VDBOX_STATE_CMDSIZE_PARAMS_G12 stateCmdSizeParams;
265
266 stateCmdSizeParams.bShortFormat = false;
267 stateCmdSizeParams.bHucDummyStream = MEDIA_IS_WA(m_waTable, WaHucStreamoutEnable);
268 CODECHAL_HW_CHK_STATUS_RETURN(GetHxxStateCommandSize(
269 CODECHAL_DECODE_MODE_CENC, // For CENC phase
270 commandsSize,
271 patchListSize,
272 &stateCmdSizeParams));
273
274 return eStatus;
275 }
276
SetCacheabilitySettings(MHW_MEMORY_OBJECT_CONTROL_PARAMS cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_END_CODEC])277 MOS_STATUS CodechalHwInterfaceG12::SetCacheabilitySettings(
278 MHW_MEMORY_OBJECT_CONTROL_PARAMS cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_END_CODEC])
279 {
280 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
281
282 CODECHAL_HW_FUNCTION_ENTER;
283
284 if (m_mfxInterface)
285 {
286 CODECHAL_HW_CHK_STATUS_RETURN(m_mfxInterface->SetCacheabilitySettings(cacheabilitySettings));
287 }
288 if (m_hcpInterface)
289 {
290 CODECHAL_HW_CHK_STATUS_RETURN(m_hcpInterface->SetCacheabilitySettings(cacheabilitySettings));
291 }
292 if (m_vdencInterface)
293 {
294 CODECHAL_HW_CHK_STATUS_RETURN(m_vdencInterface->SetCacheabilitySettings(cacheabilitySettings));
295 }
296 if (m_avpInterface)
297 {
298 CODECHAL_HW_CHK_STATUS_RETURN(m_avpInterface->SetCacheabilitySettings(cacheabilitySettings));
299 }
300 if (m_hucInterface)
301 {
302 CODECHAL_HW_CHK_STATUS_RETURN(m_hucInterface->SetCacheabilitySettings(cacheabilitySettings));
303 }
304
305 return eStatus;
306 }
307
SetRowstoreCachingOffsets(PMHW_VDBOX_ROWSTORE_PARAMS rowstoreParams)308 MOS_STATUS CodechalHwInterfaceG12::SetRowstoreCachingOffsets(
309 PMHW_VDBOX_ROWSTORE_PARAMS rowstoreParams)
310 {
311 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
312
313 CODECHAL_HW_FUNCTION_ENTER;
314
315 CODECHAL_HW_CHK_STATUS_RETURN(CodechalHwInterface::SetRowstoreCachingOffsets(rowstoreParams));
316
317 if (m_avpInterface)
318 {
319 CODECHAL_HW_CHK_STATUS_RETURN(m_avpInterface->GetRowstoreCachingAddrs(rowstoreParams));
320 }
321
322 return eStatus;
323 }
324
GetAvpStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)325 MOS_STATUS CodechalHwInterfaceG12::GetAvpStateCommandSize(
326 uint32_t mode,
327 uint32_t *commandsSize,
328 uint32_t *patchListSize,
329 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
330 {
331 CODECHAL_HW_FUNCTION_ENTER;
332
333 //calculate AVP related commands size
334 uint32_t avpCommandsSize = 0;
335 uint32_t avpPatchListSize = 0;
336 uint32_t cpCmdsize = 0;
337 uint32_t cpPatchListSize = 0;
338
339 if (m_avpInterface)
340 {
341 CODECHAL_HW_CHK_STATUS_RETURN(m_avpInterface->GetAvpStateCommandSize(
342 (uint32_t *)&avpCommandsSize,
343 (uint32_t *)&avpPatchListSize,
344 params));
345 }
346
347 if (m_cpInterface)
348 {
349 m_cpInterface->GetCpStateLevelCmdSize(cpCmdsize, cpPatchListSize);
350 }
351
352 //Calc final command size
353 *commandsSize = avpCommandsSize + cpCmdsize;
354 *patchListSize = avpPatchListSize + cpPatchListSize;
355
356 return MOS_STATUS_SUCCESS;
357 }
358
GetAvpPrimitiveCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize)359 MOS_STATUS CodechalHwInterfaceG12::GetAvpPrimitiveCommandSize(
360 uint32_t mode,
361 uint32_t *commandsSize,
362 uint32_t *patchListSize)
363 {
364 CODECHAL_HW_FUNCTION_ENTER;
365
366 //calculate AVP related commands size
367 uint32_t avpCommandsSize = 0;
368 uint32_t avpPatchListSize = 0;
369 uint32_t cpCmdsize = 0;
370 uint32_t cpPatchListSize = 0;
371
372 if (m_avpInterface)
373 {
374 CODECHAL_HW_CHK_STATUS_RETURN(m_avpInterface->GetAvpPrimitiveCommandSize(
375 (uint32_t*)&avpCommandsSize,
376 (uint32_t*)&avpPatchListSize));
377 }
378
379 if (m_cpInterface)
380 {
381 m_cpInterface->GetCpSliceLevelCmdSize(cpCmdsize, cpPatchListSize);
382 }
383
384 //Calc final command size
385 *commandsSize = avpCommandsSize + cpCmdsize;
386 *patchListSize = avpPatchListSize + cpPatchListSize;
387
388 return MOS_STATUS_SUCCESS;
389 }
390
391
SendCondBbEndCmd(PMOS_RESOURCE resource,uint32_t offset,uint32_t compData,bool disableCompMask,bool enableEndCurrentBatchBuffLevel,uint32_t compareOperation,PMOS_COMMAND_BUFFER cmdBuffer)392 MOS_STATUS CodechalHwInterfaceG12::SendCondBbEndCmd(
393 PMOS_RESOURCE resource,
394 uint32_t offset,
395 uint32_t compData,
396 bool disableCompMask,
397 bool enableEndCurrentBatchBuffLevel,
398 uint32_t compareOperation,
399 PMOS_COMMAND_BUFFER cmdBuffer)
400 {
401 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
402
403 CODECHAL_HW_FUNCTION_ENTER;
404
405 if (!Mos_ResourceIsNull(&m_conditionalBbEndDummy))
406 {
407 MHW_MI_FLUSH_DW_PARAMS flushDwParams;
408 MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams));
409 flushDwParams.postSyncOperation = 1;
410 flushDwParams.pOsResource = &m_conditionalBbEndDummy;
411 flushDwParams.dwDataDW1 = 0;
412 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(cmdBuffer, &flushDwParams));
413 }
414
415 MHW_MI_ENHANCED_CONDITIONAL_BATCH_BUFFER_END_PARAMS conditionalBatchBufferEndParams;
416 MOS_ZeroMemory(&conditionalBatchBufferEndParams, sizeof(conditionalBatchBufferEndParams));
417 conditionalBatchBufferEndParams.presSemaphoreBuffer = resource;
418 conditionalBatchBufferEndParams.dwOffset = offset;
419 conditionalBatchBufferEndParams.dwValue = compData;
420 conditionalBatchBufferEndParams.bDisableCompareMask = disableCompMask;
421 conditionalBatchBufferEndParams.dwParamsType = MHW_MI_ENHANCED_CONDITIONAL_BATCH_BUFFER_END_PARAMS::ENHANCED_PARAMS;
422 if (enableEndCurrentBatchBuffLevel)
423 {
424 conditionalBatchBufferEndParams.enableEndCurrentBatchBuffLevel = enableEndCurrentBatchBuffLevel;
425 conditionalBatchBufferEndParams.compareOperation = compareOperation;
426 }
427 eStatus = m_miInterface->AddMiConditionalBatchBufferEndCmd(cmdBuffer, &conditionalBatchBufferEndParams);
428
429 return eStatus;
430 }
431
Initialize(CodechalSetting * settings)432 MOS_STATUS CodechalHwInterfaceG12::Initialize(
433 CodechalSetting *settings)
434 {
435 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
436
437 CODECHAL_HW_FUNCTION_ENTER;
438
439 CODECHAL_HW_CHK_STATUS_RETURN(CodechalHwInterface::Initialize(settings));
440 // Added isRenderHalNeeded flag into settings
441 // Indicate whether RenderHal is needed or not
442 if (settings->isRenderHalNeeded ||
443 (settings->codecFunction == CODECHAL_FUNCTION_DECODE &&
444 settings->standard == CODECHAL_AV1))
445 {
446 //Initialize renderHal
447 m_renderHal = (PRENDERHAL_INTERFACE_LEGACY)MOS_AllocAndZeroMemory(sizeof(RENDERHAL_INTERFACE_LEGACY));
448 CODECHAL_HW_CHK_NULL_RETURN(m_renderHal);
449 CODECHAL_HW_CHK_STATUS_RETURN(RenderHal_InitInterface_Legacy(
450 (PRENDERHAL_INTERFACE_LEGACY)m_renderHal,
451 &m_renderHalCpInterface,
452 m_osInterface));
453
454 RENDERHAL_SETTINGS_LEGACY RenderHalSettings;
455 RenderHalSettings.iMediaStates = 32;
456 CODECHAL_HW_CHK_STATUS_RETURN(m_renderHal->pfnInitialize(m_renderHal, &RenderHalSettings));
457
458 //set SSEU table
459 m_renderHal->sseuTable = m_ssEuTable;
460 }
461 return eStatus;
462 }
463
ReadAvpStatus(MHW_VDBOX_NODE_IND vdboxIndex,const EncodeStatusReadParams & params,PMOS_COMMAND_BUFFER cmdBuffer)464 MOS_STATUS CodechalHwInterfaceG12::ReadAvpStatus(MHW_VDBOX_NODE_IND vdboxIndex, const EncodeStatusReadParams ¶ms, PMOS_COMMAND_BUFFER cmdBuffer)
465 {
466 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
467
468 CODECHAL_HW_FUNCTION_ENTER;
469
470 CODECHAL_HW_CHK_NULL_RETURN(cmdBuffer);
471
472 CODECHAL_HW_CHK_COND_RETURN((vdboxIndex > m_mfxInterface->GetMaxVdboxIndex()),"ERROR - vdbox index exceed the maximum");
473
474 MHW_MI_FLUSH_DW_PARAMS flushDwParams;
475 MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams));
476 std::shared_ptr<mhw::mi::Itf> m_miItf = GetMiInterfaceNext();
477 if (m_miInterface)
478 {
479 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(cmdBuffer, &flushDwParams));
480 }
481 else
482 {
483 auto &parFlush = m_miItf->MHW_GETPAR_F(MI_FLUSH_DW)();
484 parFlush = {};
485 CODECHAL_HW_CHK_STATUS_RETURN(m_miItf->MHW_ADDCMD_F(MI_FLUSH_DW)(cmdBuffer));
486 }
487
488 std::shared_ptr<mhw::vdbox::avp::Itf> m_avpItf = GetAvpInterfaceNext();
489 CODECHAL_HW_CHK_NULL_RETURN(m_avpItf);
490 auto mmioRegisters = m_avpItf->GetMmioRegisters(vdboxIndex);
491 if (m_miInterface)
492 {
493 MHW_MI_STORE_REGISTER_MEM_PARAMS miStoreRegMemParams;
494 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
495 miStoreRegMemParams.presStoreBuffer = params.resBitstreamByteCountPerFrame;
496 miStoreRegMemParams.dwOffset = params.bitstreamByteCountPerFrameOffset;
497 miStoreRegMemParams.dwRegister = mmioRegisters->avpAv1BitstreamByteCountTileRegOffset;
498 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
499 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
500 miStoreRegMemParams.presStoreBuffer = params.resQpStatusCount;
501 miStoreRegMemParams.dwOffset = params.qpStatusCountOffset;
502 miStoreRegMemParams.dwRegister = mmioRegisters->avpAv1QpStatusCountRegOffset;
503 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
504
505 }
506 else
507 {
508 auto &storeRegMemParams = m_miItf->MHW_GETPAR_F(MI_STORE_REGISTER_MEM)();
509 storeRegMemParams = {};
510 storeRegMemParams.presStoreBuffer = params.resBitstreamByteCountPerFrame;
511 storeRegMemParams.dwOffset = params.bitstreamByteCountPerFrameOffset;
512 storeRegMemParams.dwRegister = mmioRegisters->avpAv1BitstreamByteCountTileRegOffset;
513 CODECHAL_HW_CHK_STATUS_RETURN(m_miItf->MHW_ADDCMD_F(MI_STORE_REGISTER_MEM)(cmdBuffer));
514 storeRegMemParams = {};
515 storeRegMemParams.presStoreBuffer = params.resQpStatusCount;
516 storeRegMemParams.dwOffset = params.qpStatusCountOffset;
517 storeRegMemParams.dwRegister = mmioRegisters->avpAv1QpStatusCountRegOffset;
518 CODECHAL_HW_CHK_STATUS_RETURN(m_miItf->MHW_ADDCMD_F(MI_STORE_REGISTER_MEM)(cmdBuffer));
519 }
520 return eStatus;
521 }
522
ReadImageStatusForAvp(MHW_VDBOX_NODE_IND vdboxIndex,const EncodeStatusReadParams & params,PMOS_COMMAND_BUFFER cmdBuffer)523 MOS_STATUS CodechalHwInterfaceG12::ReadImageStatusForAvp(MHW_VDBOX_NODE_IND vdboxIndex, const EncodeStatusReadParams ¶ms, PMOS_COMMAND_BUFFER cmdBuffer)
524 {
525 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
526
527 CODECHAL_HW_FUNCTION_ENTER;
528
529 CODECHAL_HW_CHK_NULL_RETURN(cmdBuffer);
530
531 CODECHAL_HW_CHK_COND_RETURN((vdboxIndex > m_mfxInterface->GetMaxVdboxIndex()),"ERROR - vdbox index exceed the maximum");
532
533 std::shared_ptr<mhw::vdbox::avp::Itf> m_avpItf = GetAvpInterfaceNext();
534 CODECHAL_HW_CHK_NULL_RETURN(m_avpItf);
535 auto mmioRegisters = GetAvpInterfaceNext()->GetMmioRegisters(vdboxIndex);
536 std::shared_ptr<mhw::mi::Itf> m_miItf = GetMiInterfaceNext();
537 if (m_miInterface)
538 {
539 MHW_MI_STORE_REGISTER_MEM_PARAMS miStoreRegMemParams;
540 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
541 miStoreRegMemParams.presStoreBuffer = params.resImageStatusMask;
542 miStoreRegMemParams.dwOffset = params.imageStatusMaskOffset;
543 miStoreRegMemParams.dwRegister = mmioRegisters->avpAv1ImageStatusMaskRegOffset;
544 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
545
546 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
547 miStoreRegMemParams.presStoreBuffer = params.resImageStatusCtrl;
548 miStoreRegMemParams.dwOffset = params.imageStatusCtrlOffset;
549 miStoreRegMemParams.dwRegister = mmioRegisters->avpAv1ImageStatusControlRegOffset;
550 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
551
552 MHW_MI_FLUSH_DW_PARAMS flushDwParams;
553 MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams));
554 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(cmdBuffer, &flushDwParams));
555 }
556 else
557 {
558 auto &storeRegMemParams = m_miItf->MHW_GETPAR_F(MI_STORE_REGISTER_MEM)();
559 storeRegMemParams = {};
560 storeRegMemParams.presStoreBuffer = params.resImageStatusMask;
561 storeRegMemParams.dwOffset = params.imageStatusMaskOffset;
562 storeRegMemParams.dwRegister = mmioRegisters->avpAv1ImageStatusMaskRegOffset;
563 CODECHAL_HW_CHK_STATUS_RETURN(m_miItf->MHW_ADDCMD_F(MI_STORE_REGISTER_MEM)(cmdBuffer));
564 storeRegMemParams = {};
565 storeRegMemParams.presStoreBuffer = params.resImageStatusCtrl;
566 storeRegMemParams.dwOffset = params.imageStatusCtrlOffset;
567 storeRegMemParams.dwRegister = mmioRegisters->avpAv1ImageStatusControlRegOffset;
568 CODECHAL_HW_CHK_STATUS_RETURN(m_miItf->MHW_ADDCMD_F(MI_STORE_REGISTER_MEM)(cmdBuffer));
569 auto &parFlush = m_miItf->MHW_GETPAR_F(MI_FLUSH_DW)();
570 parFlush = {};
571 CODECHAL_HW_CHK_STATUS_RETURN(m_miItf->MHW_ADDCMD_F(MI_FLUSH_DW)(cmdBuffer));
572 }
573 return eStatus;
574 }
575
~CodechalHwInterfaceG12()576 CodechalHwInterfaceG12::~CodechalHwInterfaceG12()
577 {
578 if (m_renderHal != nullptr && m_renderHal->pfnDestroy != nullptr)
579 {
580 MOS_STATUS eStatus = m_renderHal->pfnDestroy(m_renderHal);
581 if (eStatus != MOS_STATUS_SUCCESS)
582 {
583 MHW_ASSERTMESSAGE("Failed to destroy RenderHal, eStatus:%d.\n", eStatus);
584 }
585
586 if (m_renderHalCpInterface)
587 {
588 if (m_osInterface)
589 {
590 m_osInterface->pfnDeleteMhwCpInterface(m_renderHalCpInterface);
591 m_renderHalCpInterface = nullptr;
592 }
593 else
594 {
595 MHW_ASSERTMESSAGE("Failed to destroy renderHalCpInterface.");
596 }
597 }
598 }
599
600 if (m_renderHal != nullptr)
601 {
602 MOS_FreeMemory(m_renderHal);
603 m_renderHal = nullptr;
604 }
605
606 if (m_avpInterface)
607 {
608 MOS_Delete(m_avpInterface);
609 }
610 }
611
GetFilmGrainKernelInfo(uint8_t * & kernelBase,uint32_t & kernelSize)612 MOS_STATUS CodechalHwInterfaceG12::GetFilmGrainKernelInfo(
613 uint8_t*& kernelBase,
614 uint32_t& kernelSize)
615 {
616 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
617 uint8_t* kernelArrayBase = nullptr;
618
619 auto kuidCommon = IDR_CODEC_VID_ApplyNoise_Combined;
620 #if defined(ENABLE_KERNELS) && !defined(_FULL_OPEN_SOURCE)
621 kernelArrayBase = (uint8_t*)IGCODECKRN_G12;
622 CODECHAL_HW_CHK_STATUS_RETURN(CodecHalGetKernelBinaryAndSize(kernelArrayBase,
623 kuidCommon,
624 &kernelBase,
625 &kernelSize));
626 #else
627 kernelBase = nullptr;
628 kernelSize = 0;
629 #endif
630
631 return eStatus;
632 }
633