1 /*
2 * Copyright (c) 2021-2022, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file codec_hw_xe2_lpm.cpp
24 //! \brief Implements HW interface layer for Xe2_LPM+ used on all OSs.
25 //! \details Implements HW interface layer for CNL+ to be used on on all operating systems/DDIs, across CODECHAL components.
26 //! This module must not contain any OS dependent code.
27 //!
28
29 #include "codec_hw_xe2_lpm_base.h"
30 #include "mhw_vdbox_hcp_hwcmd_xe2_lpm.h"
31 #include "mhw_vdbox_avp_impl_xe2_lpm.h"
32 #include "mhw_vdbox_hcp_hwcmd_xe2_lpm.h"
33
34 // Currently initialized with dummy values, just as an example. Will be updated later.
35 const CODECHAL_SSEU_SETTING CodechalHwInterfaceXe2_Lpm_Base::m_defaultSsEuLutM15[CODECHAL_NUM_MEDIA_STATES_XE2_LPM] =
36 {
37 // Slice Sub-Slice EU Rsvd(freq)
38 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_OLP
39 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_NORMAL
40 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_PERFORMANCE
41 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_QUALITY
42 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_I_FRAME_DIST
43 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_32X_SCALING
44 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_16X_SCALING
45 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_4X_SCALING
46 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_32X_ME
47 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_16X_ME
48 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_4X_ME
49 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_BRC_INIT_RESET
50 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_BRC_UPDATE
51 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_BRC_BLOCK_COPY
52 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HYBRID_PAK_P1
53 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HYBRID_PAK_P2
54 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_I_FRAME_CHROMA
55 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_I_FRAME_LUMA
56 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_MPU_FHB
57 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_TPU_FHB
58 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_PA_COPY
59 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_PL2_COPY
60 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_ADV
61 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_2X_SCALING
62 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_32x32_PU_MODE_DECISION
63 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_16x16_PU_SAD
64 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_16x16_PU_MODE_DECISION
65 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_8x8_PU
66 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_8x8_PU_FMODE
67 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_32x32_B_INTRA_CHECK
68 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_B_MBENC
69 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_RESET_VLINE_STRIDE
70 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_B_PAK
71 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_BRC_LCU_UPDATE
72 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ME_VDENC_STREAMIN
73 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_ENC_I_32x32
74 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_ENC_I_16x16
75 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_ENC_P
76 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_ENC_TX
77 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_LUMA_RECON
78 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_CHROMA_RECON
79 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_DEBLOCK_MASK
80 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_LUMA_DEBLOCK
81 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_CHROMA_DEBLOCK
82 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_MC_PRED
83 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_P_FRAME_LUMA_RECON
84 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_P_FRAME_CHROMA_RECON
85 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_LUMA_RECON
86 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_CHROMA_RECON
87 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_PREPROC
88 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_ENC_WP
89 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_I_MBENC
90 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_CSC_DS_COPY
91 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_2X_4X_SCALING
92 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_HEVC_LCU64_B_MBENC
93 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_MB_BRC_UPDATE
94 { 1, 0, 8, 0 }, // CODECHAL_MEDIA_STATE_STATIC_FRAME_DETECTION
95 { 1, 0, 8, 0 },
96 { 1, 0, 8, 0 },
97 { 1, 0, 8, 0 },
98 { 1, 0, 8, 0 },
99 { 2, 3, 8, 0 },
100 { 2, 3, 8, 0 },
101 { 2, 3, 8, 0 },
102 { 2, 3, 8, 0 },
103 };
104
CodechalHwInterfaceXe2_Lpm_Base(PMOS_INTERFACE osInterface,CODECHAL_FUNCTION codecFunction,MhwInterfacesNext * mhwInterfacesNext,bool disableScalability)105 CodechalHwInterfaceXe2_Lpm_Base::CodechalHwInterfaceXe2_Lpm_Base(
106 PMOS_INTERFACE osInterface,
107 CODECHAL_FUNCTION codecFunction,
108 MhwInterfacesNext *mhwInterfacesNext,
109 bool disableScalability)
110 : CodechalHwInterfaceNext(osInterface, codecFunction, mhwInterfacesNext, disableScalability)
111 {
112 CODEC_HW_FUNCTION_ENTER;
113
114 m_mediaSfcItf = std::make_shared<MediaSfcInterface>(m_osInterface);
115 InitCacheabilityControlSettings(codecFunction);
116
117 if (GetHcpInterfaceNext())
118 {
119 m_hcpItf = GetHcpInterfaceNext();
120 ENCODE_CHK_NULL_NO_STATUS_RETURN(m_hcpItf);
121 }
122 m_isVdencSuperSliceEnabled = true;
123
124 m_ssEuTable = m_defaultSsEuLutM15;
125 m_numMediaStates = CODECHAL_NUM_MEDIA_STATES_XE2_LPM;
126
127 // Set platform dependent parameters
128 m_sizeOfCmdBatchBufferEnd = m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)();
129 m_sizeOfCmdMediaReset = m_miItf->MHW_GETSIZE_F(MI_LOAD_REGISTER_IMM)() * 8;
130 m_vdencBrcImgStateBufferSize = m_vdencItf->MHW_GETSIZE_F(VDENC_AVC_IMG_STATE)()
131 + m_mfxItf->MHW_GETSIZE_F(MFX_AVC_IMG_STATE)()
132 + m_vdencItf->MHW_GETSIZE_F(VDENC_CMD3)()
133 + m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)();
134
135 m_vdencBatchBuffer1stGroupSize = m_hcpItf->MHW_GETSIZE_F(HCP_PIPE_MODE_SELECT)()
136 + m_miItf->MHW_GETSIZE_F(MFX_WAIT)() * 2
137 + m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)();
138
139 m_vdencBatchBuffer2ndGroupSize = m_vdencItf->MHW_GETSIZE_F(VDENC_CMD1)()
140 + m_hcpItf->MHW_GETSIZE_F(HCP_PIC_STATE)()
141 + m_vdencItf->MHW_GETSIZE_F(VDENC_CMD2)()
142 + m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)();
143
144 m_vdencReadBatchBufferSize =
145 m_vdenc2ndLevelBatchBufferSize = m_vdencBatchBuffer1stGroupSize
146 + m_vdencBatchBuffer2ndGroupSize
147 + ENCODE_HEVC_VDENC_NUM_MAX_SLICES
148 * (2 * m_hcpItf->MHW_GETSIZE_F(HCP_WEIGHTOFFSET_STATE)()
149 + m_hcpItf->MHW_GETSIZE_F(HCP_SLICE_STATE)()
150 + (HEVC_MAX_NAL_UNIT_TYPE + 2) * m_hcpItf->MHW_GETSIZE_F(HCP_PAK_INSERT_OBJECT)()
151 + m_vdencItf->MHW_GETSIZE_F(VDENC_WEIGHTSOFFSETS_STATE)()
152 + m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)()
153 + 4 * ENCODE_VDENC_HEVC_PADDING_DW_SIZE);
154
155 m_HucStitchCmdBatchBufferSize = 7 * 4
156 + 14 * 4
157 + m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)();
158
159 // HCP_WEIGHTOFFSET_STATE_CMD cmds is planned to be added in near future
160 m_vdencBatchBufferPerSliceConstSize = m_hcpItf->MHW_GETSIZE_F(HCP_SLICE_STATE)()
161 + m_hcpItf->MHW_GETSIZE_F(HCP_PAK_INSERT_OBJECT)() // 1st PakInsertObject cmd is not always inserted for each slice, 2nd PakInsertObject cmd is always inserted for each slice
162 + m_vdencItf->MHW_GETSIZE_F(VDENC_WEIGHTSOFFSETS_STATE)()
163 + m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)();
164
165 // Set to size of the BRC update command buffer, since it is larger than BRC Init/ PAK integration commands
166 m_hucCommandBufferSize = m_hucItf->MHW_GETSIZE_F(HUC_IMEM_STATE)()
167 + m_hucItf->MHW_GETSIZE_F(HUC_PIPE_MODE_SELECT)()
168 + m_miItf->MHW_GETSIZE_F(MFX_WAIT)() * 3
169 + m_hucItf->MHW_GETSIZE_F(HUC_DMEM_STATE)()
170 + m_hucItf->MHW_GETSIZE_F(HUC_VIRTUAL_ADDR_STATE)()
171 + m_hucItf->MHW_GETSIZE_F(HUC_STREAM_OBJECT)()
172 + m_miItf->MHW_GETSIZE_F(MI_STORE_DATA_IMM)()
173 + m_miItf->MHW_GETSIZE_F(MI_STORE_REGISTER_MEM)()
174 + m_hucItf->MHW_GETSIZE_F(HUC_START)()
175 + m_vdencItf->MHW_GETSIZE_F(VD_PIPELINE_FLUSH)()
176 + m_miItf->MHW_GETSIZE_F(MI_FLUSH_DW)()
177 + m_miItf->MHW_GETSIZE_F(MI_STORE_DATA_IMM)() * 2
178 + m_miItf->MHW_GETSIZE_F(MI_STORE_REGISTER_MEM)() * 2
179 + m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)();
180
181 // No kernel used on xe2 lpm
182 m_maxKernelLoadCmdSize = 0;
183
184 m_sizeOfCmdMediaObject = 0;
185 m_sizeOfCmdMediaStateFlush = 0;
186 }
187
SetCacheabilitySettings(MHW_MEMORY_OBJECT_CONTROL_PARAMS cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_END_CODEC])188 MOS_STATUS CodechalHwInterfaceXe2_Lpm_Base::SetCacheabilitySettings(
189 MHW_MEMORY_OBJECT_CONTROL_PARAMS cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_END_CODEC])
190 {
191 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
192
193 CODEC_HW_FUNCTION_ENTER;
194
195 CodechalHwInterfaceNext::SetCacheabilitySettings(cacheabilitySettings);
196
197 return eStatus;
198 }
199
SetRowstoreCachingOffsets(PMHW_VDBOX_ROWSTORE_PARAMS rowstoreParams)200 MOS_STATUS CodechalHwInterfaceXe2_Lpm_Base::SetRowstoreCachingOffsets(
201 PMHW_VDBOX_ROWSTORE_PARAMS rowstoreParams)
202 {
203 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
204
205 CODEC_HW_FUNCTION_ENTER;
206
207 CODEC_HW_CHK_STATUS_RETURN(CodechalHwInterfaceNext::SetRowstoreCachingOffsets(rowstoreParams));
208 if (GetMfxInterfaceNext())
209 {
210 CODEC_HW_CHK_STATUS_RETURN(GetMfxInterfaceNext()->GetRowstoreCachingAddrs(rowstoreParams));
211 }
212
213 if (GetVvcpInterfaceNext())
214 {
215 CODEC_HW_CHK_STATUS_RETURN(GetVvcpInterfaceNext()->GetRowstoreCachingAddrs(rowstoreParams));
216 }
217
218 return eStatus;
219 }
220
GetAvpStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)221 MOS_STATUS CodechalHwInterfaceXe2_Lpm_Base::GetAvpStateCommandSize(
222 uint32_t mode,
223 uint32_t *commandsSize,
224 uint32_t *patchListSize,
225 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
226 {
227 CODEC_HW_FUNCTION_ENTER;
228
229 //calculate AVP related commands size
230 uint32_t avpCommandsSize = 0;
231 uint32_t avpPatchListSize = 0;
232 uint32_t cpCmdsize = 0;
233 uint32_t cpPatchListSize = 0;
234
235 if (GetAvpInterfaceNext() != nullptr)
236 {
237 CODEC_HW_CHK_STATUS_RETURN(GetAvpInterfaceNext()->GetAvpStateCmdSize(
238 (uint32_t *)&avpCommandsSize,
239 (uint32_t *)&avpPatchListSize,
240 params));
241 }
242
243 if (m_cpInterface != nullptr)
244 {
245 m_cpInterface->GetCpStateLevelCmdSize(cpCmdsize, cpPatchListSize);
246 }
247
248 //Calc final command size
249 *commandsSize = avpCommandsSize + cpCmdsize;
250 *patchListSize = avpPatchListSize + cpPatchListSize;
251
252 return MOS_STATUS_SUCCESS;
253 }
254
GetAvpPrimitiveCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize)255 MOS_STATUS CodechalHwInterfaceXe2_Lpm_Base::GetAvpPrimitiveCommandSize(
256 uint32_t mode,
257 uint32_t *commandsSize,
258 uint32_t *patchListSize)
259 {
260 CODEC_HW_FUNCTION_ENTER;
261
262 //calculate AVP related commands size
263 uint32_t avpCommandsSize = 0;
264 uint32_t avpPatchListSize = 0;
265 uint32_t cpCmdsize = 0;
266 uint32_t cpPatchListSize = 0;
267
268 if (GetAvpInterfaceNext() != nullptr)
269 {
270 MHW_VDBOX_STATE_CMDSIZE_PARAMS stateCmdSizeParams;
271 CODEC_HW_CHK_STATUS_RETURN(GetAvpInterfaceNext()->GetAvpPrimitiveCmdSize(
272 (uint32_t*)&avpCommandsSize,
273 (uint32_t*)&avpPatchListSize,
274 &stateCmdSizeParams));
275 }
276
277 if (m_cpInterface != nullptr)
278 {
279 m_cpInterface->GetCpSliceLevelCmdSize(cpCmdsize, cpPatchListSize);
280 }
281
282 //Calc final command size
283 *commandsSize = avpCommandsSize + cpCmdsize;
284 *patchListSize = avpPatchListSize + cpPatchListSize;
285
286 return MOS_STATUS_SUCCESS;
287 }
288
289
SendCondBbEndCmd(PMOS_RESOURCE resource,uint32_t offset,uint32_t compData,bool disableCompMask,bool enableEndCurrentBatchBuffLevel,uint32_t compareOperation,PMOS_COMMAND_BUFFER cmdBuffer)290 MOS_STATUS CodechalHwInterfaceXe2_Lpm_Base::SendCondBbEndCmd(
291 PMOS_RESOURCE resource,
292 uint32_t offset,
293 uint32_t compData,
294 bool disableCompMask,
295 bool enableEndCurrentBatchBuffLevel,
296 uint32_t compareOperation,
297 PMOS_COMMAND_BUFFER cmdBuffer)
298 {
299 CODEC_HW_FUNCTION_ENTER;
300
301 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
302
303 if (!Mos_ResourceIsNull(&m_conditionalBbEndDummy))
304 {
305 auto &par = GetMiInterfaceNext()->GETPAR_MI_FLUSH_DW();
306 par = {};
307 par.postSyncOperation = 1;
308 par.pOsResource = &m_conditionalBbEndDummy;
309 par.dwDataDW1 = 0;
310 CODEC_HW_CHK_STATUS_RETURN(GetMiInterfaceNext()->ADDCMD_MI_FLUSH_DW(cmdBuffer));
311 }
312
313 auto &par = GetMiInterfaceNext()->GETPAR_MI_CONDITIONAL_BATCH_BUFFER_END();
314 par = {};
315 par.presSemaphoreBuffer = resource;
316 par.dwOffset = offset;
317 par.dwValue = compData;
318 par.bDisableCompareMask = disableCompMask;
319 par.dwParamsType = mhw::mi::MHW_MI_ENHANCED_CONDITIONAL_BATCH_BUFFER_END_PARAMS::ENHANCED_PARAMS;
320 if (enableEndCurrentBatchBuffLevel)
321 {
322 par.enableEndCurrentBatchBuffLevel = enableEndCurrentBatchBuffLevel;
323 par.compareOperation = compareOperation;
324 }
325 eStatus = GetMiInterfaceNext()->ADDCMD_MI_CONDITIONAL_BATCH_BUFFER_END(cmdBuffer);
326
327 return eStatus;
328 }
329
Initialize(CodechalSetting * settings)330 MOS_STATUS CodechalHwInterfaceXe2_Lpm_Base::Initialize(
331 CodechalSetting *settings)
332 {
333 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
334
335 CODEC_HW_FUNCTION_ENTER;
336
337 CODEC_HW_CHK_STATUS_RETURN(CodechalHwInterfaceNext::Initialize(settings));
338
339 //Initialize renderHal
340 m_renderHal = (PRENDERHAL_INTERFACE)MOS_AllocAndZeroMemory(sizeof(RENDERHAL_INTERFACE));
341 CODEC_HW_CHK_NULL_RETURN(m_renderHal);
342 CODEC_HW_CHK_STATUS_RETURN(RenderHal_InitInterface(
343 m_renderHal,
344 &m_renderHalCpInterface,
345 m_osInterface));
346
347 RENDERHAL_SETTINGS RenderHalSettings;
348 RenderHalSettings.iMediaStates = 32;
349 CODEC_HW_CHK_STATUS_RETURN(m_renderHal->pfnInitialize(m_renderHal, &RenderHalSettings));
350
351 //set SSEU table
352 m_renderHal->sseuTable = m_ssEuTable;
353
354 return eStatus;
355 }
356
GetVvcpStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)357 MOS_STATUS CodechalHwInterfaceXe2_Lpm_Base::GetVvcpStateCommandSize(
358 uint32_t mode,
359 uint32_t *commandsSize,
360 uint32_t *patchListSize,
361 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
362 {
363 CODEC_HW_FUNCTION_ENTER;
364
365 //calculate VVCP related commands size
366 uint32_t vvcpCommandsSize = 0;
367 uint32_t vvcpPatchListSize = 0;
368 uint32_t cpCmdsize = 0;
369 uint32_t cpPatchListSize = 0;
370
371 if (GetVvcpInterfaceNext())
372 {
373 CODEC_HW_CHK_STATUS_RETURN(GetVvcpInterfaceNext()->GetVvcpStateCmdSize(
374 (uint32_t *)&vvcpCommandsSize,
375 (uint32_t *)&vvcpPatchListSize,
376 params));
377 }
378
379 if (m_cpInterface)
380 {
381 m_cpInterface->GetCpStateLevelCmdSize(cpCmdsize, cpPatchListSize);
382 }
383
384 //Calc final command size
385 *commandsSize = vvcpCommandsSize + cpCmdsize;
386 *patchListSize = vvcpPatchListSize + cpPatchListSize;
387
388 return MOS_STATUS_SUCCESS;
389 }
390
GetVvcpPrimitiveCommandSize(uint32_t mode,uint32_t * sliceCommandsSize,uint32_t * slicePatchListSize,uint32_t * tileCommandsSize,uint32_t * tilePatchListSize)391 MOS_STATUS CodechalHwInterfaceXe2_Lpm_Base::GetVvcpPrimitiveCommandSize(
392 uint32_t mode,
393 uint32_t *sliceCommandsSize,
394 uint32_t *slicePatchListSize,
395 uint32_t *tileCommandsSize,
396 uint32_t *tilePatchListSize)
397 {
398 CODEC_HW_FUNCTION_ENTER;
399
400 //calculate VVCP related commands size
401 uint32_t vvcpSliceCommandsSize = 0;
402 uint32_t vvcpSlicePatchListSize = 0;
403 uint32_t vvcpTileCommandsSize = 0;
404 uint32_t vvcpTilePatchListSize = 0;
405 uint32_t cpCmdsize = 0;
406 uint32_t cpPatchListSize = 0;
407
408 if (GetVvcpInterfaceNext())
409 {
410 CODEC_HW_CHK_STATUS_RETURN(GetVvcpInterfaceNext()->GetVvcpPrimitiveCmdSize(
411 (uint32_t*)&vvcpSliceCommandsSize,
412 (uint32_t*)&vvcpSlicePatchListSize,
413 (uint32_t*)&vvcpTileCommandsSize,
414 (uint32_t*)&vvcpTilePatchListSize));
415 }
416
417 if (m_cpInterface)
418 {
419 m_cpInterface->GetCpSliceLevelCmdSize(cpCmdsize, cpPatchListSize);
420 }
421
422 //Calc final command size
423 *sliceCommandsSize = vvcpSliceCommandsSize + cpCmdsize;
424 *slicePatchListSize = vvcpSlicePatchListSize + cpPatchListSize;
425 *tileCommandsSize = vvcpTileCommandsSize;
426 *tilePatchListSize = vvcpTilePatchListSize;
427
428 return MOS_STATUS_SUCCESS;
429 }
430
~CodechalHwInterfaceXe2_Lpm_Base()431 CodechalHwInterfaceXe2_Lpm_Base::~CodechalHwInterfaceXe2_Lpm_Base()
432 {
433 if (m_renderHal != nullptr && m_renderHal->pfnDestroy != nullptr)
434 {
435 MOS_STATUS eStatus = m_renderHal->pfnDestroy(m_renderHal);
436 if (eStatus != MOS_STATUS_SUCCESS)
437 {
438 MHW_ASSERTMESSAGE("Failed to destroy RenderHal, eStatus:%d.\n", eStatus);
439 }
440
441 if (m_renderHalCpInterface)
442 {
443 MOS_Delete(m_renderHalCpInterface);
444 m_renderHalCpInterface = nullptr;
445 }
446
447 MOS_FreeMemory(m_renderHal);
448 m_renderHal = nullptr;
449 }
450 }
451
GetHcpStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)452 MOS_STATUS CodechalHwInterfaceXe2_Lpm_Base::GetHcpStateCommandSize(
453 uint32_t mode,
454 uint32_t * commandsSize,
455 uint32_t * patchListSize,
456 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
457 {
458 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
459
460 CODEC_HW_FUNCTION_ENTER;
461
462 uint32_t standard = CodecHal_GetStandardFromMode(mode);
463
464 uint32_t hcpCommandsSize = 0;
465 uint32_t hcpPatchListSize = 0;
466 uint32_t cpCmdsize = 0;
467 uint32_t cpPatchListSize = 0;
468
469 if (m_hcpItf && (standard == CODECHAL_HEVC || standard == CODECHAL_VP9))
470 {
471 CODEC_HW_CHK_STATUS_RETURN(m_hcpItf->GetHcpStateCommandSize(
472 mode, &hcpCommandsSize, &hcpPatchListSize, params));
473
474 m_cpInterface->GetCpStateLevelCmdSize(cpCmdsize, cpPatchListSize);
475 }
476
477 *commandsSize = hcpCommandsSize + cpCmdsize;
478 *patchListSize = hcpPatchListSize + cpPatchListSize;
479
480 return eStatus;
481 }