1 /*===================== begin_copyright_notice ==================================
2
3 # Copyright (c) 2020-2021, Intel Corporation
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12 # The above copyright notice and this permission notice shall be included
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23 ======================= end_copyright_notice ==================================*/
24 //!
25 //! \file codechal_hw_xe_xpm.cpp
26 //! \brief Implements HW interface layer for XeHP used on all OSs.
27 //! \details Implements HW interface layer for XeHP to be used on on all operating systems/DDIs, across CODECHAL components.
28 //! This module must not contain any OS dependent code.
29 //!
30
31 #include "codechal_hw_xe_xpm.h"
32 #include "codechal_hw_g12_X.h"
33 #include "mhw_render_g12_X.h"
34 #include "mhw_vdbox_hcp_hwcmd_g12_X.h" // temporary include for calculating size of various hardware commands
35 #include "mhw_vdbox_vdenc_g12_X.h"
36 #include "mhw_vdbox_hcp_g12_X.h"
37 #include "media_interfaces_g12_tgllp.h"// temporary include for getting avp interface
38 #include "media_interfaces_xehp_sdv.h"//temporary include for getting avp interface
39 #if defined(ENABLE_KERNELS) && !defined(_FULL_OPEN_SOURCE)
40 #include "Xe_XPM_Film_Grain.h"
41 #endif
42
CodechalHwInterfaceXe_Xpm(PMOS_INTERFACE osInterface,CODECHAL_FUNCTION codecFunction,MhwInterfaces * mhwInterfaces,bool disableScalability)43 CodechalHwInterfaceXe_Xpm::CodechalHwInterfaceXe_Xpm(
44 PMOS_INTERFACE osInterface,
45 CODECHAL_FUNCTION codecFunction,
46 MhwInterfaces *mhwInterfaces,
47 bool disableScalability)
48 : CodechalHwInterfaceG12(osInterface, codecFunction, mhwInterfaces, disableScalability)
49 {
50 CODECHAL_HW_FUNCTION_ENTER;
51
52
53 m_avpInterface = static_cast<MhwInterfacesXehp_Sdv*>(mhwInterfaces)->m_avpInterface;
54
55 m_bltState = MOS_New(BltStateXe_Xpm, m_osInterface);
56 if(m_bltState != nullptr)
57 {
58 m_bltState->Initialize();
59 }
60 else
61 {
62 MHW_ASSERTMESSAGE("Invalid(nullptr) BltStateXe_Xpm!");
63 }
64
65 InitCacheabilityControlSettings(codecFunction);
66
67 m_isVdencSuperSliceEnabled = true;
68
69 m_ssEuTable = m_defaultSsEuLutG12;
70
71 // Set platform dependent parameters
72 m_sizeOfCmdBatchBufferEnd = mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
73 m_sizeOfCmdMediaReset = mhw_mi_g12_X::MI_LOAD_REGISTER_IMM_CMD::byteSize * 8;
74 m_vdencBrcImgStateBufferSize = 80
75 + mhw_vdbox_mfx_g12_X::MFX_AVC_IMG_STATE_CMD::byteSize
76 + 92
77 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
78
79 m_vdencBatchBuffer1stGroupSize = mhw_vdbox_hcp_g12_X::HCP_PIPE_MODE_SELECT_CMD::byteSize
80 + mhw_mi_g12_X::MFX_WAIT_CMD::byteSize * 2
81 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
82
83 m_vdencBatchBuffer2ndGroupSize = 128
84 + mhw_vdbox_hcp_g12_X::HCP_PIC_STATE_CMD::byteSize
85 + 216
86 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
87
88 m_vdencReadBatchBufferSize =
89 m_vdenc2ndLevelBatchBufferSize = m_vdencBatchBuffer1stGroupSize
90 + m_vdencBatchBuffer2ndGroupSize
91 + ENCODE_HEVC_VDENC_NUM_MAX_SLICES
92 * (2 * mhw_vdbox_hcp_g12_X::HCP_WEIGHTOFFSET_STATE_CMD::byteSize
93 + mhw_vdbox_hcp_g12_X::HCP_SLICE_STATE_CMD::byteSize
94 + 3 * mhw_vdbox_hcp_g12_X::HCP_PAK_INSERT_OBJECT_CMD::byteSize
95 + mhw_vdbox_vdenc_g12_X::VDENC_WEIGHTSOFFSETS_STATE_CMD::byteSize
96 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize
97 + 4 * ENCODE_VDENC_HEVC_PADDING_DW_SIZE);
98
99 m_HucStitchCmdBatchBufferSize = 7 * 4
100 + 14 * 4
101 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
102
103 // HCP_WEIGHTOFFSET_STATE_CMD cmds is planned to be added in near future
104 m_vdencBatchBufferPerSliceConstSize = mhw_vdbox_hcp_g12_X::HCP_SLICE_STATE_CMD::byteSize
105 + mhw_vdbox_hcp_g12_X::HCP_PAK_INSERT_OBJECT_CMD::byteSize // 1st PakInsertObject cmd is not always inserted for each slice, 2nd PakInsertObject cmd is always inserted for each slice
106 + mhw_vdbox_vdenc_g12_X::VDENC_WEIGHTSOFFSETS_STATE_CMD::byteSize
107 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
108
109 // Set to size of the BRC update command buffer, since it is larger than BRC Init/ PAK integration commands
110 m_hucCommandBufferSize = mhw_vdbox_huc_g12_X::HUC_IMEM_STATE_CMD::byteSize
111 + mhw_vdbox_huc_g12_X::HUC_PIPE_MODE_SELECT_CMD::byteSize
112 + mhw_mi_g12_X::MFX_WAIT_CMD::byteSize * 3
113 + mhw_vdbox_huc_g12_X::HUC_DMEM_STATE_CMD::byteSize
114 + mhw_vdbox_huc_g12_X::HUC_VIRTUAL_ADDR_STATE_CMD::byteSize
115 + mhw_vdbox_huc_g12_X::HUC_STREAM_OBJECT_CMD::byteSize
116 + mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize
117 + mhw_mi_g12_X::MI_STORE_REGISTER_MEM_CMD::byteSize
118 + mhw_vdbox_huc_g12_X::HUC_START_CMD::byteSize
119 + mhw_vdbox_vdenc_g12_X::VD_PIPELINE_FLUSH_CMD::byteSize
120 + mhw_mi_g12_X::MI_FLUSH_DW_CMD::byteSize
121 + mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize * 2
122 + mhw_mi_g12_X::MI_STORE_REGISTER_MEM_CMD::byteSize * 2
123 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
124
125 m_maxKernelLoadCmdSize =
126 mhw_mi_g12_X::PIPE_CONTROL_CMD::byteSize +
127 mhw_render_g12_X::PIPELINE_SELECT_CMD::byteSize +
128 mhw_render_g12_X::MEDIA_OBJECT_CMD::byteSize +
129 mhw_render_g12_X::STATE_BASE_ADDRESS_CMD::byteSize +
130 mhw_render_g12_X::MEDIA_VFE_STATE_CMD::byteSize +
131 mhw_render_g12_X::MEDIA_CURBE_LOAD_CMD::byteSize +
132 mhw_render_g12_X::MEDIA_INTERFACE_DESCRIPTOR_LOAD_CMD::byteSize +
133 mhw_mi_g12_X::MI_BATCH_BUFFER_START_CMD::byteSize +
134 mhw_render_g12_X::MEDIA_OBJECT_WALKER_CMD::byteSize +
135 mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize;
136
137 m_sizeOfCmdMediaObject = mhw_render_g12_X::MEDIA_OBJECT_CMD::byteSize;
138 m_sizeOfCmdMediaStateFlush = mhw_mi_g12_X::MEDIA_STATE_FLUSH_CMD::byteSize;
139 }
140
141
GetFilmGrainKernelInfo(uint8_t * & kernelBase,uint32_t & kernelSize)142 MOS_STATUS CodechalHwInterfaceXe_Xpm::GetFilmGrainKernelInfo(
143 uint8_t*& kernelBase,
144 uint32_t& kernelSize)
145 {
146 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
147
148 #if defined(ENABLE_KERNELS) && !defined(_FULL_OPEN_SOURCE)
149 kernelBase = (uint8_t*)XE_XPM_FILM_GRAIN;
150 kernelSize = XE_XPM_FILM_GRAIN_SIZE;
151 #else
152 kernelBase = nullptr;
153 kernelSize = 0;
154 #endif
155
156 return eStatus;
157 }
158