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Searched defs:DCR (Results 1 – 25 of 30) sorted by relevance

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/btstack/port/stm32-wb55xx-nucleo-freertos/Drivers/CMSIS/Device/ST/STM32WBxx/Include/
H A Dstm32wb55xx.h430 …__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset… member
630 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32wb50xx.h577 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
/btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Device/ST/STM32F4xx/Include/
H A Dstm32f412zx.h636 …__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0… member
674 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32f412vx.h636 …__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0… member
674 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32f412rx.h636 …__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0… member
674 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32f410rx.h496 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32f410tx.h493 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32f410cx.h496 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32f446xx.h710 …__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0… member
766 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32f413xx.h697 …__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0… member
735 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32f423xx.h698 …__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0… member
736 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32f411xe.h491 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32f401xe.h490 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32f401xc.h490 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32f469xx.h912 …__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0… member
950 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32f479xx.h913 …__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0… member
951 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32f412cx.h631 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32f415xx.h652 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32f405xx.h653 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32f417xx.h748 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
H A Dstm32f407xx.h749 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
/btstack/port/stm32-l451-miromico-sx1280/Drivers/CMSIS/Device/ST/STM32L4xx/Include/
H A Dstm32l451xx.h614 …__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset… member
844 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
/btstack/port/stm32-l073rz-nucleo-em9304/Drivers/CMSIS/Device/ST/STM32L0xx/Include/
H A Dstm32l073xx.h529 …__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
/btstack/port/stm32-l476rg-nucleo-sx1280/Drivers/CMSIS/Device/ST/STM32L4xx/Include/
H A Dstm32l476xx.h667 …__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset… member
914 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
/btstack/port/stm32-f4discovery-cc256x/Drivers/CMSIS/Device/ST/STM32F4xx/Include/
H A Dstm32f407xx.h765 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member

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