1 /***********************license start*********************************** 2 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 * 23 * This Software, including technical data, may be subject to U.S. export 24 * control laws, including the U.S. Export Administration Act and its 25 * associated regulations, and may be subject to export or import 26 * regulations in other countries. 27 * 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT 31 * TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 32 * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 33 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 34 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 35 * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, 36 * QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK 37 * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 /** 41 * Functions, enumarations, and structures related to DIMM SPDs. 42 * Everything in this file is internal to libdram. 43 */ 44 45 /* data field addresses in the DDR3 SPD eeprom */ 46 typedef enum ddr3_spd_addrs { 47 DDR3_SPD_BYTES_PROGRAMMED = 0, 48 DDR3_SPD_REVISION = 1, 49 DDR3_SPD_KEY_BYTE_DEVICE_TYPE = 2, 50 DDR3_SPD_KEY_BYTE_MODULE_TYPE = 3, 51 DDR3_SPD_DENSITY_BANKS = 4, 52 DDR3_SPD_ADDRESSING_ROW_COL_BITS = 5, 53 DDR3_SPD_NOMINAL_VOLTAGE = 6, 54 DDR3_SPD_MODULE_ORGANIZATION = 7, 55 DDR3_SPD_MEMORY_BUS_WIDTH = 8, 56 DDR3_SPD_FINE_TIMEBASE_DIVIDEND_DIVISOR = 9, 57 DDR3_SPD_MEDIUM_TIMEBASE_DIVIDEND = 10, 58 DDR3_SPD_MEDIUM_TIMEBASE_DIVISOR = 11, 59 DDR3_SPD_MINIMUM_CYCLE_TIME_TCKMIN = 12, 60 DDR3_SPD_CAS_LATENCIES_LSB = 14, 61 DDR3_SPD_CAS_LATENCIES_MSB = 15, 62 DDR3_SPD_MIN_CAS_LATENCY_TAAMIN = 16, 63 DDR3_SPD_MIN_WRITE_RECOVERY_TWRMIN = 17, 64 DDR3_SPD_MIN_RAS_CAS_DELAY_TRCDMIN = 18, 65 DDR3_SPD_MIN_ROW_ACTIVE_DELAY_TRRDMIN = 19, 66 DDR3_SPD_MIN_ROW_PRECHARGE_DELAY_TRPMIN = 20, 67 DDR3_SPD_UPPER_NIBBLES_TRAS_TRC = 21, 68 DDR3_SPD_MIN_ACTIVE_PRECHARGE_LSB_TRASMIN = 22, 69 DDR3_SPD_MIN_ACTIVE_REFRESH_LSB_TRCMIN = 23, 70 DDR3_SPD_MIN_REFRESH_RECOVERY_LSB_TRFCMIN = 24, 71 DDR3_SPD_MIN_REFRESH_RECOVERY_MSB_TRFCMIN = 25, 72 DDR3_SPD_MIN_INTERNAL_WRITE_READ_CMD_TWTRMIN = 26, 73 DDR3_SPD_MIN_INTERNAL_READ_PRECHARGE_CMD_TRTPMIN = 27, 74 DDR3_SPD_UPPER_NIBBLE_TFAW = 28, 75 DDR3_SPD_MIN_FOUR_ACTIVE_WINDOW_TFAWMIN = 29, 76 DDR3_SPD_MINIMUM_CYCLE_TIME_FINE_TCKMIN = 34, 77 DDR3_SPD_MIN_CAS_LATENCY_FINE_TAAMIN = 35, 78 DDR3_SPD_MIN_RAS_CAS_DELAY_FINE_TRCDMIN = 36, 79 DDR3_SPD_MIN_ROW_PRECHARGE_DELAY_FINE_TRPMIN = 37, 80 DDR3_SPD_MIN_ACTIVE_REFRESH_LSB_FINE_TRCMIN = 38, 81 DDR3_SPD_ADDRESS_MAPPING = 63, 82 DDR3_SPD_MODULE_SERIAL_NUMBER = 122, 83 DDR3_SPD_CYCLICAL_REDUNDANCY_CODE_LOWER_NIBBLE = 126, 84 DDR3_SPD_CYCLICAL_REDUNDANCY_CODE_UPPER_NIBBLE = 127, 85 DDR3_SPD_MODULE_PART_NUMBER = 128 86 } ddr3_spd_addr_t; 87 88 /* data field addresses in the DDR4 SPD eeprom */ 89 typedef enum ddr4_spd_addrs { 90 DDR4_SPD_BYTES_PROGRAMMED = 0, 91 DDR4_SPD_REVISION = 1, 92 DDR4_SPD_KEY_BYTE_DEVICE_TYPE = 2, 93 DDR4_SPD_KEY_BYTE_MODULE_TYPE = 3, 94 DDR4_SPD_DENSITY_BANKS = 4, 95 DDR4_SPD_ADDRESSING_ROW_COL_BITS = 5, 96 DDR4_SPD_PACKAGE_TYPE = 6, 97 DDR4_SPD_OPTIONAL_FEATURES = 7, 98 DDR4_SPD_THERMAL_REFRESH_OPTIONS = 8, 99 DDR4_SPD_OTHER_OPTIONAL_FEATURES = 9, 100 DDR4_SPD_SECONDARY_PACKAGE_TYPE = 10, 101 DDR4_SPD_MODULE_NOMINAL_VOLTAGE = 11, 102 DDR4_SPD_MODULE_ORGANIZATION = 12, 103 DDR4_SPD_MODULE_MEMORY_BUS_WIDTH = 13, 104 DDR4_SPD_MODULE_THERMAL_SENSOR = 14, 105 DDR4_SPD_RESERVED_BYTE15 = 15, 106 DDR4_SPD_RESERVED_BYTE16 = 16, 107 DDR4_SPD_TIMEBASES = 17, 108 DDR4_SPD_MINIMUM_CYCLE_TIME_TCKAVGMIN = 18, 109 DDR4_SPD_MAXIMUM_CYCLE_TIME_TCKAVGMAX = 19, 110 DDR4_SPD_CAS_LATENCIES_BYTE0 = 20, 111 DDR4_SPD_CAS_LATENCIES_BYTE1 = 21, 112 DDR4_SPD_CAS_LATENCIES_BYTE2 = 22, 113 DDR4_SPD_CAS_LATENCIES_BYTE3 = 23, 114 DDR4_SPD_MIN_CAS_LATENCY_TAAMIN = 24, 115 DDR4_SPD_MIN_RAS_CAS_DELAY_TRCDMIN = 25, 116 DDR4_SPD_MIN_ROW_PRECHARGE_DELAY_TRPMIN = 26, 117 DDR4_SPD_UPPER_NIBBLES_TRAS_TRC = 27, 118 DDR4_SPD_MIN_ACTIVE_PRECHARGE_LSB_TRASMIN = 28, 119 DDR4_SPD_MIN_ACTIVE_REFRESH_LSB_TRCMIN = 29, 120 DDR4_SPD_MIN_REFRESH_RECOVERY_LSB_TRFC1MIN = 30, 121 DDR4_SPD_MIN_REFRESH_RECOVERY_MSB_TRFC1MIN = 31, 122 DDR4_SPD_MIN_REFRESH_RECOVERY_LSB_TRFC2MIN = 32, 123 DDR4_SPD_MIN_REFRESH_RECOVERY_MSB_TRFC2MIN = 33, 124 DDR4_SPD_MIN_REFRESH_RECOVERY_LSB_TRFC4MIN = 34, 125 DDR4_SPD_MIN_REFRESH_RECOVERY_MSB_TRFC4MIN = 35, 126 DDR4_SPD_MIN_FOUR_ACTIVE_WINDOW_MSN_TFAWMIN = 36, 127 DDR4_SPD_MIN_FOUR_ACTIVE_WINDOW_LSB_TFAWMIN = 37, 128 DDR4_SPD_MIN_ROW_ACTIVE_DELAY_SAME_TRRD_SMIN = 38, 129 DDR4_SPD_MIN_ROW_ACTIVE_DELAY_DIFF_TRRD_LMIN = 39, 130 DDR4_SPD_MIN_CAS_TO_CAS_DELAY_TCCD_LMIN = 40, 131 DDR4_SPD_MIN_CAS_TO_CAS_DELAY_FINE_TCCD_LMIN = 117, 132 DDR4_SPD_MIN_ACT_TO_ACT_DELAY_SAME_FINE_TRRD_LMIN = 118, 133 DDR4_SPD_MIN_ACT_TO_ACT_DELAY_DIFF_FINE_TRRD_SMIN = 119, 134 DDR4_SPD_MIN_ACT_TO_ACT_REFRESH_DELAY_FINE_TRCMIN = 120, 135 DDR4_SPD_MIN_ROW_PRECHARGE_DELAY_FINE_TRPMIN = 121, 136 DDR4_SPD_MIN_RAS_TO_CAS_DELAY_FINE_TRCDMIN = 122, 137 DDR4_SPD_MIN_CAS_LATENCY_FINE_TAAMIN = 123, 138 DDR4_SPD_MAX_CYCLE_TIME_FINE_TCKAVGMAX = 124, 139 DDR4_SPD_MIN_CYCLE_TIME_FINE_TCKAVGMIN = 125, 140 DDR4_SPD_CYCLICAL_REDUNDANCY_CODE_LOWER_NIBBLE = 126, 141 DDR4_SPD_CYCLICAL_REDUNDANCY_CODE_UPPER_NIBBLE = 127, 142 DDR4_SPD_REFERENCE_RAW_CARD = 130, 143 DDR4_SPD_UDIMM_ADDR_MAPPING_FROM_EDGE = 131, 144 DDR4_SPD_REGISTER_MANUFACTURER_ID_LSB = 133, 145 DDR4_SPD_REGISTER_MANUFACTURER_ID_MSB = 134, 146 DDR4_SPD_REGISTER_REVISION_NUMBER = 135, 147 DDR4_SPD_RDIMM_ADDR_MAPPING_FROM_REGISTER_TO_DRAM = 136, 148 DDR4_SPD_RDIMM_REGISTER_DRIVE_STRENGTH_CTL = 137, 149 DDR4_SPD_RDIMM_REGISTER_DRIVE_STRENGTH_CK = 138, 150 DDR4_SPD_MODULE_SERIAL_NUMBER = 325, 151 DDR4_SPD_MODULE_PART_NUMBER = 329 152 } ddr4_spd_addr_t; 153 154 extern int read_entire_spd(bdk_node_t node, dram_config_t *cfg, int lmc, int dimm); 155 extern int read_spd(bdk_node_t node, const dimm_config_t *dimm_config, int spd_field); 156 157 extern int validate_dimm(bdk_node_t node, const dimm_config_t *dimm_config); 158 159 extern void report_dimm(bdk_node_t node, const dimm_config_t *dimm_config, 160 int dimm, int ddr_interface_num, int num_ranks, 161 int dram_width, int dimm_size_mb); 162 163 extern int dram_get_default_spd_speed(bdk_node_t node, const ddr_configuration_t *ddr_config); 164 165 extern const char *ddr3_dimm_types[]; 166 extern const char *ddr4_dimm_types[]; 167