1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_DRAMC_PARAM_COMMON_H__ 4 #define __SOC_MEDIATEK_DRAMC_PARAM_COMMON_H__ 5 6 /* 7 * NOTE: This file is shared between coreboot and dram blob. Any change in this 8 * file should be synced to the other repository. 9 */ 10 11 #include <soc/dramc_soc.h> 12 13 enum DRAMC_PARAM_STATUS_CODES { 14 DRAMC_SUCCESS = 0, 15 DRAMC_ERR_INVALID_VERSION, 16 DRAMC_ERR_INVALID_SIZE, 17 DRAMC_ERR_INVALID_FLAGS, 18 DRAMC_ERR_RECALIBRATE, 19 DRAMC_ERR_INIT_DRAM, 20 DRAMC_ERR_COMPLEX_RW_MEM_TEST, 21 DRAMC_ERR_1ST_COMPLEX_RW_MEM_TEST, 22 DRAMC_ERR_2ND_COMPLEX_RW_MEM_TEST, 23 DRAMC_ERR_FAST_CALIBRATION, 24 }; 25 26 enum DRAMC_PARAM_FLAG { 27 DRAMC_FLAG_HAS_SAVED_DATA = 0x0001, 28 }; 29 30 enum DRAMC_PARAM_CONFIG { 31 DRAMC_CONFIG_EMCP = 0x0001, 32 DRAMC_CONFIG_DVFS = 0x0002, 33 DRAMC_CONFIG_FAST_K = 0x0004, 34 /* Security configs */ 35 DRAMC_CONFIG_SCRAMBLE = 0x0100, 36 }; 37 38 struct dramc_param_header { 39 u16 version; /* DRAMC_PARAM_HEADER_VERSION, set in coreboot */ 40 u16 size; /* size of whole dramc_param, set in coreboot */ 41 u16 status; /* DRAMC_PARAM_STATUS_CODES, set in dram blob */ 42 u16 flags; /* DRAMC_PARAM_FLAG, set in dram blob */ 43 u16 config; /* DRAMC_PARAM_CONFIG, set in coreboot */ 44 }; 45 46 enum SDRAM_DDR_TYPE { 47 DDR_TYPE_DISCRETE, 48 DDR_TYPE_EMCP, 49 }; 50 51 enum SDRAM_DDR_GEOMETRY_TYPE { 52 DDR_TYPE_2CH_2RK_4GB_2_2, 53 DDR_TYPE_2CH_2RK_6GB_3_3, 54 DDR_TYPE_2CH_2RK_8GB_4_4_BYTE, 55 DDR_TYPE_2CH_1RK_4GB_4_0, 56 DDR_TYPE_2CH_2RK_6GB_2_4, 57 DDR_TYPE_2CH_2RK_8GB_4_4, 58 }; 59 60 struct sdram_info { 61 u32 ddr_type; /* SDRAM_DDR_TYPE */ 62 u32 ddr_geometry; /* SDRAM_DDR_GEOMETRY_TYPE */ 63 }; 64 65 struct emi_mdl { 66 u32 cona_val; 67 u32 conh_val; 68 u32 conf_val; 69 u32 chn_cona_val; 70 }; 71 72 struct ddr_mrr_info { 73 u16 mr5_vendor_id; 74 u16 mr6_revision_id; 75 u16 mr7_revision_id; 76 u64 mr8_density[RANK_MAX]; 77 u32 rank_nums; 78 u8 die_num[RANK_MAX]; 79 }; 80 81 enum SDRAM_DVFS_FLAG { 82 DRAMC_DISABLE_DVFS, 83 DRAMC_ENABLE_DVFS, 84 }; 85 86 enum SDRAM_VOLTAGE_TYPE { 87 SDRAM_VOLTAGE_NVCORE_NVDRAM, 88 SDRAM_VOLTAGE_HVCORE_HVDRAM, 89 SDRAM_VOLTAGE_LVCORE_LVDRAM, 90 }; 91 92 struct ddr_base_info { 93 u32 config_dvfs; /* SDRAM_DVFS_FLAG */ 94 struct sdram_info sdram; 95 u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */ 96 u32 support_ranks; 97 u64 rank_size[RANK_MAX]; 98 struct emi_mdl emi_config; 99 DRAM_CBT_MODE_T cbt_mode[RANK_MAX]; 100 struct ddr_mrr_info mrr_info; 101 u32 data_rate; 102 }; 103 104 const struct sdram_info *get_sdram_config(void); 105 106 #endif 107