1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 3 #ifndef __DRAMC_AO_REGS_H__ 4 #define __DRAMC_AO_REGS_H__ 5 6 #define Channel_A_DRAMC_AO_BASE_ADDRESS 0x10230000 7 #define Channel_B_DRAMC_AO_BASE_ADDRESS 0x10240000 8 9 #define DRAMC_AO_BASE_ADDRESS Channel_A_DRAMC_AO_BASE_VIRTUAL 10 11 #define DRAMC_REG_DDRCOMMON0 (DRAMC_AO_BASE_ADDRESS + 0x0000) 12 #define DDRCOMMON0_DISSTOP26M Fld(1, 0) //[0:0] 13 #define DDRCOMMON0_RANK_ASYM Fld(1, 1) //[1:1] 14 #define DDRCOMMON0_DM16BITFULL Fld(1, 2) //[2:2] 15 #define DDRCOMMON0_TRCDEARLY Fld(1, 3) //[3:3] 16 #define DDRCOMMON0_BK8EN Fld(1, 8) //[8:8] 17 #define DDRCOMMON0_BG4EN Fld(1, 11) //[11:11] 18 #define DDRCOMMON0_GDDR3EN Fld(1, 16) //[16:16] 19 #define DDRCOMMON0_LPDDR2EN Fld(1, 17) //[17:17] 20 #define DDRCOMMON0_LPDDR3EN Fld(1, 18) //[18:18] 21 #define DDRCOMMON0_LPDDR4EN Fld(1, 19) //[19:19] 22 #define DDRCOMMON0_LPDDR5EN Fld(1, 20) //[20:20] 23 #define DDRCOMMON0_DDR2EN Fld(1, 22) //[22:22] 24 #define DDRCOMMON0_DDR3EN Fld(1, 23) //[23:23] 25 #define DDRCOMMON0_DDR4EN Fld(1, 24) //[24:24] 26 #define DDRCOMMON0_DRAMC_SW_RST Fld(1, 31) //[31:31] 27 28 #define DRAMC_REG_SA_RESERVE (DRAMC_AO_BASE_ADDRESS + 0x000C) 29 #define SA_RESERVE_SINGLE_RANK Fld(1, 0) //[0:0] 30 #define SA_RESERVE_DFS_FSP_RTMRW Fld(2, 1) //[2:1] 31 #define SA_RESERVE_SUPPORT_4266 Fld(1, 3) //[3: 3] 32 #define SA_RESERVE_DRM_SHU_SRAM_LEVEL Fld(4, 4) //[7: 4] 33 #define SA_RESERVE_DRM_SHU_LEVEL Fld(1, 8) //[8:8] 34 #define SA_RESERVE_DRM_DSC_DRAM Fld(1, 9) //[9:9] 35 #define SA_RESERVE_SA_RESERVE Fld(14, 10) //[23:10] 36 #define SA_RESERVE_MODE_RK1 Fld(4, 24) //[27:24] 37 #define SA_RESERVE_MODE_RK0 Fld(4, 28) //[31:28] 38 39 #define DRAMC_REG_NONSHU_RSV (DRAMC_AO_BASE_ADDRESS + 0x00FC) 40 #define NONSHU_RSV_NONSHU_RSV Fld(32, 0) //[31:0] 41 42 #define DRAMC_REG_TEST2_A0 (DRAMC_AO_BASE_ADDRESS + 0x0100) 43 #define TEST2_A0_TEST2_PAT1 Fld(8, 0) //[7:0] 44 #define TEST2_A0_TEST2_PAT0 Fld(8, 8) //[15:8] 45 #define TEST2_A0_LOOP_NV_END Fld(1, 16) //[16:16] 46 #define TEST2_A0_ERR_BREAK_EN Fld(1, 17) //[17:17] 47 #define TEST2_A0_TA2_LOOP_EN Fld(1, 18) //[18:18] 48 #define TEST2_A0_TA2_CG_FR Fld(1, 19) //[19:19] 49 #define TEST2_A0_LOOP_CNT_INDEX Fld(4, 20) //[23:20] 50 #define TEST2_A0_WDT_BY_DRAMC_DIS Fld(1, 24) //[24:24] 51 52 #define DRAMC_REG_TEST2_A2 (DRAMC_AO_BASE_ADDRESS + 0x0104) 53 #define TEST2_A2_TEST2_OFF Fld(28, 4) //[31:4] 54 55 #define DRAMC_REG_TEST2_A3 (DRAMC_AO_BASE_ADDRESS + 0x0108) 56 #define TEST2_A3_TESTCNT Fld(4, 0) //[3:0] 57 #define TEST2_A3_TESTWRHIGH Fld(1, 4) //[4:4] 58 #define TEST2_A3_ADRDECEN_TARKMODE Fld(1, 5) //[5:5] 59 #define TEST2_A3_PSTWR2 Fld(1, 6) //[6:6] 60 #define TEST2_A3_TESTAUDPAT Fld(1, 7) //[7:7] 61 #define TEST2_A3_TESTCLKRUN Fld(1, 8) //[8:8] 62 #define TEST2_A3_ERRFLAG_BYTE_SEL Fld(2, 9) //[10:9] 63 #define TEST2_A3_PAT_SHIFT_SW_EN Fld(1, 11) //[11:11] 64 #define TEST2_A3_PAT_SHIFT_OFFSET Fld(3, 12) //[14:12] 65 #define TEST2_A3_TEST2_PAT_SHIFT Fld(1, 15) //[15:15] 66 #define TEST2_A3_TEST_AID_EN Fld(1, 16) //[16:16] 67 #define TEST2_A3_HFIDPAT Fld(1, 17) //[17:17] 68 #define TEST2_A3_AUTO_GEN_PAT Fld(1, 18) //[18:18] 69 #define TEST2_A3_LBSELFCMP Fld(1, 19) //[19:19] 70 #define TEST2_A3_DMPAT32 Fld(1, 24) //[24:24] 71 #define TEST2_A3_TESTADR_SHIFT Fld(1, 25) //[25:25] 72 #define TEST2_A3_TAHPRI_B Fld(1, 26) //[26:26] 73 #define TEST2_A3_TESTLP Fld(1, 27) //[27:27] 74 #define TEST2_A3_TEST2WREN2_HW_EN Fld(1, 28) //[28:28] 75 #define TEST2_A3_TEST1 Fld(1, 29) //[29:29] 76 #define TEST2_A3_TEST2R Fld(1, 30) //[30:30] 77 #define TEST2_A3_TEST2W Fld(1, 31) //[31:31] 78 79 #define DRAMC_REG_TEST2_A4 (DRAMC_AO_BASE_ADDRESS + 0x010C) 80 #define TEST2_A4_TESTAUDINC Fld(5, 0) //[4:0] 81 #define TEST2_A4_TEST2DISSCRAM Fld(1, 5) //[5:5] 82 #define TEST2_A4_TESTSSOPAT Fld(1, 6) //[6:6] 83 #define TEST2_A4_TESTSSOXTALKPAT Fld(1, 7) //[7:7] 84 #define TEST2_A4_TESTAUDINIT Fld(5, 8) //[12:8] 85 #define TEST2_A4_TEST2_EN1ARB_DIS Fld(1, 13) //[13:13] 86 #define TEST2_A4_TESTAUDBITINV Fld(1, 14) //[14:14] 87 #define TEST2_A4_TESTAUDMODE Fld(1, 15) //[15:15] 88 #define TEST2_A4_TESTXTALKPAT Fld(1, 16) //[16:16] 89 #define TEST2_A4_TEST_REQ_LEN1 Fld(1, 17) //[17:17] 90 #define TEST2_A4_TEST2EN1_OPT2 Fld(1, 18) //[18:18] 91 #define TEST2_A4_TEST2EN1_OPT1_DIS Fld(1, 19) //[19:19] 92 #define TEST2_A4_TEST2_DQMTGL Fld(1, 21) //[21:21] 93 #define TEST2_A4_TESTAGENTRK Fld(2, 24) //[25:24] 94 #define TEST2_A4_TESTDMITGLPAT Fld(1, 26) //[26:26] 95 #define TEST2_A4_TEST1TO4LEN1_DIS Fld(1, 27) //[27:27] 96 #define TEST2_A4_TESTAGENTRKSEL Fld(3, 28) //[30:28] 97 #define TEST2_A4_TESTAGENT_DMYRD_OPT Fld(1, 31) //[31:31] 98 99 #define DRAMC_REG_DUMMY_RD (DRAMC_AO_BASE_ADDRESS + 0x0110) 100 #define DUMMY_RD_SREF_DMYRD_MASK Fld(1, 0) //[0:0] 101 #define DUMMY_RD_DMYRDOFOEN Fld(1, 1) //[1:1] 102 #define DUMMY_RD_DUMMY_RD_SW Fld(1, 4) //[4:4] 103 #define DUMMY_RD_DMYWR_LPRI_EN Fld(1, 5) //[5:5] 104 #define DUMMY_RD_DMY_WR_DBG Fld(1, 6) //[6:6] 105 #define DUMMY_RD_DMY_RD_DBG Fld(1, 7) //[7:7] 106 #define DUMMY_RD_DRS_CNTX Fld(7, 8) //[14:8] 107 #define DUMMY_RD_DRS_SELFWAKE_DMYRD_DIS Fld(1, 15) //[15:15] 108 #define DUMMY_RD_RANK_NUM Fld(2, 16) //[17:16] 109 #define DUMMY_RD_DUMMY_RD_EN Fld(1, 20) //[20:20] 110 #define DUMMY_RD_SREF_DMYRD_EN Fld(1, 21) //[21:21] 111 #define DUMMY_RD_DQSG_DMYRD_EN Fld(1, 22) //[22:22] 112 #define DUMMY_RD_DQSG_DMYWR_EN Fld(1, 23) //[23:23] 113 #define DUMMY_RD_DUMMY_RD_PA_OPT Fld(1, 24) //[24:24] 114 #define DUMMY_RD_DMY_RD_RX_TRACK Fld(1, 25) //[25:25] 115 #define DUMMY_RD_DMYRD_HPRI_DIS Fld(1, 26) //[26:26] 116 #define DUMMY_RD_DMYRD_REORDER_DIS Fld(1, 27) //[27:27] 117 #define DUMMY_RD_RETRY_SP_RK_DIS Fld(1, 28) //[28:28] 118 119 #define DRAMC_REG_DUMMY_RD_INTV (DRAMC_AO_BASE_ADDRESS + 0x0114) 120 #define DUMMY_RD_INTV_DUMMY_RD_CNT0 Fld(1, 0) //[0:0] 121 #define DUMMY_RD_INTV_DUMMY_RD_CNT1 Fld(1, 1) //[1:1] 122 #define DUMMY_RD_INTV_DUMMY_RD_CNT2 Fld(1, 2) //[2:2] 123 #define DUMMY_RD_INTV_DUMMY_RD_CNT3 Fld(1, 3) //[3:3] 124 #define DUMMY_RD_INTV_DUMMY_RD_CNT4 Fld(1, 4) //[4:4] 125 #define DUMMY_RD_INTV_DUMMY_RD_CNT5 Fld(1, 5) //[5:5] 126 #define DUMMY_RD_INTV_DUMMY_RD_CNT6 Fld(1, 6) //[6:6] 127 #define DUMMY_RD_INTV_DUMMY_RD_CNT7 Fld(1, 7) //[7:7] 128 #define DUMMY_RD_INTV_DUMMY_RD_1_CNT0 Fld(1, 16) //[16:16] 129 #define DUMMY_RD_INTV_DUMMY_RD_1_CNT1 Fld(1, 17) //[17:17] 130 #define DUMMY_RD_INTV_DUMMY_RD_1_CNT2 Fld(1, 18) //[18:18] 131 #define DUMMY_RD_INTV_DUMMY_RD_1_CNT3 Fld(1, 19) //[19:19] 132 #define DUMMY_RD_INTV_DUMMY_RD_1_CNT4 Fld(1, 20) //[20:20] 133 #define DUMMY_RD_INTV_DUMMY_RD_1_CNT5 Fld(1, 21) //[21:21] 134 #define DUMMY_RD_INTV_DUMMY_RD_1_CNT6 Fld(1, 22) //[22:22] 135 #define DUMMY_RD_INTV_DUMMY_RD_1_CNT7 Fld(1, 23) //[23:23] 136 137 #define DRAMC_REG_BUS_MON1 (DRAMC_AO_BASE_ADDRESS + 0x0118) 138 #define BUS_MON1_WRBYTE_CNT_OPT Fld(1, 0) //[0:0] 139 140 #define DRAMC_REG_DRAMC_DBG_SEL1 (DRAMC_AO_BASE_ADDRESS + 0x011C) 141 #define DRAMC_DBG_SEL1_DEBUG_SEL_0 Fld(16, 0) //[15:0] 142 #define DRAMC_DBG_SEL1_DEBUG_SEL_1 Fld(16, 16) //[31:16] 143 144 #define DRAMC_REG_DRAMC_DBG_SEL2 (DRAMC_AO_BASE_ADDRESS + 0x0120) 145 #define DRAMC_DBG_SEL2_DEBUG_SEL_2 Fld(16, 0) //[15:0] 146 #define DRAMC_DBG_SEL2_DEBUG_SEL_3 Fld(16, 16) //[31:16] 147 148 #define DRAMC_REG_SWCMD_EN (DRAMC_AO_BASE_ADDRESS + 0x0124) 149 #define SWCMD_EN_MPRWEN Fld(1, 0) //[0:0] 150 #define SWCMD_EN_STESTEN Fld(1, 1) //[1:1] 151 #define SWCMD_EN_MPCMANEN Fld(1, 2) //[2:2] 152 #define SWCMD_EN_PREAEN Fld(1, 3) //[3:3] 153 #define SWCMD_EN_ACTEN Fld(1, 4) //[4:4] 154 #define SWCMD_EN_RDDQCEN Fld(1, 5) //[5:5] 155 #define SWCMD_EN_WRFIFOEN Fld(1, 6) //[6:6] 156 #define SWCMD_EN_RDFIFOEN Fld(1, 7) //[7:7] 157 #define SWCMD_EN_DQSOSCDISEN Fld(1, 8) //[8:8] 158 #define SWCMD_EN_DQSOSCENEN Fld(1, 9) //[9:9] 159 #define SWCMD_EN_ZQLATEN Fld(1, 10) //[10:10] 160 #define SWCMD_EN_MRWEN Fld(1, 11) //[11:11] 161 #define SWCMD_EN_MRREN Fld(1, 12) //[12:12] 162 #define SWCMD_EN_AREFEN Fld(1, 13) //[13:13] 163 #define SWCMD_EN_ZQCEN Fld(1, 14) //[14:14] 164 #define SWCMD_EN_SPREA_EN Fld(1, 15) //[15:15] 165 #define SWCMD_EN_ZQCEN_SWTRIG Fld(1, 16) //[16:16] 166 #define SWCMD_EN_ZQLATEN_SWTRIG Fld(1, 17) //[17:17] 167 #define SWCMD_EN_WCK2DQI_START_SWTRIG Fld(1, 18) //[18:18] 168 #define SWCMD_EN_WCK2DQO_START_SWTRIG Fld(1, 19) //[19:19] 169 #define SWCMD_EN_ZQ_SW Fld(1, 20) //[20:20] 170 #define SWCMD_EN_WCK2DQ_SW Fld(1, 21) //[21:21] 171 #define SWCMD_EN_SWCMDEN_RESERVED87 Fld(2, 22) //[23:22] 172 #define SWCMD_EN_RTMRWEN Fld(1, 24) //[24:24] 173 #define SWCMD_EN_RTSWCMDEN Fld(1, 25) //[25:25] 174 #define SWCMD_EN_RTSWCMD_SEL Fld(6, 26) //[31:26] 175 176 #define DRAMC_REG_SWCMD_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x0128) 177 #define SWCMD_CTRL0_MRSOP Fld(8, 0) //[7:0] 178 #define SWCMD_CTRL0_MRSMA Fld(13, 8) //[20:8] 179 #define SWCMD_CTRL0_MRSBA Fld(3, 21) //[23:21] 180 #define SWCMD_CTRL0_MRSRK Fld(2, 24) //[25:24] 181 #define SWCMD_CTRL0_MRRRK Fld(2, 26) //[27:26] 182 #define SWCMD_CTRL0_MRSBG Fld(2, 28) //[29:28] 183 #define SWCMD_CTRL0_SWTRIG_ZQ_RK Fld(1, 30) //[30:30] 184 185 #define DRAMC_REG_SWCMD_CTRL1 (DRAMC_AO_BASE_ADDRESS + 0x012C) 186 #define SWCMD_CTRL1_RDDQC_LP_INTV Fld(2, 0) //[1:0] 187 #define SWCMD_CTRL1_RDDQC_LP_ENB Fld(1, 2) //[2:2] 188 #define SWCMD_CTRL1_ACTEN_BK Fld(3, 3) //[5:3] 189 #define SWCMD_CTRL1_ACTEN_ROW_R17_R16 Fld(2, 22) //[22:23] //Lewis add for ppr 190 #define SWCMD_CTRL1_ACTEN_ROW Fld(18, 6) //[23:6] 191 #define SWCMD_CTRL1_WRFIFO_MODE2 Fld(1, 31) //[31:31] 192 193 #define DRAMC_REG_SWCMD_CTRL2 (DRAMC_AO_BASE_ADDRESS + 0x0130) 194 #define SWCMD_CTRL2_RTSWCMD_AGE Fld(10, 0) //[9:0] 195 #define SWCMD_CTRL2_RTSWCMD_RK Fld(2, 10) //[11:10] 196 #define SWCMD_CTRL2_RTSWCMD_MA Fld(8, 12) //[19:12] 197 #define SWCMD_CTRL2_RTSWCMD_OP Fld(8, 20) //[27:20] 198 #define SWCMD_CTRL2_RTSWCMD_ALLTYPE_OPT Fld(1, 28) //[28:28] 199 200 #define DRAMC_REG_RDDQCGOLDEN1 (DRAMC_AO_BASE_ADDRESS + 0x0134) 201 #define RDDQCGOLDEN1_LP5_MR20_6_GOLDEN Fld(1, 0) //[0:0] 202 #define RDDQCGOLDEN1_LP5_MR20_7_GOLDEN Fld(1, 1) //[1:1] 203 204 #define DRAMC_REG_RDDQCGOLDEN (DRAMC_AO_BASE_ADDRESS + 0x0138) 205 #define RDDQCGOLDEN_MR20_GOLDEN Fld(8, 0) //[7:0] 206 #define RDDQCGOLDEN_MR15_GOLDEN Fld(8, 8) //[15:8] 207 #define RDDQCGOLDEN_MR40_GOLDEN Fld(8, 16) //[23:16] 208 #define RDDQCGOLDEN_MR32_GOLDEN Fld(8, 24) //[31:24] 209 210 #define DRAMC_REG_RTMRW_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x013C) 211 #define RTMRW_CTRL0_RTMRW0_RK Fld(2, 0) //[1:0] 212 #define RTMRW_CTRL0_RTMRW1_RK Fld(2, 2) //[3:2] 213 #define RTMRW_CTRL0_RTMRW2_RK Fld(2, 4) //[5:4] 214 #define RTMRW_CTRL0_RTMRW3_RK Fld(2, 6) //[7:6] 215 #define RTMRW_CTRL0_RTMRW4_RK Fld(2, 8) //[9:8] 216 #define RTMRW_CTRL0_RTMRW5_RK Fld(2, 10) //[11:10] 217 #define RTMRW_CTRL0_RTMRW_LEN Fld(3, 12) //[14:12] 218 #define RTMRW_CTRL0_RTMRW_AGE Fld(10, 15) //[24:15] 219 #define RTMRW_CTRL0_RTMRW_LAT Fld(7, 25) //[31:25] 220 221 #define DRAMC_REG_RTMRW_CTRL1 (DRAMC_AO_BASE_ADDRESS + 0x0140) 222 #define RTMRW_CTRL1_RTMRW0_MA Fld(8, 0) //[7:0] 223 #define RTMRW_CTRL1_RTMRW1_MA Fld(8, 8) //[15:8] 224 #define RTMRW_CTRL1_RTMRW2_MA Fld(8, 16) //[23:16] 225 #define RTMRW_CTRL1_RTMRW3_MA Fld(8, 24) //[31:24] 226 227 #define DRAMC_REG_RTMRW_CTRL2 (DRAMC_AO_BASE_ADDRESS + 0x0144) 228 #define RTMRW_CTRL2_RTMRW0_OP Fld(8, 0) //[7:0] 229 #define RTMRW_CTRL2_RTMRW1_OP Fld(8, 8) //[15:8] 230 #define RTMRW_CTRL2_RTMRW2_OP Fld(8, 16) //[23:16] 231 #define RTMRW_CTRL2_RTMRW3_OP Fld(8, 24) //[31:24] 232 233 #define DRAMC_REG_RTMRW_CTRL3 (DRAMC_AO_BASE_ADDRESS + 0x0148) 234 #define RTMRW_CTRL3_RTMRW4_MA Fld(8, 0) //[7:0] 235 #define RTMRW_CTRL3_RTMRW5_MA Fld(8, 8) //[15:8] 236 #define RTMRW_CTRL3_RTMRW4_OP Fld(8, 16) //[23:16] 237 #define RTMRW_CTRL3_RTMRW5_OP Fld(8, 24) //[31:24] 238 239 #define DRAMC_REG_CBT_WLEV_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x014C) 240 #define CBT_WLEV_CTRL0_CBT_CAPATEN Fld(1, 0) //[0:0] 241 #define CBT_WLEV_CTRL0_TCMDEN Fld(1, 1) //[1:1] 242 #define CBT_WLEV_CTRL0_BYTEMODECBTEN Fld(1, 2) //[2:2] 243 #define CBT_WLEV_CTRL0_WRITE_LEVEL_EN Fld(1, 3) //[3:3] 244 #define CBT_WLEV_CTRL0_DQSOEAOEN Fld(1, 4) //[4:4] 245 #define CBT_WLEV_CTRL0_CBTMASKDQSOE Fld(1, 5) //[5:5] 246 #define CBT_WLEV_CTRL0_WLEV_DQSPATEN Fld(1, 6) //[6:6] 247 #define CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG Fld(1, 7) //[7:7] 248 #define CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL Fld(4, 8) //[11:8] 249 #define CBT_WLEV_CTRL0_WLEV_DQSPAT_LAT Fld(8, 12) //[19:12] 250 #define CBT_WLEV_CTRL0_WLEV_MCK_NUM Fld(2, 20) //[21:20] 251 #define CBT_WLEV_CTRL0_WLEV_WCK_HR Fld(1, 22) //[22:22] 252 #define CBT_WLEV_CTRL0_CBT_WLEV_WCKAO Fld(1, 23) //[23:23] 253 #define CBT_WLEV_CTRL0_CBT_SW_DQM_B0_LP5 Fld(1, 24) //[24:24] 254 #define CBT_WLEV_CTRL0_CBT_SW_DQM_B1_LP5 Fld(1, 25) //[25:25] 255 #define CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN Fld(4, 26) //[29:26] 256 #define CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE Fld(1, 30) //[30:30] 257 258 #define DRAMC_REG_CBT_WLEV_CTRL1 (DRAMC_AO_BASE_ADDRESS + 0x0150) 259 #define CBT_WLEV_CTRL1_CATRAINCSEXT Fld(1, 0) //[0:0] 260 #define CBT_WLEV_CTRL1_CATRAINMRS Fld(1, 1) //[1:1] 261 #define CBT_WLEV_CTRL1_CATRAINEN Fld(1, 2) //[2:2] 262 #define CBT_WLEV_CTRL1_CATRAINLAT Fld(4, 11) //[14:11] 263 #define CBT_WLEV_CTRL1_CATRAIN_INTV Fld(8, 15) //[22:15] 264 #define CBT_WLEV_CTRL1_TCMDO1LAT Fld(8, 23) //[30:23] 265 266 #define DRAMC_REG_CBT_WLEV_CTRL2 (DRAMC_AO_BASE_ADDRESS + 0x0154) 267 #define CBT_WLEV_CTRL2_CATRAINCA Fld(16, 0) //[15:0] 268 #define CBT_WLEV_CTRL2_CATRAINCA_Y Fld(16, 16) //[31:16] 269 270 #define DRAMC_REG_CBT_WLEV_CTRL3 (DRAMC_AO_BASE_ADDRESS + 0x0158) 271 #define CBT_WLEV_CTRL3_CATRAIN_PAT_STOP0 Fld(4, 0) //[3:0] 272 #define CBT_WLEV_CTRL3_CATRAIN_PAT_STOP1 Fld(3, 4) //[6:4] 273 #define CBT_WLEV_CTRL3_CATRAIN_1PAT_SEL0 Fld(4, 7) //[10:7] 274 #define CBT_WLEV_CTRL3_CATRAIN_1PAT_SEL1 Fld(3, 11) //[13:11] 275 #define CBT_WLEV_CTRL3_DQSBX_G Fld(4, 14) //[17:14] 276 #define CBT_WLEV_CTRL3_DQSBY_G Fld(4, 18) //[21:18] 277 #define CBT_WLEV_CTRL3_DQSBX1_G Fld(4, 22) //[25:22] 278 #define CBT_WLEV_CTRL3_DQSBY1_G Fld(4, 26) //[29:26] 279 280 #define DRAMC_REG_CBT_WLEV_CTRL4 (DRAMC_AO_BASE_ADDRESS + 0x015C) 281 #define CBT_WLEV_CTRL4_CBT_TXDQ_B0 Fld(8, 0) //[7:0] 282 #define CBT_WLEV_CTRL4_CBT_TXDQ_B1 Fld(8, 8) //[15:8] 283 284 #define DRAMC_REG_CBT_WLEV_ATK_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x0160) 285 #define CBT_WLEV_ATK_CTRL0_ARPICS_SW Fld(1, 0) //[0:0] 286 #define CBT_WLEV_ATK_CTRL0_ARPICA_SW Fld(1, 1) //[1:1] 287 #define CBT_WLEV_ATK_CTRL0_ARPIDQS_SW Fld(1, 2) //[2:2] 288 #define CBT_WLEV_ATK_CTRL0_CSTRAIN_ATKEN Fld(1, 3) //[3:3] 289 #define CBT_WLEV_ATK_CTRL0_CATRAIN_ATKEN Fld(1, 4) //[4:4] 290 #define CBT_WLEV_ATK_CTRL0_WLEV_ATKEN Fld(1, 5) //[5:5] 291 #define CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_INTV Fld(5, 6) //[10:6] 292 #define CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_LENPI Fld(6, 11) //[16:11] 293 #define CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_RESPI Fld(2, 17) //[18:17] 294 #define CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_INITPI Fld(6, 19) //[24:19] 295 #define CBT_WLEV_ATK_CTRL0_CBT_ATK_CABITDBG Fld(3, 25) //[27:25] 296 297 #define DRAMC_REG_CBT_WLEV_ATK_CTRL1 (DRAMC_AO_BASE_ADDRESS + 0x0164) 298 #define CBT_WLEV_ATK_CTRL1_UICS_SW Fld(2, 0) //[1:0] 299 #define CBT_WLEV_ATK_CTRL1_UICA_SW Fld(7, 2) //[8:2] 300 #define CBT_WLEV_ATK_CTRL1_UIDQS_SW Fld(4, 9) //[12:9] 301 #define CBT_WLEV_ATK_CTRL1_UIWCK_FS_B1_RK0_SW Fld(1, 13) //[13:13] 302 #define CBT_WLEV_ATK_CTRL1_UIWCK_FS_B0_RK0_SW Fld(1, 14) //[14:14] 303 #define CBT_WLEV_ATK_CTRL1_UIWCK_FS_B1_RK1_SW Fld(1, 15) //[15:15] 304 #define CBT_WLEV_ATK_CTRL1_UIWCK_FS_B0_RK1_SW Fld(1, 16) //[16:16] 305 #define CBT_WLEV_ATK_CTRL1_CBT_ATK_CA1UI64PI Fld(1, 17) //[17:17] 306 307 #define DRAMC_REG_SREF_DPD_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0168) 308 #define SREF_DPD_CTRL_LPSM_BYPASS_B Fld(1, 7) //[7:7] 309 #define SREF_DPD_CTRL_DPDWOSC Fld(1, 8) //[8:8] 310 #define SREF_DPD_CTRL_CLR_EN Fld(1, 9) //[9:9] 311 #define SREF_DPD_CTRL_SELFREF_AUTOSAVE_EN Fld(1, 10) //[10:10] 312 #define SREF_DPD_CTRL_SREF_PRD_OPT Fld(1, 11) //[11:11] 313 #define SREF_DPD_CTRL_SREF_CG_OPT Fld(1, 12) //[12:12] 314 #define SREF_DPD_CTRL_SRFPD_DIS Fld(1, 13) //[13:13] 315 #define SREF_DPD_CTRL_SREF3_OPTION Fld(1, 14) //[14:14] 316 #define SREF_DPD_CTRL_SREF2_OPTION Fld(1, 15) //[15:15] 317 #define SREF_DPD_CTRL_SREFDLY Fld(4, 16) //[19:16] 318 #define SREF_DPD_CTRL_DSM_HW_EN Fld(1, 20) //[20:20] 319 #define SREF_DPD_CTRL_DSM_TRIGGER Fld(1, 21) //[21:21] 320 #define SREF_DPD_CTRL_SREF_HW_EN Fld(1, 22) //[22:22] 321 #define SREF_DPD_CTRL_SELFREF Fld(1, 23) //[23:23] 322 #define SREF_DPD_CTRL_DPDWAKEDCMCKE Fld(1, 25) //[25:25] 323 #define SREF_DPD_CTRL_CMDCKAR Fld(1, 26) //[26:26] 324 #define SREF_DPD_CTRL_GTDMW_SYNC_MASK Fld(1, 28) //[28:28] 325 #define SREF_DPD_CTRL_GT_SYNC_MASK Fld(1, 29) //[29:29] 326 #define SREF_DPD_CTRL_DAT_SYNC_MASK Fld(1, 30) //[30:30] 327 #define SREF_DPD_CTRL_PHY_SYNC_MASK Fld(1, 31) //[31:31] 328 329 #define DRAMC_REG_CFC_CTRL (DRAMC_AO_BASE_ADDRESS + 0x016C) 330 #define CFC_CTRL_CFC_CTRL_RESERVED Fld(1, 0) //[0:0] 331 332 #define DRAMC_REG_DLLFRZ_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0170) 333 #define DLLFRZ_CTRL_INPUTRXTRACK_BLOCK Fld(1, 0) //[0:0] 334 #define DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT Fld(1, 1) //[1:1] 335 #define DLLFRZ_CTRL_DLLFRZ_BLOCKLONG Fld(1, 2) //[2:2] 336 #define DLLFRZ_CTRL_DLLFRZIDLE4XUPD Fld(1, 3) //[3:3] 337 #define DLLFRZ_CTRL_FASTDQSG2X Fld(1, 4) //[4:4] 338 #define DLLFRZ_CTRL_FASTDQSGUPD Fld(1, 5) //[5:5] 339 #define DLLFRZ_CTRL_MANUDLLFRZ Fld(1, 6) //[6:6] 340 #define DLLFRZ_CTRL_DLLFRZ Fld(1, 7) //[7:7] 341 #define DLLFRZ_CTRL_UPDBYWR Fld(1, 8) //[8:8] 342 343 #define DRAMC_REG_MPC_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0174) 344 #define MPC_CTRL_MPC_BLOCKALE_OPT Fld(1, 0) //[0:0] 345 #define MPC_CTRL_MPC_BLOCKALE_OPT1 Fld(1, 1) //[1:1] 346 #define MPC_CTRL_MPC_BLOCKALE_OPT2 Fld(1, 2) //[2:2] 347 #define MPC_CTRL_ZQ_BLOCKALE_OPT Fld(1, 3) //[3:3] 348 #define MPC_CTRL_RW2ZQLAT_OPT Fld(1, 4) //[4:4] 349 #define MPC_CTRL_REFR_BLOCKEN Fld(1, 5) //[5:5] 350 #define MPC_CTRL_RTMRW_HPRI_EN Fld(1, 6) //[6:6] 351 #define MPC_CTRL_RTSWCMD_HPRI_EN Fld(1, 7) //[7:7] 352 353 #define DRAMC_REG_HW_MRR_FUN (DRAMC_AO_BASE_ADDRESS + 0x0178) 354 #define HW_MRR_FUN_TMRR_ENA Fld(1, 0) //[0:0] 355 #define HW_MRR_FUN_TRCDMRR_EN Fld(1, 1) //[1:1] 356 #define HW_MRR_FUN_TRPMRR_EN Fld(1, 2) //[2:2] 357 #define HW_MRR_FUN_MANTMRR_EN Fld(1, 3) //[3:3] 358 #define HW_MRR_FUN_TR2MRR_ENA Fld(1, 4) //[4:4] 359 #define HW_MRR_FUN_R2MRRHPRICTL Fld(1, 5) //[5:5] 360 #define HW_MRR_FUN_BUFEN_RFC_OPT Fld(1, 8) //[8:8] 361 #define HW_MRR_FUN_MRR_REQNOPUSH_DIS Fld(1, 9) //[9:9] 362 #define HW_MRR_FUN_MRR_BLOCK_NOR_DIS Fld(1, 10) //[10:10] 363 #define HW_MRR_FUN_MRR_HW_HIPRI Fld(1, 11) //[11:11] 364 #define HW_MRR_FUN_MRR_SPCMD_WAKE_DIS Fld(1, 12) //[12:12] 365 #define HW_MRR_FUN_TMRR_OE_OPT_DIS Fld(1, 13) //[13:13] 366 #define HW_MRR_FUN_MRR_SBR_OPT_DIS Fld(1, 14) //[14:14] 367 #define HW_MRR_FUN_MRR_INT_TIE0_DIS Fld(1, 15) //[15:15] 368 #define HW_MRR_FUN_MRR_PUSH2POP_ENA Fld(1, 16) //[16:16] 369 #define HW_MRR_FUN_MRR_PUSH2POP_CLR Fld(1, 17) //[17:17] 370 #define HW_MRR_FUN_MRR_PUSH2POP_ST_CLR Fld(1, 18) //[18:18] 371 #define HW_MRR_FUN_MRR_MADIS Fld(1, 19) //[19:19] 372 #define HW_MRR_FUN_MRR_PUSH2POP_SEL Fld(3, 20) //[22:20] 373 #define HW_MRR_FUN_MRR_SBR3_BKVA_DIS Fld(1, 23) //[23:23] 374 #define HW_MRR_FUN_MRR_DDRCLKCOMB_DIS Fld(1, 24) //[24:24] 375 #define HW_MRR_FUN_TRPRCD_DIS_OPT1 Fld(1, 25) //[25:25] 376 #define HW_MRR_FUN_TRPRCD_OPT2 Fld(1, 26) //[26:26] 377 #define HW_MRR_FUN_MRR_SBR2_QHIT_DIS Fld(1, 27) //[27:27] 378 #define HW_MRR_FUN_MRR_INPUT_BANK Fld(3, 28) //[30:28] 379 #define HW_MRR_FUN_MRR_TZQCS_DIS Fld(1, 31) //[31:31] 380 381 #define DRAMC_REG_SCHEDULER_COM (DRAMC_AO_BASE_ADDRESS + 0x017C) 382 #define SCHEDULER_COM_RWOFOEN Fld(1, 0) //[0:0] 383 #define SCHEDULER_COM_RWHPRICTL Fld(1, 4) //[4:4] 384 #define SCHEDULER_COM_RWSPLIT Fld(1, 5) //[5:5] 385 #define SCHEDULER_COM_MWHPRIEN Fld(1, 6) //[6:6] 386 #define SCHEDULER_COM_SPEC_MODE Fld(1, 7) //[7:7] 387 #define SCHEDULER_COM_DISRDPHASE1 Fld(1, 8) //[8:8] 388 #define SCHEDULER_COM_PBR2PBR_OPT Fld(1, 9) //[9:9] 389 390 #define DRAMC_REG_ACTIMING_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0190) 391 #define ACTIMING_CTRL_SEQCLKRUN3 Fld(1, 0) //[0:0] 392 #define ACTIMING_CTRL_SEQCLKRUN2 Fld(1, 1) //[1:1] 393 #define ACTIMING_CTRL_SEQCLKRUN Fld(1, 2) //[2:2] 394 #define ACTIMING_CTRL_TMRR2WDIS Fld(1, 4) //[4:4] 395 #define ACTIMING_CTRL_MRRSWUPD Fld(1, 5) //[5:5] 396 #define ACTIMING_CTRL_REFNA_OPT Fld(1, 6) //[6:6] 397 #define ACTIMING_CTRL_REFBW_FREN Fld(1, 8) //[8:8] 398 #define ACTIMING_CTRL_CLKWITRFC Fld(1, 9) //[9:9] 399 #define ACTIMING_CTRL_CHKFORPRE Fld(1, 10) //[10:10] 400 #define ACTIMING_CTRL_BC4OTF_OPT Fld(1, 11) //[11:11] 401 #define ACTIMING_CTRL_TMRRICHKDIS Fld(1, 21) //[21:21] 402 #define ACTIMING_CTRL_TMRRIBYRK_DIS Fld(1, 22) //[22:22] 403 #define ACTIMING_CTRL_MRRIOPT Fld(1, 23) //[23:23] 404 #define ACTIMING_CTRL_FASTW2R Fld(1, 24) //[24:24] 405 #define ACTIMING_CTRL_APBL2 Fld(1, 25) //[25:25] 406 #define ACTIMING_CTRL_LPDDR2_NO_INT Fld(1, 27) //[27:27] 407 408 #define DRAMC_REG_ZQ_SET0 (DRAMC_AO_BASE_ADDRESS + 0x01A0) 409 #define ZQ_SET0_ZQCSOP Fld(8, 0) //[7:0] 410 #define ZQ_SET0_ZQCSAD Fld(8, 8) //[15:8] 411 #define ZQ_SET0_ZQCS_MASK_SEL Fld(3, 16) //[18:16] 412 #define ZQ_SET0_ZQCS_MASK_SEL_CGAR Fld(1, 19) //[19:19] 413 #define ZQ_SET0_ZQMASK_CGAR Fld(1, 20) //[20:20] 414 #define ZQ_SET0_ZQCSMASK_OPT Fld(1, 21) //[21:21] 415 #define ZQ_SET0_ZQ_SRF_OPT Fld(1, 22) //[22:22] 416 #define ZQ_SET0_DM3RANK Fld(1, 23) //[23:23] 417 #define ZQ_SET0_ZQCSMASK Fld(1, 29) //[29:29] 418 #define ZQ_SET0_ZQCSDUAL Fld(1, 30) //[30:30] 419 #define ZQ_SET0_ZQCALL Fld(1, 31) //[31:31] 420 421 #define DRAMC_REG_ZQ_SET1 (DRAMC_AO_BASE_ADDRESS + 0x01A4) 422 #define ZQ_SET1_ZQCS_NONMASK_CLR Fld(1, 20) //[20:20] 423 #define ZQ_SET1_ZQCS_MASK_FIX Fld(1, 21) //[21:21] 424 #define ZQ_SET1_ZQCS_MASK_VALUE Fld(1, 22) //[22:22] 425 #define ZQ_SET1_ZQCALDISB Fld(1, 30) //[30:30] 426 #define ZQ_SET1_ZQCSDISB Fld(1, 31) //[31:31] 427 428 #define DRAMC_REG_TX_TRACKING_SET0 (DRAMC_AO_BASE_ADDRESS + 0x01B0) 429 #define TX_TRACKING_SET0_TX_TRACKING_OPT Fld(1, 15) //[15:15] 430 #define TX_TRACKING_SET0_SW_UP_TX_NOW_CASE Fld(1, 16) //[16:16] 431 #define TX_TRACKING_SET0_TXUIPI_CAL_CGAR Fld(1, 17) //[17:17] 432 #define TX_TRACKING_SET0_SHU_PRELOAD_TX_START Fld(1, 18) //[18:18] 433 #define TX_TRACKING_SET0_SHU_PRELOAD_TX_HW Fld(1, 19) //[19:19] 434 #define TX_TRACKING_SET0_APHY_CG_OPT1 Fld(1, 20) //[20:20] 435 #define TX_TRACKING_SET0_HMRRSEL_CGAR Fld(1, 21) //[21:21] 436 #define TX_TRACKING_SET0_RDDQSOSC_CGAR Fld(1, 22) //[22:22] 437 #define TX_TRACKING_SET0_DQSOSC_THRD_OPT Fld(1, 23) //[23:23] 438 #define TX_TRACKING_SET0_TX_PRECAL_RELOAD_OPT Fld(1, 24) //[24:24] 439 #define TX_TRACKING_SET0_DQSOSC_C2R_OPT Fld(1, 31) //[31:31] 440 441 #define DRAMC_REG_TX_RETRY_SET0 (DRAMC_AO_BASE_ADDRESS + 0x01C0) 442 #define TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK Fld(1, 0) //[0:0] 443 #define TX_RETRY_SET0_XSR_TX_RETRY_OPT Fld(1, 1) //[1:1] 444 #define TX_RETRY_SET0_XSR_TX_RETRY_EN Fld(1, 2) //[2:2] 445 #define TX_RETRY_SET0_XSR_TX_RETRY_SPM_MODE Fld(1, 3) //[3:3] 446 #define TX_RETRY_SET0_XSR_TX_RETRY_SW_EN Fld(1, 4) //[4:4] 447 #define TX_RETRY_SET0_TX_RETRY_UPDPI_CG_OPT Fld(1, 5) //[5:5] 448 #define TX_RETRY_SET0_TX_RETRY_SHU_RESP_OPT Fld(1, 6) //[6:6] 449 450 #define DRAMC_REG_MPC_OPTION (DRAMC_AO_BASE_ADDRESS + 0x01C8) 451 #define MPC_OPTION_MPCOP Fld(7, 8) //[14:8] 452 #define MPC_OPTION_MPCMAN_CAS2EN Fld(1, 16) //[16:16] 453 #define MPC_OPTION_MPCRKEN Fld(1, 17) //[17:17] 454 455 #define DRAMC_REG_MRR_BIT_MUX1 (DRAMC_AO_BASE_ADDRESS + 0x01D0) 456 #define MRR_BIT_MUX1_MRR_BIT0_SEL Fld(5, 0) //[4:0] 457 #define MRR_BIT_MUX1_MRR_BIT1_SEL Fld(5, 8) //[12:8] 458 #define MRR_BIT_MUX1_MRR_BIT2_SEL Fld(5, 16) //[20:16] 459 #define MRR_BIT_MUX1_MRR_BIT3_SEL Fld(5, 24) //[28:24] 460 461 #define DRAMC_REG_MRR_BIT_MUX2 (DRAMC_AO_BASE_ADDRESS + 0x01D4) 462 #define MRR_BIT_MUX2_MRR_BIT4_SEL Fld(5, 0) //[4:0] 463 #define MRR_BIT_MUX2_MRR_BIT5_SEL Fld(5, 8) //[12:8] 464 #define MRR_BIT_MUX2_MRR_BIT6_SEL Fld(5, 16) //[20:16] 465 #define MRR_BIT_MUX2_MRR_BIT7_SEL Fld(5, 24) //[28:24] 466 467 #define DRAMC_REG_MRR_BIT_MUX3 (DRAMC_AO_BASE_ADDRESS + 0x01D8) 468 #define MRR_BIT_MUX3_MRR_BIT8_SEL Fld(5, 0) //[4:0] 469 #define MRR_BIT_MUX3_MRR_BIT9_SEL Fld(5, 8) //[12:8] 470 #define MRR_BIT_MUX3_MRR_BIT10_SEL Fld(5, 16) //[20:16] 471 #define MRR_BIT_MUX3_MRR_BIT11_SEL Fld(5, 24) //[28:24] 472 473 #define DRAMC_REG_MRR_BIT_MUX4 (DRAMC_AO_BASE_ADDRESS + 0x01DC) 474 #define MRR_BIT_MUX4_MRR_BIT12_SEL Fld(5, 0) //[4:0] 475 #define MRR_BIT_MUX4_MRR_BIT13_SEL Fld(5, 8) //[12:8] 476 #define MRR_BIT_MUX4_MRR_BIT14_SEL Fld(5, 16) //[20:16] 477 #define MRR_BIT_MUX4_MRR_BIT15_SEL Fld(5, 24) //[28:24] 478 479 #define DRAMC_REG_SHUCTRL (DRAMC_AO_BASE_ADDRESS + 0x01F8) 480 #define SHUCTRL_R_DVFS_FSM_CLR Fld(1, 0) //[0:0] 481 #define SHUCTRL_DMSHU_DRAMC Fld(1, 4) //[4:4] 482 483 #define DRAMC_REG_DRAMC_PD_CTRL (DRAMC_AO_BASE_ADDRESS + 0x01FC) 484 #define DRAMC_PD_CTRL_DCMEN Fld(1, 0) //[0:0] 485 #define DRAMC_PD_CTRL_DCMEN2 Fld(1, 1) //[1:1] 486 #define DRAMC_PD_CTRL_DCMENNOTRFC Fld(1, 2) //[2:2] 487 #define DRAMC_PD_CTRL_PHYGLUECLKRUN Fld(1, 3) //[3:3] 488 #define DRAMC_PD_CTRL_PHYCLK_REFWKEN Fld(1, 4) //[4:4] 489 #define DRAMC_PD_CTRL_COMBPHY_CLKENSAME Fld(1, 5) //[5:5] 490 #define DRAMC_PD_CTRL_MIOCKCTRLOFF Fld(1, 6) //[6:6] 491 #define DRAMC_PD_CTRL_DRAMC_IDLE_DCM_FIXON Fld(1, 7) //[7:7] 492 #define DRAMC_PD_CTRL_PG_DCM_OPT Fld(1, 9) //[9:9] 493 #define DRAMC_PD_CTRL_COMB_DCM Fld(1, 10) //[10:10] 494 #define DRAMC_PD_CTRL_APHYCKCG_FIXOFF Fld(1, 12) //[12:12] 495 #define DRAMC_PD_CTRL_TCKFIXON Fld(1, 13) //[13:13] 496 #define DRAMC_PD_CTRL_PHYCLKDYNGEN Fld(1, 30) //[30:30] 497 #define DRAMC_PD_CTRL_COMBCLKCTRL Fld(1, 31) //[31:31] 498 499 #define DRAMC_REG_DCM_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x0200) 500 #define DCM_CTRL0_BCLKAR Fld(1, 2) //[2:2] 501 #define DCM_CTRL0_DBG_CKE1FIXON Fld(1, 4) //[4:4] 502 #define DCM_CTRL0_DBG_CKE1FIXOFF Fld(1, 5) //[5:5] 503 #define DCM_CTRL0_DBG_CKEFIXON Fld(1, 6) //[6:6] 504 #define DCM_CTRL0_DBG_CKEFIXOFF Fld(1, 7) //[7:7] 505 #define DCM_CTRL0_DISDMOEDIS Fld(1, 8) //[8:8] 506 #define DCM_CTRL0_IDLE_CNT_OPT Fld(1, 16) //[16:16] 507 #define DCM_CTRL0_IDLEDCM_CNT_OPT Fld(1, 17) //[17:17] 508 #define DCM_CTRL0_IDLE_COND_OPT Fld(1, 18) //[18:18] 509 510 #define DRAMC_REG_CKECTRL (DRAMC_AO_BASE_ADDRESS + 0x0204) 511 #define CKECTRL_CKE2RANK_OPT3 Fld(1, 1) //[1:1] 512 #define CKECTRL_CKE2FIXON Fld(1, 2) //[2:2] 513 #define CKECTRL_CKE2FIXOFF Fld(1, 3) //[3:3] 514 #define CKECTRL_CKE1FIXON Fld(1, 4) //[4:4] 515 #define CKECTRL_CKE1FIXOFF Fld(1, 5) //[5:5] 516 #define CKECTRL_CKEFIXON Fld(1, 6) //[6:6] 517 #define CKECTRL_CKEFIXOFF Fld(1, 7) //[7:7] 518 #define CKECTRL_CKE2RANK_OPT5 Fld(1, 8) //[8:8] 519 #define CKECTRL_CKE2RANK_OPT6 Fld(1, 9) //[9:9] 520 #define CKECTRL_CKE2RANK_OPT7 Fld(1, 10) //[10:10] 521 #define CKECTRL_CKE2RANK_OPT8 Fld(1, 11) //[11:11] 522 #define CKECTRL_CKEEXTEND Fld(1, 12) //[12:12] 523 #define CKECTRL_CKETIMER_SEL Fld(1, 13) //[13:13] 524 #define CKECTRL_FASTWAKE_SEL Fld(1, 14) //[14:14] 525 #define CKECTRL_CKEWAKE_SEL Fld(1, 15) //[15:15] 526 #define CKECTRL_CKEWAKE_SEL2 Fld(1, 16) //[16:16] 527 #define CKECTRL_CKE2RANK_OPT9 Fld(1, 17) //[17:17] 528 #define CKECTRL_CKE2RANK_OPT10 Fld(1, 18) //[18:18] 529 #define CKECTRL_CKE2RANK_OPT11 Fld(1, 19) //[19:19] 530 #define CKECTRL_CKE2RANK_OPT12 Fld(1, 20) //[20:20] 531 #define CKECTRL_CKE2RANK_OPT13 Fld(1, 21) //[21:21] 532 #define CKECTRL_CKEPBDIS Fld(1, 22) //[22:22] 533 #define CKECTRL_CKELCKFIX Fld(1, 23) //[23:23] 534 #define CKECTRL_CKE2RANK_OPT2 Fld(1, 24) //[24:24] 535 #define CKECTRL_CKE2RANK_OPT Fld(1, 25) //[25:25] 536 #define CKECTRL_RUNTIMEMRRCKEFIX Fld(1, 27) //[27:27] 537 #define CKECTRL_RUNTIMEMRRMIODIS Fld(1, 28) //[28:28] 538 #define CKECTRL_CKEON Fld(1, 31) //[31:31] 539 540 #define DRAMC_REG_DVFS_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x0208) 541 #define DVFS_CTRL0_R_DRAMC_CHA Fld(1, 0) //[0:0] 542 #define DVFS_CTRL0_SHU_PHYRST_SEL Fld(1, 1) //[1:1] 543 #define DVFS_CTRL0_R_DVFS_SREF_OPT Fld(1, 5) //[5:5] 544 #define DVFS_CTRL0_HWSET_WLRL Fld(1, 8) //[8:8] 545 #define DVFS_CTRL0_MR13_SHU_EN Fld(1, 9) //[9:9] 546 #define DVFS_CTRL0_VRCG_EN Fld(1, 10) //[10:10] 547 #define DVFS_CTRL0_SHU_CLK_MASK Fld(1, 12) //[12:12] 548 #define DVFS_CTRL0_DVFS_RXFIFOST_SKIP Fld(1, 13) //[13:13] 549 #define DVFS_CTRL0_DVFS_MR2_SKIP Fld(1, 14) //[14:14] 550 #define DVFS_CTRL0_DVFS_NOQUEFLUSH_EN Fld(1, 15) //[15:15] 551 #define DVFS_CTRL0_DVFS_CKE_OPT Fld(1, 16) //[16:16] 552 #define DVFS_CTRL0_R_SHUFFLE_BLOCK_OPT Fld(2, 17) //[18:17] 553 #define DVFS_CTRL0_DVFS_CG_OPT Fld(1, 19) //[19:19] 554 #define DVFS_CTRL0_SCARB_PRI_OPT Fld(1, 20) //[20:20] 555 #define DVFS_CTRL0_R_DMDVFSMRW_EN Fld(1, 21) //[21:21] 556 #define DVFS_CTRL0_MRWWOPRA Fld(1, 22) //[22:22] 557 #define DVFS_CTRL0_SHU2RKOPT Fld(1, 23) //[23:23] 558 #define DVFS_CTRL0_R_DMSHU_RDATRST_MASK Fld(1, 25) //[25:25] 559 #define DVFS_CTRL0_DVFS_SYNC_MASK Fld(1, 27) //[27:27] 560 561 #define DRAMC_REG_SHUCTRL1 (DRAMC_AO_BASE_ADDRESS + 0x020C) 562 #define SHUCTRL1_FC_PRDCNT Fld(8, 0) //[7:0] 563 #define SHUCTRL1_CKFSPE_PRDCNT Fld(8, 8) //[15:8] 564 #define SHUCTRL1_CKFSPX_PRDCNT Fld(8, 16) //[23:16] 565 #define SHUCTRL1_VRCGEN_PRDCNT Fld(8, 24) //[31:24] 566 567 #define DRAMC_REG_DVFS_TIMING_CTRL1 (DRAMC_AO_BASE_ADDRESS + 0x0210) 568 #define DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT Fld(8, 0) //[7:0] 569 #define DVFS_TIMING_CTRL1_DMSHU_CNT Fld(6, 16) //[21:16] 570 571 #define DRAMC_REG_SHUCTRL3 (DRAMC_AO_BASE_ADDRESS + 0x0214) 572 #define SHUCTRL3_VRCGDIS_MRSMA Fld(13, 0) //[12:0] 573 #define SHUCTRL3_VRCGDISOP Fld(8, 16) //[23:16] 574 575 #define DRAMC_REG_DVFS_TIMING_CTRL3 (DRAMC_AO_BASE_ADDRESS + 0x0218) 576 #define DVFS_TIMING_CTRL3_PREA_INTV Fld(5, 0) //[4:0] 577 #define DVFS_TIMING_CTRL3_MRW_INTV Fld(5, 8) //[12:8] 578 #define DVFS_TIMING_CTRL3_RTMRW_MRW1_SKIP Fld(1, 16) //[16:16] 579 #define DVFS_TIMING_CTRL3_RTMRW_MRW2_SKIP Fld(1, 17) //[17:17] 580 #define DVFS_TIMING_CTRL3_RTMRW_MRW3_SKIP Fld(1, 18) //[18:18] 581 #define DVFS_TIMING_CTRL3_RTMRW_MRW1_PAUSE Fld(1, 19) //[19:19] 582 #define DVFS_TIMING_CTRL3_RTMRW_MRW2_PAUSE Fld(1, 20) //[20:20] 583 #define DVFS_TIMING_CTRL3_RTMRW_MRW3_PAUSE Fld(1, 21) //[21:21] 584 #define DVFS_TIMING_CTRL3_RTMRW_MRW3_PRDCNT Fld(8, 24) //[31:24] 585 586 #define DRAMC_REG_CMD_DEC_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x021C) 587 #define CMD_DEC_CTRL0_GDDR3RST Fld(1, 0) //[0:0] 588 #define CMD_DEC_CTRL0_SELPH_CMD_CG_DIS Fld(1, 4) //[4:4] 589 #define CMD_DEC_CTRL0_RA15TOCS1 Fld(1, 27) //[27:27] 590 #define CMD_DEC_CTRL0_RKMODE Fld(3, 8) //[10:8] 591 #define CMD_DEC_CTRL0_RKSWAP Fld(1, 11) //[11:11] 592 #define CMD_DEC_CTRL0_CS1FIXOFF Fld(1, 12) //[12:12] 593 #define CMD_DEC_CTRL0_PHYPIPE1EN Fld(1, 15) //[15:15] 594 #define CMD_DEC_CTRL0_PHYPIPE2EN Fld(1, 16) //[16:16] 595 #define CMD_DEC_CTRL0_PHYPIPE3EN Fld(1, 17) //[17:17] 596 #define CMD_DEC_CTRL0_DQCMD Fld(1, 19) //[19:19] 597 598 #define DRAMC_REG_HMR4 (DRAMC_AO_BASE_ADDRESS + 0x0220) 599 #define HMR4_DRS_MR4_OPT_B Fld(1, 0) //[0:0] 600 #define HMR4_HMR4_TOG_OPT Fld(1, 1) //[1:1] 601 #define HMR4_SPDR_MR4_OPT Fld(1, 2) //[2:2] 602 #define HMR4_SRFMR4_CNTKEEP_B Fld(1, 3) //[3:3] 603 #define HMR4_MRRREFUPD_B Fld(1, 4) //[4:4] 604 #define HMR4_HMR4_BYTEMODE_EN Fld(1, 5) //[5:5] 605 #define HMR4_MR4INT_LIMITEN Fld(1, 6) //[6:6] 606 #define HMR4_REFR_PERIOD_OPT Fld(1, 7) //[7:7] 607 #define HMR4_REFRDIS Fld(1, 8) //[8:8] 608 #define HMR4_REFRCNT_OPT Fld(1, 9) //[9:9] 609 610 #define DRAMC_REG_BYPASS_FSPOP (DRAMC_AO_BASE_ADDRESS + 0x0224) 611 #define BYPASS_FSPOP_BPFSP_SET_SHU0 Fld(1, 0) //[0:0] 612 #define BYPASS_FSPOP_BPFSP_SET_SHU1 Fld(1, 1) //[1:1] 613 #define BYPASS_FSPOP_BPFSP_SET_SHU2 Fld(1, 2) //[2:2] 614 #define BYPASS_FSPOP_BPFSP_SET_SHU3 Fld(1, 3) //[3:3] 615 #define BYPASS_FSPOP_BPFSP_SET_SHU4 Fld(1, 4) //[4:4] 616 #define BYPASS_FSPOP_BPFSP_SET_SHU5 Fld(1, 5) //[5:5] 617 #define BYPASS_FSPOP_BPFSP_SET_SHU6 Fld(1, 6) //[6:6] 618 #define BYPASS_FSPOP_BPFSP_SET_SHU7 Fld(1, 7) //[7:7] 619 #define BYPASS_FSPOP_BPFSP_SET_SHU8 Fld(1, 8) //[8:8] 620 #define BYPASS_FSPOP_BPFSP_SET_SHU9 Fld(1, 9) //[9:9] 621 #define BYPASS_FSPOP_BPFSP_OPT Fld(1, 16) //[16:16] 622 623 #define DRAMC_REG_RKCFG (DRAMC_AO_BASE_ADDRESS + 0x0228) 624 #define RKCFG_MRS2RK Fld(1, 10) //[10:10] 625 #define RKCFG_CKE2RANK Fld(1, 12) //[12:12] 626 627 #define DRAMC_REG_SLP4_TESTMODE (DRAMC_AO_BASE_ADDRESS + 0x022C) 628 #define SLP4_TESTMODE_CA0_TEST Fld(4, 0) //[3:0] 629 #define SLP4_TESTMODE_CA1_TEST Fld(4, 4) //[7:4] 630 #define SLP4_TESTMODE_CA2_TEST Fld(4, 8) //[11:8] 631 #define SLP4_TESTMODE_CA3_TEST Fld(4, 12) //[15:12] 632 #define SLP4_TESTMODE_CA4_TEST Fld(4, 16) //[19:16] 633 #define SLP4_TESTMODE_CA5_TEST Fld(4, 20) //[23:20] 634 635 #define DRAMC_REG_DQ_MUX_SET0 (DRAMC_AO_BASE_ADDRESS + 0x0230) 636 #define DQ_MUX_SET0_SRF_ENTER_MASK_OPT Fld(1, 30) //[30:30] 637 #define DQ_MUX_SET0_DQ4BMUX Fld(1, 31) //[31:31] 638 639 #define DRAMC_REG_DBIWR_PROTECT (DRAMC_AO_BASE_ADDRESS + 0x0234) 640 #define DBIWR_PROTECT_DBIWR_IMP_EN Fld(1, 0) //[0:0] 641 #define DBIWR_PROTECT_DBIWR_PINMUX_EN Fld(1, 1) //[1:1] 642 #define DBIWR_PROTECT_DBIWR_OPT_B0 Fld(8, 16) //[23:16] 643 #define DBIWR_PROTECT_DBIWR_OPT_B1 Fld(8, 24) //[31:24] 644 645 #define DRAMC_REG_TX_SET0 (DRAMC_AO_BASE_ADDRESS + 0x0238) 646 #define TX_SET0_TXRANK Fld(2, 0) //[1:0] 647 #define TX_SET0_TXRANKFIX Fld(1, 2) //[2:2] 648 #define TX_SET0_DDRPHY_COMB_CG_SEL Fld(1, 3) //[3:3] 649 #define TX_SET0_TX_DQM_DEFAULT Fld(1, 4) //[4:4] 650 #define TX_SET0_DQBUS_X32 Fld(1, 5) //[5:5] 651 #define TX_SET0_OE_DOWNGRADE Fld(1, 6) //[6:6] 652 #define TX_SET0_DQ16COM1 Fld(1, 21) //[21:21] 653 #define TX_SET0_WPRE2T Fld(1, 22) //[22:22] 654 #define TX_SET0_DRSCLR_EN Fld(1, 24) //[24:24] 655 #define TX_SET0_DRSCLR_RK0_EN Fld(1, 25) //[25:25] 656 #define TX_SET0_ARPI_CAL_E2OPT Fld(1, 26) //[26:26] 657 #define TX_SET0_TX_DLY_CAL_E2OPT Fld(1, 27) //[27:27] 658 #define TX_SET0_DQS_OE_OP1_DIS Fld(1, 28) //[28:28] 659 #define TX_SET0_DQS_OE_OP2_EN Fld(1, 29) //[29:29] 660 #define TX_SET0_RK_SCINPUT_OPT Fld(1, 30) //[30:30] 661 #define TX_SET0_DRAMOEN Fld(1, 31) //[31:31] 662 663 #define DRAMC_REG_TX_CG_SET0 (DRAMC_AO_BASE_ADDRESS + 0x023C) 664 #define TX_CG_SET0_SELPH_4LCG_DIS Fld(1, 0) //[0:0] 665 #define TX_CG_SET0_SELPH_CG_DIS Fld(1, 1) //[1:1] 666 #define TX_CG_SET0_DWCLKRUN Fld(1, 2) //[2:2] 667 #define TX_CG_SET0_WDATA_CG_DIS Fld(1, 3) //[3:3] 668 #define TX_CG_SET0_TX_ATK_CLKRUN Fld(1, 4) //[4:4] 669 #define TX_CG_SET0_PSEL_OPT3 Fld(1, 22) //[22:22] 670 #define TX_CG_SET0_PSEL_OPT2 Fld(1, 23) //[23:23] 671 #define TX_CG_SET0_PSEL_OPT1 Fld(1, 24) //[24:24] 672 #define TX_CG_SET0_PSEL_CNT Fld(6, 25) //[30:25] 673 #define TX_CG_SET0_PSELAR Fld(1, 31) //[31:31] 674 675 #define DRAMC_REG_RX_SET0 (DRAMC_AO_BASE_ADDRESS + 0x0240) 676 #define RX_SET0_RDATRST Fld(1, 0) //[0:0] 677 #define RX_SET0_PRE_DLE_VLD_OPT Fld(1, 1) //[1:1] 678 #define RX_SET0_DATLAT_PDLE_TH Fld(3, 2) //[4:2] 679 #define RX_SET0_RANKRDY_OPT Fld(1, 5) //[5:5] 680 #define RX_SET0_SMRR_UPD_OLD Fld(1, 6) //[6:6] 681 #define RX_SET0_EBG_DLE_SKIP_SPEC_RID Fld(1, 29) //[29:29] 682 #define RX_SET0_DM32BIT_RDSEL_OPT Fld(1, 30) //[30:30] 683 #define RX_SET0_DM4TO1MODE Fld(1, 31) //[31:31] 684 685 #define DRAMC_REG_RX_CG_SET0 (DRAMC_AO_BASE_ADDRESS + 0x0244) 686 #define RX_CG_SET0_RDPERIODON Fld(1, 29) //[29:29] 687 #define RX_CG_SET0_RDATCKAR Fld(1, 30) //[30:30] 688 #define RX_CG_SET0_RDYCKAR Fld(1, 31) //[31:31] 689 690 #define DRAMC_REG_DQSOSCR (DRAMC_AO_BASE_ADDRESS + 0x0248) 691 #define DQSOSCR_DQSOSC_INTEN Fld(1, 0) //[0:0] 692 #define DQSOSCR_DQSOSC2RK Fld(1, 1) //[1:1] 693 #define DQSOSCR_TXUPD_BLOCK_SEL Fld(2, 2) //[3:2] 694 #define DQSOSCR_TXUPD_BLOCK_OPT Fld(1, 4) //[4:4] 695 #define DQSOSCR_TXUPDMODE Fld(1, 5) //[5:5] 696 #define DQSOSCR_MANUTXUPD Fld(1, 6) //[6:6] 697 #define DQSOSCR_ARUIDQ_SW Fld(1, 7) //[7:7] 698 #define DQSOSCR_DQS2DQ_UPD_BLOCK_CNT Fld(5, 8) //[12:8] 699 #define DQSOSCR_TDQS2DQ_UPD_BLOCKING Fld(1, 13) //[13:13] 700 #define DQSOSCR_DQS2DQ_UPD_MON_OPT Fld(1, 14) //[14:14] 701 #define DQSOSCR_DQS2DQ_UPD_MON_CNT_SEL Fld(2, 15) //[16:15] 702 #define DQSOSCR_TXUPD_IDLE_SEL Fld(2, 17) //[18:17] 703 #define DQSOSCR_TXUPD_ABREF_SEL Fld(2, 19) //[20:19] 704 #define DQSOSCR_TXUPD_IDLE_OPT Fld(1, 21) //[21:21] 705 #define DQSOSCR_DQS2DQ_SHU_HW_CAL_DIS Fld(1, 22) //[22:22] 706 #define DQSOSCR_SREF_TXUI_RELOAD_OPT Fld(1, 23) //[23:23] 707 #define DQSOSCR_DQSOSCRDIS Fld(1, 24) //[24:24] 708 #define DQSOSCR_DQS2DQ_WARN_OPT Fld(1, 25) //[25:25] 709 #define DQSOSCR_R_DMDQS2DQ_FILT_OPT Fld(1, 26) //[26:26] 710 #define DQSOSCR_SREF_TXPI_RELOAD_OPT Fld(1, 27) //[27:27] 711 #define DQSOSCR_EMPTY_WRITE_OPT Fld(1, 28) //[28:28] 712 #define DQSOSCR_TXUPD_ABREF_OPT Fld(1, 29) //[29:29] 713 #define DQSOSCR_DQSOSCLOPAD Fld(1, 30) //[30:30] 714 #define DQSOSCR_DQSOSC_CALEN Fld(1, 31) //[31:31] 715 716 #define DRAMC_REG_DRAMCTRL (DRAMC_AO_BASE_ADDRESS + 0x024C) 717 #define DRAMCTRL_CTOREQ_HPRI_OPT Fld(1, 0) //[0:0] 718 #define DRAMCTRL_MATAB_LP5_MODE Fld(1, 1) //[1:1] 719 #define DRAMCTRL_ADRDECEN Fld(1, 2) //[2:2] 720 #define DRAMCTRL_ADRBIT3DEC Fld(1, 3) //[3:3] 721 #define DRAMCTRL_ADRDEN_1TO4_OPT Fld(1, 5) //[5:5] 722 #define DRAMCTRL_ALL_BLOCK_CTO_ALE_DBG_EN Fld(1, 8) //[8:8] 723 #define DRAMCTRL_SELFREF_BLOCK_CTO_ALE_DBG_EN Fld(1, 9) //[9:9] 724 #define DRAMCTRL_DVFS_BLOCK_CTO_ALE_DBG_EN Fld(1, 10) //[10:10] 725 #define DRAMCTRL_AG0MWR Fld(1, 12) //[12:12] 726 #define DRAMCTRL_DYNMWREN Fld(1, 13) //[13:13] 727 #define DRAMCTRL_ALEBLOCK Fld(1, 14) //[14:14] 728 #define DRAMCTRL_PREALL_OPTION Fld(1, 19) //[19:19] 729 #define DRAMCTRL_REQQUE_DEPTH_UPD Fld(1, 25) //[25:25] 730 #define DRAMCTRL_REQQUE_THD_EN Fld(1, 26) //[26:26] 731 #define DRAMCTRL_REQQUE_MAXCNT_CHG Fld(1, 27) //[27:27] 732 #define DRAMCTRL_PREA_RK Fld(2, 28) //[29:28] 733 #define DRAMCTRL_SHORTQ_OPT Fld(1, 31) //[31:31] 734 735 #define DRAMC_REG_MISCTL0 (DRAMC_AO_BASE_ADDRESS + 0x0250) 736 #define MISCTL0_REFP_ARBMASK_PBR2PBR_ENA Fld(1, 0) //[0:0] 737 #define MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS Fld(1, 1) //[1:1] 738 #define MISCTL0_WDLE_DVFS_NO_FLUSH_OPT_DIS Fld(1, 4) //[4:4] 739 #define MISCTL0_GROUP_A_REV Fld(4, 8) //[11:8] 740 #define MISCTL0_PG_WAKEUP_OPT Fld(2, 14) //[15:14] 741 #define MISCTL0_PAGDIS Fld(1, 17) //[17:17] 742 #define MISCTL0_REFA_ARB_EN2 Fld(1, 19) //[19:19] 743 #define MISCTL0_REFA_ARB_EN_OPTION Fld(1, 21) //[21:21] 744 #define MISCTL0_REORDER_MASK_E1T Fld(1, 22) //[22:22] 745 #define MISCTL0_PBC_ARB_E1T Fld(1, 23) //[23:23] 746 #define MISCTL0_PBC_ARB_EN Fld(1, 24) //[24:24] 747 #define MISCTL0_REFA_ARB_EN Fld(1, 25) //[25:25] 748 #define MISCTL0_REFP_ARB_EN Fld(1, 26) //[26:26] 749 #define MISCTL0_EMIPREEN Fld(1, 27) //[27:27] 750 #define MISCTL0_REFP_ARB_EN2 Fld(1, 31) //[31:31] 751 752 #define DRAMC_REG_PERFCTL0 (DRAMC_AO_BASE_ADDRESS + 0x0254) 753 #define PERFCTL0_EBG_EN Fld(1, 0) //[0:0] 754 #define PERFCTL0_AIDCHKEN Fld(1, 3) //[3:3] 755 #define PERFCTL0_RWHPRIEN Fld(1, 8) //[8:8] 756 #define PERFCTL0_RWLLATEN Fld(1, 9) //[9:9] 757 #define PERFCTL0_RWAGEEN Fld(1, 10) //[10:10] 758 #define PERFCTL0_EMILLATEN Fld(1, 11) //[11:11] 759 #define PERFCTL0_WFLUSHEN Fld(1, 14) //[14:14] 760 #define PERFCTL0_REORDER_MODE Fld(1, 18) //[18:18] 761 #define PERFCTL0_REORDEREN Fld(1, 19) //[19:19] 762 #define PERFCTL0_SBR_MASK_OPT Fld(1, 20) //[20:20] 763 #define PERFCTL0_SBR_MASK_OPT2 Fld(1, 21) //[21:21] 764 #define PERFCTL0_MAFIXHIGH Fld(1, 22) //[22:22] 765 #define PERFCTL0_RECORDER_MASK_OPT Fld(1, 24) //[24:24] 766 #define PERFCTL0_MDMCU_MASK_EN Fld(1, 25) //[25:25] 767 768 #define DRAMC_REG_ARBCTL (DRAMC_AO_BASE_ADDRESS + 0x0258) 769 #define ARBCTL_MAXPENDCNT Fld(8, 0) //[7:0] 770 #define ARBCTL_RDATACNTDIS Fld(1, 8) //[8:8] 771 #define ARBCTL_WDATACNTDIS Fld(1, 9) //[9:9] 772 773 #define DRAMC_REG_DATASCR (DRAMC_AO_BASE_ADDRESS + 0x025C) 774 #define DATASCR_WDATKEY0 Fld(1, 0) //[0:0] 775 #define DATASCR_WDATKEY1 Fld(1, 1) //[1:1] 776 #define DATASCR_WDATKEY2 Fld(1, 2) //[2:2] 777 #define DATASCR_WDATKEY3 Fld(1, 3) //[3:3] 778 #define DATASCR_WDATKEY4 Fld(1, 4) //[4:4] 779 #define DATASCR_WDATKEY5 Fld(1, 5) //[5:5] 780 #define DATASCR_WDATKEY6 Fld(1, 6) //[6:6] 781 #define DATASCR_WDATKEY7 Fld(1, 7) //[7:7] 782 #define DATASCR_WDATITLV Fld(1, 8) //[8:8] 783 784 #define DRAMC_REG_CLKAR (DRAMC_AO_BASE_ADDRESS + 0x0260) 785 #define CLKAR_REQQUE_PACG_DIS Fld(15, 0) //[14:0] 786 #define CLKAR_SRF_CLKRUN Fld(1, 17) //[17:17] 787 #define CLKAR_IDLE_OPT Fld(1, 18) //[18:18] 788 #define CLKAR_RKSIZE Fld(3, 20) //[22:20] 789 #define CLKAR_DCMREF_OPT Fld(1, 24) //[24:24] 790 #define CLKAR_REQQUECLKRUN Fld(1, 27) //[27:27] 791 792 #define DRAMC_REG_REFCTRL0 (DRAMC_AO_BASE_ADDRESS + 0x0264) 793 #define REFCTRL0_PBREF_BK_REFA_NUM Fld(3, 0) //[2:0] 794 #define REFCTRL0_PBREF_BK_REFA_ENA Fld(1, 3) //[3:3] 795 #define REFCTRL0_RFRINTCTL Fld(1, 5) //[5:5] 796 #define REFCTRL0_RFRINTEN Fld(1, 6) //[6:6] 797 #define REFCTRL0_REFOVERCNT_RST Fld(1, 7) //[7:7] 798 #define REFCTRL0_DMPGVLD_IG Fld(1, 8) //[8:8] 799 #define REFCTRL0_KEEP_PBREF_OPT Fld(1, 9) //[9:9] 800 #define REFCTRL0_KEEP_PBREF Fld(1, 10) //[10:10] 801 #define REFCTRL0_REFRATE_FOR_BK_ARBMASK Fld(1, 11) //[11:11] 802 #define REFCTRL0_DISBYREFNUM Fld(3, 12) //[14:12] 803 #define REFCTRL0_PBREF_DISBYREFNUM Fld(1, 16) //[16:16] 804 #define REFCTRL0_PBREF_DISBYRATE Fld(1, 17) //[17:17] 805 #define REFCTRL0_SREF3_OPTION1 Fld(1, 19) //[19:19] 806 #define REFCTRL0_ADVREF_CNT Fld(4, 20) //[23:20] 807 #define REFCTRL0_REF_PREGATE_CNT Fld(4, 24) //[27:24] 808 #define REFCTRL0_REFDIS Fld(1, 29) //[29:29] 809 810 #define DRAMC_REG_REFCTRL1 (DRAMC_AO_BASE_ADDRESS + 0x0268) 811 #define REFCTRL1_PB2AB_OPT Fld(1, 0) //[0:0] 812 #define REFCTRL1_PB2AB_OPT1 Fld(1, 1) //[1:1] 813 #define REFCTRL1_PBREF_DISBYMODREF Fld(1, 2) //[2:2] 814 #define REFCTRL1_REFPENDINGINT_OPT1 Fld(1, 3) //[3:3] 815 #define REFCTRL1_PRE8REF Fld(1, 4) //[4:4] 816 #define REFCTRL1_REF_QUE_AUTOSAVE_EN Fld(1, 5) //[5:5] 817 #define REFCTRL1_REFPEND_OPT1 Fld(1, 6) //[6:6] 818 #define REFCTRL1_REFPEND_OPT2 Fld(1, 7) //[7:7] 819 #define REFCTRL1_REFPB2AB_IGZQCS Fld(1, 8) //[8:8] 820 #define REFCTRL1_REFRATE_MON_CLR Fld(1, 11) //[11:11] 821 #define REFCTRL1_REF_OVERHEAD_PBR2PB_ENA Fld(1, 13) //[13:13] 822 #define REFCTRL1_REF_OVERHEAD_RATE_REFAL_ENA Fld(1, 14) //[14:14] 823 #define REFCTRL1_REF_OVERHEAD_RATE_REFPB_ENA Fld(1, 15) //[15:15] 824 #define REFCTRL1_REFRATE_MANUAL Fld(5, 16) //[20:16] 825 #define REFCTRL1_REF_OVERHEAD_SLOW_REFAL_ENA Fld(1, 24) //[24:24] 826 #define REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA Fld(1, 25) //[25:25] 827 #define REFCTRL1_REF_OVERHEAD_ALL_REFAL_ENA Fld(1, 26) //[26:26] 828 #define REFCTRL1_REF_OVERHEAD_ALL_REFPB_ENA Fld(1, 27) //[27:27] 829 #define REFCTRL1_REFRATE_MANUAL_RATE_TRIG Fld(1, 31) //[31:31] 830 831 #define DRAMC_REG_REF_BOUNCE1 (DRAMC_AO_BASE_ADDRESS + 0x026C) 832 #define REF_BOUNCE1_REFRATE_DEBOUNCE_COUNT Fld(8, 0) //[7:0] 833 #define REF_BOUNCE1_REFRATE_DEBOUNCE_TH Fld(5, 8) //[12:8] 834 #define REF_BOUNCE1_REFRATE_DEBOUNCE_OPT Fld(1, 13) //[13:13] 835 #define REF_BOUNCE1_REFRATE_DEBOUNCE_DIS Fld(16, 16) //[31:16] 836 837 #define DRAMC_REG_REF_BOUNCE2 (DRAMC_AO_BASE_ADDRESS + 0x0270) 838 #define REF_BOUNCE2_PRE_MR4INT_TH Fld(5, 0) //[4:0] 839 840 #define DRAMC_REG_REFPEND1 (DRAMC_AO_BASE_ADDRESS + 0x0278) 841 #define REFPEND1_MPENDREFCNT_TH0 Fld(4, 0) //[3:0] 842 #define REFPEND1_MPENDREFCNT_TH1 Fld(4, 4) //[7:4] 843 #define REFPEND1_MPENDREFCNT_TH2 Fld(4, 8) //[11:8] 844 #define REFPEND1_MPENDREFCNT_TH3 Fld(4, 12) //[15:12] 845 #define REFPEND1_MPENDREFCNT_TH4 Fld(4, 16) //[19:16] 846 #define REFPEND1_MPENDREFCNT_TH5 Fld(4, 20) //[23:20] 847 #define REFPEND1_MPENDREFCNT_TH6 Fld(4, 24) //[27:24] 848 #define REFPEND1_MPENDREFCNT_TH7 Fld(4, 28) //[31:28] 849 850 #define DRAMC_REG_REFPEND2 (DRAMC_AO_BASE_ADDRESS + 0x027C) 851 #define REFPEND2_MPENDREFCNT_TH8 Fld(4, 0) //[3:0] 852 #define REFPEND2_MPENDREFCNT_TH9 Fld(4, 4) //[7:4] 853 #define REFPEND2_MPENDREFCNT_TH10 Fld(4, 8) //[11:8] 854 #define REFPEND2_MPENDREFCNT_TH11 Fld(4, 12) //[15:12] 855 #define REFPEND2_MPENDREFCNT_TH12 Fld(4, 16) //[19:16] 856 #define REFPEND2_MPENDREFCNT_TH13 Fld(4, 20) //[23:20] 857 #define REFPEND2_MPENDREFCNT_TH14 Fld(4, 24) //[27:24] 858 #define REFPEND2_MPENDREFCNT_TH15 Fld(4, 28) //[31:28] 859 860 #define DRAMC_REG_REFQUE_CNT (DRAMC_AO_BASE_ADDRESS + 0x0280) 861 #define REFQUE_CNT_REFRESH_QUEUE_CNT_FROM_AO Fld(4, 0) //[3:0] 862 863 #define DRAMC_REG_SCSMCTRL (DRAMC_AO_BASE_ADDRESS + 0x0284) 864 #define SCSMCTRL_SC_PG_UPD_OPT Fld(1, 0) //[0:0] 865 #define SCSMCTRL_SC_PG_MAN_DIS Fld(1, 1) //[1:1] 866 #define SCSMCTRL_SC_PG_OPT2_DIS Fld(1, 8) //[8:8] 867 #define SCSMCTRL_SC_PG_STCMD_AREF_DIS Fld(1, 9) //[9:9] 868 #define SCSMCTRL_SC_PG_MPRW_DIS Fld(1, 10) //[10:10] 869 #define SCSMCTRL_SCPRE Fld(1, 19) //[19:19] 870 871 #define DRAMC_REG_SCSMCTRL_CG (DRAMC_AO_BASE_ADDRESS + 0x0288) 872 #define SCSMCTRL_CG_SCARB_SM_CGAR Fld(1, 30) //[30:30] 873 #define SCSMCTRL_CG_SCSM_CGAR Fld(1, 31) //[31:31] 874 875 #define DRAMC_REG_REFCTRL2 (DRAMC_AO_BASE_ADDRESS + 0x028C) 876 #define REFCTRL2_MR4INT_TH Fld(5, 0) //[4:0] 877 #define REFCTRL2_PB2AB_THD Fld(3, 8) //[10:8] 878 #define REFCTRL2_REF_OVERHEAD_RATE Fld(16, 16) //[31:16] 879 880 #define DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0 (DRAMC_AO_BASE_ADDRESS + 0x0290) 881 #define TX_FREQ_RATIO_OLD_MODE0_FREQ_RATIO_TX_8 Fld(5, 0) //[4:0] 882 #define TX_FREQ_RATIO_OLD_MODE0_FREQ_RATIO_TX_9 Fld(5, 8) //[12:8] 883 #define TX_FREQ_RATIO_OLD_MODE0_FREQ_RATIO_TX_10 Fld(5, 16) //[20:16] 884 #define TX_FREQ_RATIO_OLD_MODE0_FREQ_RATIO_TX_11 Fld(5, 24) //[28:24] 885 #define TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT Fld(1, 31) //[31:31] 886 887 #define DRAMC_REG_TX_FREQ_RATIO_OLD_MODE1 (DRAMC_AO_BASE_ADDRESS + 0x0294) 888 #define TX_FREQ_RATIO_OLD_MODE1_FREQ_RATIO_TX_4 Fld(5, 0) //[4:0] 889 #define TX_FREQ_RATIO_OLD_MODE1_FREQ_RATIO_TX_5 Fld(5, 8) //[12:8] 890 #define TX_FREQ_RATIO_OLD_MODE1_FREQ_RATIO_TX_6 Fld(5, 16) //[20:16] 891 #define TX_FREQ_RATIO_OLD_MODE1_FREQ_RATIO_TX_7 Fld(5, 24) //[28:24] 892 893 #define DRAMC_REG_TX_FREQ_RATIO_OLD_MODE2 (DRAMC_AO_BASE_ADDRESS + 0x0298) 894 #define TX_FREQ_RATIO_OLD_MODE2_FREQ_RATIO_TX_0 Fld(5, 0) //[4:0] 895 #define TX_FREQ_RATIO_OLD_MODE2_FREQ_RATIO_TX_1 Fld(5, 8) //[12:8] 896 #define TX_FREQ_RATIO_OLD_MODE2_FREQ_RATIO_TX_2 Fld(5, 16) //[20:16] 897 #define TX_FREQ_RATIO_OLD_MODE2_FREQ_RATIO_TX_3 Fld(5, 24) //[28:24] 898 899 #define DRAMC_REG_WDT_RST (DRAMC_AO_BASE_ADDRESS + 0x029C) 900 #define WDT_RST_WDT_DBG_RST Fld(1, 0) //[0:0] 901 902 #define DRAMC_REG_SEDA_LOOP_BAK_ERR_PAT_B01 (DRAMC_AO_BASE_ADDRESS + 0x02A0) 903 #define SEDA_LOOP_BAK_ERR_PAT_B01_SEDA_LOOP_BAK_ERR_PAT0 Fld(32, 0) //[31:0] 904 905 #define DRAMC_REG_SEDA_LOOP_BAK_ERR_PAT_B23 (DRAMC_AO_BASE_ADDRESS + 0x02A4) 906 #define SEDA_LOOP_BAK_ERR_PAT_B23_SEDA_LOOP_BAK_ERR_PAT1 Fld(32, 0) //[31:0] 907 908 #define DRAMC_REG_SEDA_LOOP_BAK_ERR_PAT_B45 (DRAMC_AO_BASE_ADDRESS + 0x02A8) 909 #define SEDA_LOOP_BAK_ERR_PAT_B45_SEDA_LOOP_BAK_ERR_PAT2 Fld(32, 0) //[31:0] 910 911 #define DRAMC_REG_SEDA_LOOP_BAK_ERR_PAT_B67 (DRAMC_AO_BASE_ADDRESS + 0x02AC) 912 #define SEDA_LOOP_BAK_ERR_PAT_B67_SEDA_LOOP_BAK_ERR_PAT3 Fld(32, 0) //[31:0] 913 914 #define DRAMC_REG_SEDA_LOOP_BAK_SET (DRAMC_AO_BASE_ADDRESS + 0x02B0) 915 #define SEDA_LOOP_BAK_SET_WPRE0T Fld(1, 0) //[0:0] 916 #define SEDA_LOOP_BAK_SET_DRAMC_LOOP_BAK_EN Fld(1, 1) //[1:1] 917 #define SEDA_LOOP_BAK_SET_DRAMC_LOOP_BAK_CMP_EN Fld(1, 2) //[2:2] 918 #define SEDA_LOOP_BAK_SET_LOOP_BAK_WDAT_SEL Fld(3, 4) //[6:4] 919 920 #define DRAMC_REG_DBG_CMDDEC_CMDSEL0 (DRAMC_AO_BASE_ADDRESS + 0x02C0) 921 #define DBG_CMDDEC_CMDSEL0_RANK0_10GBEN Fld(1, 0) //[0:0] 922 #define DBG_CMDDEC_CMDSEL0_RANK1_10GBEN Fld(1, 1) //[1:1] 923 #define DBG_CMDDEC_CMDSEL0_DBG_CMDDEC_CMDSEL Fld(1, 4) //[4:4] 924 #define DBG_CMDDEC_CMDSEL0_DBG_CMDDEC_CMDTYPE Fld(16, 16) //[31:16] 925 926 #define DRAMC_REG_DBG_CMDDEC_CMDSEL1 (DRAMC_AO_BASE_ADDRESS + 0x02C4) 927 #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_OP Fld(8, 0) //[7:0] 928 #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_MA Fld(8, 8) //[15:8] 929 #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_C Fld(12, 16) //[27:16] 930 #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_RK Fld(2, 28) //[29:28] 931 #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_SINGLE Fld(1, 30) //[30:30] 932 933 #define DRAMC_REG_DBG_CMDDEC_CMDSEL2 (DRAMC_AO_BASE_ADDRESS + 0x02C8) 934 #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_R Fld(17, 0) //[16:0] 935 #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_BA Fld(3, 17) //[19:17] 936 #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_BL Fld(1, 20) //[20:20] 937 #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_AP Fld(1, 21) //[21:21] 938 #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_AB Fld(1, 22) //[22:22] 939 940 #define DRAMC_REG_DBG_CMDDEC_CMDSEL3 (DRAMC_AO_BASE_ADDRESS + 0x02CC) 941 #define DBG_CMDDEC_CMDSEL3_DBG_CMDDEC_CMDSEL_CA0 Fld(8, 0) //[7:0] 942 #define DBG_CMDDEC_CMDSEL3_DBG_CMDDEC_CMDSEL_CA1 Fld(8, 8) //[15:8] 943 #define DBG_CMDDEC_CMDSEL3_DBG_CMDDEC_CMDSEL_CA2 Fld(8, 16) //[23:16] 944 #define DBG_CMDDEC_CMDSEL3_DBG_CMDDEC_CMDSEL_CA3 Fld(8, 24) //[31:24] 945 946 #define DRAMC_REG_DBG_CMDDEC_CMDSEL4 (DRAMC_AO_BASE_ADDRESS + 0x02D0) 947 #define DBG_CMDDEC_CMDSEL4_DBG_CMDDEC_CMDSEL_CA4 Fld(8, 0) //[7:0] 948 #define DBG_CMDDEC_CMDSEL4_DBG_CMDDEC_CMDSEL_CA5 Fld(8, 8) //[15:8] 949 950 #define DRAMC_REG_RTSWCMD_CNT (DRAMC_AO_BASE_ADDRESS + 0x02D4) 951 #define RTSWCMD_CNT_RTSWCMD_CNT Fld(32, 0) //[31:0] 952 953 #define DRAMC_REG_REFCTRL3 (DRAMC_AO_BASE_ADDRESS + 0x02D8) 954 #define REFCTRL3_REF_DERATING_EN Fld(16, 0) //[15:0] 955 956 #define DRAMC_REG_DRAMC_IRQ_EN (DRAMC_AO_BASE_ADDRESS + 0x02E0) 957 #define DRAMC_IRQ_EN_MR4INT_EN Fld(1, 0) //[0:0] 958 #define DRAMC_IRQ_EN_REFPENDINGINT_EN Fld(1, 1) //[1:1] 959 #define DRAMC_IRQ_EN_PRE_MR4INT_EN Fld(1, 2) //[2:2] 960 #define DRAMC_IRQ_EN_RTMRWINT_EN Fld(1, 3) //[3:3] 961 #define DRAMC_IRQ_EN_INT_SREF_REQ_NO_ACK_EN Fld(1, 6) //[6:6] 962 #define DRAMC_IRQ_EN_INT_SREF_REQ_SHORT_EN Fld(1, 7) //[7:7] 963 #define DRAMC_IRQ_EN_INT_SREF_REQ_DTRIG_EN Fld(1, 8) //[8:8] 964 #define DRAMC_IRQ_EN_RTSWCMDINT_EN Fld(1, 12) //[12:12] 965 #define DRAMC_IRQ_EN_TX_TRACKING_INT1_EN Fld(1, 16) //[16:16] 966 #define DRAMC_IRQ_EN_TX_TRACKING_INT2_EN Fld(1, 17) //[17:17] 967 #define DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV Fld(14, 18) //[31:18] 968 969 #define DRAMC_REG_DRAMC_IRQ_CLEAR (DRAMC_AO_BASE_ADDRESS + 0x02E4) 970 #define DRAMC_IRQ_CLEAR_MR4INT_CLR Fld(1, 0) //[0:0] 971 #define DRAMC_IRQ_CLEAR_REFPENDINGINT_CLR Fld(1, 1) //[1:1] 972 #define DRAMC_IRQ_CLEAR_PRE_MR4INT_CLR Fld(1, 2) //[2:2] 973 #define DRAMC_IRQ_CLEAR_RTMRWINT_CLR Fld(1, 3) //[3:3] 974 #define DRAMC_IRQ_CLEAR_INT_SREF_REQ_NO_ACK_CLR Fld(1, 6) //[6:6] 975 #define DRAMC_IRQ_CLEAR_INT_SREF_REQ_SHORT_CLR Fld(1, 7) //[7:7] 976 #define DRAMC_IRQ_CLEAR_INT_SREF_REQ_DTRIG_CLR Fld(1, 8) //[8:8] 977 #define DRAMC_IRQ_CLEAR_RTSWCMDINT_CLR Fld(1, 12) //[12:12] 978 #define DRAMC_IRQ_CLEAR_DRAMC_IRQ_CLEAR_RSV Fld(19, 13) //[31:13] 979 980 #define DRAMC_REG_IRQ_RSV1 (DRAMC_AO_BASE_ADDRESS + 0x02E8) 981 #define IRQ_RSV1_IRQ_RSV1 Fld(32, 0) //[31:0] 982 983 #define DRAMC_REG_IRQ_RSV2 (DRAMC_AO_BASE_ADDRESS + 0x02EC) 984 #define IRQ_RSV2_IRQ_RSV2 Fld(32, 0) //[31:0] 985 986 #define DRAMC_REG_REFCNT_FR_CLK1 (DRAMC_AO_BASE_ADDRESS + 0x02F0) 987 #define REFCNT_FR_CLK1_REFCNT_FR_CLK_1X Fld(11, 0) //[10:0] 988 #define REFCNT_FR_CLK1_REFCNT_FR_CLK_2X Fld(11, 16) //[26:16] 989 990 #define DRAMC_REG_REFCNT_FR_CLK2 (DRAMC_AO_BASE_ADDRESS + 0x02F4) 991 #define REFCNT_FR_CLK2_REFCNT_FR_CLK_4X Fld(11, 0) //[10:0] 992 #define REFCNT_FR_CLK2_REFCNT_FR_CLK_8X Fld(11, 16) //[26:16] 993 994 #define DRAMC_REG_REFCNT_FR_CLK3 (DRAMC_AO_BASE_ADDRESS + 0x02F8) 995 #define REFCNT_FR_CLK3_REFCNT_FR_CLK_0P25X Fld(11, 0) //[10:0] 996 #define REFCNT_FR_CLK3_REFCNT_FR_CLK_0P5X Fld(11, 16) //[26:16] 997 998 #define DRAMC_REG_REFCNT_FR_CLK4 (DRAMC_AO_BASE_ADDRESS + 0x02FC) 999 #define REFCNT_FR_CLK4_REFCNT_FR_CLK_1P3X Fld(11, 0) //[10:0] 1000 #define REFCNT_FR_CLK4_REFCNT_FR_CLK_1P7X Fld(11, 16) //[26:16] 1001 1002 #define DRAMC_REG_REFCNT_FR_CLK5 (DRAMC_AO_BASE_ADDRESS + 0x0300) 1003 #define REFCNT_FR_CLK5_REFCNT_FR_CLK_2P5X Fld(11, 0) //[10:0] 1004 #define REFCNT_FR_CLK5_REFCNT_FR_CLK_3P3X Fld(11, 16) //[26:16] 1005 1006 #define DRAMC_REG_REFCNT_FR_CLK6 (DRAMC_AO_BASE_ADDRESS + 0x0304) 1007 #define REFCNT_FR_CLK6_REFCNT_FR_CLK_6X Fld(11, 0) //[10:0] 1008 #define REFCNT_FR_CLK6_REFCNT_FR_CLK_0P7X Fld(11, 16) //[26:16] 1009 1010 #define DRAMC_REG_REFCNT_FR_CLK7 (DRAMC_AO_BASE_ADDRESS + 0x0308) 1011 #define REFCNT_FR_CLK7_REFCNT_FR_CLK_0P125X Fld(11, 0) //[10:0] 1012 1013 #define DRAMC_REG_DCM_SUB_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0310) 1014 #define DCM_SUB_CTRL_SUBCLK_CTRL_ZQ_CAL Fld(1, 0) //[0:0] 1015 #define DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING Fld(1, 1) //[1:1] 1016 #define DCM_SUB_CTRL_SUBCLK_CTRL_TEST2 Fld(1, 2) //[2:2] 1017 #define DCM_SUB_CTRL_SUBCLK_CTRL_SWCMD Fld(1, 3) //[3:3] 1018 #define DCM_SUB_CTRL_SUBCLK_CTRL_SREF Fld(1, 4) //[4:4] 1019 #define DCM_SUB_CTRL_SUBCLK_CTRL_SHUFFLE_SM Fld(1, 5) //[5:5] 1020 #define DCM_SUB_CTRL_SUBCLK_CTRL_REF Fld(1, 6) //[6:6] 1021 #define DCM_SUB_CTRL_SUBCLK_CTRL_PD_NEW Fld(1, 7) //[7:7] 1022 #define DCM_SUB_CTRL_SUBCLK_CTRL_HMR4 Fld(1, 8) //[8:8] 1023 #define DCM_SUB_CTRL_SUBCLK_CTRL_DUMMY_READ Fld(1, 9) //[9:9] 1024 #define DCM_SUB_CTRL_SUBCLK_CTRL_DPD Fld(1, 10) //[10:10] 1025 #define DCM_SUB_CTRL_SUBCLK_CTRL_CBT_WLEV Fld(1, 11) //[11:11] 1026 #define DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK Fld(1, 12) //[12:12] 1027 1028 #define DRAMC_REG_CBT_WLEV_CTRL5 (DRAMC_AO_BASE_ADDRESS + 0x0320) 1029 #define CBT_WLEV_CTRL5_NEW_CBT_CAPATEN Fld(1, 0) //[0:0] 1030 #define CBT_WLEV_CTRL5_NEW_CBT_CAGOLDEN_SEL Fld(3, 1) //[3:1] 1031 #define CBT_WLEV_CTRL5_NEW_CBT_PAT_INTV Fld(8, 4) //[11:4] 1032 #define CBT_WLEV_CTRL5_NEW_CBT_INVERT_NUM Fld(1, 12) //[12:12] 1033 #define CBT_WLEV_CTRL5_NEW_CBT_PAT_NUM Fld(3, 13) //[15:13] 1034 #define CBT_WLEV_CTRL5_NEW_CBT_CA_NUM Fld(4, 16) //[19:16] 1035 #define CBT_WLEV_CTRL5_NEW_CBT_PAT_RKSEL Fld(2, 20) //[21:20] 1036 #define CBT_WLEV_CTRL5_CBT_NEW_MODE Fld(1, 22) //[22:22] 1037 1038 #define DRAMC_REG_DRAM_CLK_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0330) 1039 #define DRAM_CLK_CTRL_CLK_EN Fld(1, 0) //[0:0] 1040 1041 #define DRAMC_REG_SCRAMBLE_CFG0 (DRAMC_AO_BASE_ADDRESS + 0x0334) 1042 #define SCRAMBLE_CFG0_SC_CFG0 Fld(32, 0) //[31:0] 1043 1044 #define DRAMC_REG_SCRAMBLE_CFG1 (DRAMC_AO_BASE_ADDRESS + 0x0338) 1045 #define SCRAMBLE_CFG1_SC_CFG1 Fld(32, 0) //[31:0] 1046 1047 #define DRAMC_REG_SCRAMBLE_CFG2 (DRAMC_AO_BASE_ADDRESS + 0x033C) 1048 #define SCRAMBLE_CFG2_SC_CFG2 Fld(32, 0) //[31:0] 1049 1050 #define DRAMC_REG_SCRAMBLE_CFG3 (DRAMC_AO_BASE_ADDRESS + 0x0340) 1051 #define SCRAMBLE_CFG3_SC_CFG3 Fld(32, 0) //[31:0] 1052 1053 #define DRAMC_REG_SCRAMBLE_CFG4 (DRAMC_AO_BASE_ADDRESS + 0x0344) 1054 #define SCRAMBLE_CFG4_SC_CFG4 Fld(32, 0) //[31:0] 1055 1056 #define DRAMC_REG_SCRAMBLE_CFG5 (DRAMC_AO_BASE_ADDRESS + 0x0348) 1057 #define SCRAMBLE_CFG5_SC_CFG5 Fld(32, 0) //[31:0] 1058 1059 #define DRAMC_REG_SCRAMBLE_CFG6 (DRAMC_AO_BASE_ADDRESS + 0x034C) 1060 #define SCRAMBLE_CFG6_SC_CFG6 Fld(32, 0) //[31:0] 1061 1062 #define DRAMC_REG_SCRAMBLE_CFG7 (DRAMC_AO_BASE_ADDRESS + 0x0350) 1063 #define SCRAMBLE_CFG7_SC_CFG7 Fld(32, 0) //[31:0] 1064 1065 #define DRAMC_REG_SCRAMBLE_CFG8 (DRAMC_AO_BASE_ADDRESS + 0x0354) 1066 #define SCRAMBLE_CFG8_SC_CMP_EN0 Fld(1, 0) //[0:0] 1067 #define SCRAMBLE_CFG8_SC_CMP_TYPE0 Fld(1, 2) //[2:2] 1068 #define SCRAMBLE_CFG8_SC_CMP_EN1 Fld(1, 4) //[4:4] 1069 #define SCRAMBLE_CFG8_SC_CMP_TYPE1 Fld(1, 6) //[6:6] 1070 #define SCRAMBLE_CFG8_SC_CMP_EN2 Fld(1, 8) //[8:8] 1071 #define SCRAMBLE_CFG8_SC_CMP_TYPE2 Fld(1, 10) //[10:10] 1072 #define SCRAMBLE_CFG8_SC_CMP_EN3 Fld(1, 12) //[12:12] 1073 #define SCRAMBLE_CFG8_SC_CMP_TYPE3 Fld(1, 14) //[14:14] 1074 #define SCRAMBLE_CFG8_SC_DDR_TYPE Fld(1, 16) //[16:16] 1075 #define SCRAMBLE_CFG8_SC_EX32_EN Fld(1, 17) //[17:17] 1076 #define SCRAMBLE_CFG8_SC_RETRUN_HUSKY Fld(1, 19) //[19:19] 1077 #define SCRAMBLE_CFG8_SC_EN Fld(1, 24) //[24:24] 1078 #define SCRAMBLE_CFG8_SC_CMP_SEL Fld(2, 28) //[29:28] 1079 1080 #define DRAMC_REG_SCRAMBLE_CFG9 (DRAMC_AO_BASE_ADDRESS + 0x0358) 1081 #define SCRAMBLE_CFG9_SC_DWADDR_3 Fld(16, 0) //[15:0] 1082 #define SCRAMBLE_CFG9_SC_UPADDR_3 Fld(16, 16) //[31:16] 1083 1084 #define DRAMC_REG_SCRAMBLE_CFGA (DRAMC_AO_BASE_ADDRESS + 0x035C) 1085 #define SCRAMBLE_CFGA_SC_DWADDR_2 Fld(16, 0) //[15:0] 1086 #define SCRAMBLE_CFGA_SC_UPADDR_2 Fld(16, 16) //[31:16] 1087 1088 #define DRAMC_REG_SCRAMBLE_CFGB (DRAMC_AO_BASE_ADDRESS + 0x0360) 1089 #define SCRAMBLE_CFGB_SC_DWADDR_1 Fld(16, 0) //[15:0] 1090 #define SCRAMBLE_CFGB_SC_UPADDR_1 Fld(16, 16) //[31:16] 1091 1092 #define DRAMC_REG_SCRAMBLE_CFGC (DRAMC_AO_BASE_ADDRESS + 0x0364) 1093 #define SCRAMBLE_CFGC_SC_DWADDR_0 Fld(16, 0) //[15:0] 1094 #define SCRAMBLE_CFGC_SC_UPADDR_0 Fld(16, 16) //[31:16] 1095 1096 #define DRAMC_REG_SCRAMBLE_CFGD (DRAMC_AO_BASE_ADDRESS + 0x0368) 1097 #define SCRAMBLE_CFGD_SC_CFGD Fld(32, 0) //[31:0] 1098 1099 #define DRAMC_REG_SCRAMBLE_CFGE (DRAMC_AO_BASE_ADDRESS + 0x036C) 1100 #define SCRAMBLE_CFGE_SC_CFGE Fld(32, 0) //[31:0] 1101 1102 #define DRAMC_REG_SCRAMBLE_CFGF (DRAMC_AO_BASE_ADDRESS + 0x0370) 1103 #define SCRAMBLE_CFGF_SC_CFGF Fld(32, 0) //[31:0] 1104 1105 #define DRAMC_REG_RK_TEST2_A1 (DRAMC_AO_BASE_ADDRESS + 0x0500) 1106 #define RK_TEST2_A1_TEST2_BASE Fld(29, 3) //[31:3] 1107 1108 #define DRAMC_REG_RK_DUMMY_RD_WDATA0 (DRAMC_AO_BASE_ADDRESS + 0x0504) 1109 #define RK_DUMMY_RD_WDATA0_DMY_RD_WDATA0 Fld(32, 0) //[31:0] 1110 1111 #define DRAMC_REG_RK_DUMMY_RD_WDATA1 (DRAMC_AO_BASE_ADDRESS + 0x0508) 1112 #define RK_DUMMY_RD_WDATA1_DMY_RD_WDATA1 Fld(32, 0) //[31:0] 1113 1114 #define DRAMC_REG_RK_DUMMY_RD_WDATA2 (DRAMC_AO_BASE_ADDRESS + 0x050C) 1115 #define RK_DUMMY_RD_WDATA2_DMY_RD_WDATA2 Fld(32, 0) //[31:0] 1116 1117 #define DRAMC_REG_RK_DUMMY_RD_WDATA3 (DRAMC_AO_BASE_ADDRESS + 0x0510) 1118 #define RK_DUMMY_RD_WDATA3_DMY_RD_WDATA3 Fld(32, 0) //[31:0] 1119 1120 #define DRAMC_REG_RK_DUMMY_RD_ADR (DRAMC_AO_BASE_ADDRESS + 0x0514) 1121 #define RK_DUMMY_RD_ADR_DMY_RD_COL_ADR Fld(11, 17) //[27:17] 1122 #define RK_DUMMY_RD_ADR_DMY_RD_LEN Fld(4, 28) //[31:28] 1123 1124 #define DRAMC_REG_RK_DUMMY_RD_ADR2 (DRAMC_AO_BASE_ADDRESS + 0x0554) 1125 #define RK_DUMMY_RD_ADR2_DMY_RD_BK Fld(4, 0) //[3:0] 1126 #define RK_DUMMY_RD_ADR2_DMY_RD_ROW_ADR Fld(18, 4) //[21:4] 1127 1128 #define DRAMC_REG_RK_SREF_DPD_TCK_RK_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0568) 1129 #define RK_SREF_DPD_TCK_RK_CTRL_DPD_EN Fld(1, 29) //[29:29] 1130 #define RK_SREF_DPD_TCK_RK_CTRL_DPDX_EN Fld(1, 30) //[30:30] 1131 #define RK_SREF_DPD_TCK_RK_CTRL_SRF_EN Fld(1, 31) //[31:31] 1132 1133 #define DRAMC_REG_RK_DQSOSC (DRAMC_AO_BASE_ADDRESS + 0x0590) 1134 #define RK_DQSOSC_RK0_BYTE_MODE Fld(1, 29) //[29:29] 1135 #define RK_DQSOSC_DQSOSCR_RK0EN Fld(1, 30) //[30:30] 1136 #define RK_DQSOSC_DQSOSC_RK0INTCLR Fld(1, 31) //[31:31] 1137 1138 #define DRAMC_REG_WDT_DBG_SIGNAL (DRAMC_AO_BASE_ADDRESS + 0x0D00) 1139 #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_CPT2_RK0_FROM_AO Fld(1, 0) //[0:0] 1140 #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_CPT2_RK1_FROM_AO Fld(1, 1) //[1:1] 1141 #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_ERR2_RK0_FROM_AO Fld(1, 2) //[2:2] 1142 #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_ERR2_RK1_FROM_AO Fld(1, 3) //[3:3] 1143 #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DLE_CNT_OK2_RK0_FROM_AO Fld(1, 4) //[4:4] 1144 #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DLE_CNT_OK2_RK1_FROM_AO Fld(1, 5) //[5:5] 1145 #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_CPT2_RK0_FROM_AO Fld(1, 8) //[8:8] 1146 #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_CPT2_RK1_FROM_AO Fld(1, 9) //[9:9] 1147 #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_ERR2_RK0_FROM_AO Fld(1, 10) //[10:10] 1148 #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_ERR2_RK1_FROM_AO Fld(1, 11) //[11:11] 1149 #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DLE_CNT_OK2_RK0_FROM_AO Fld(1, 12) //[12:12] 1150 #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DLE_CNT_OK2_RK1_FROM_AO Fld(1, 13) //[13:13] 1151 #define WDT_DBG_SIGNAL_LATCH_DRAMC_GATING_ERROR_FROM_AO Fld(1, 14) //[14:14] 1152 1153 #define DRAMC_REG_SELFREF_HWSAVE_FLAG (DRAMC_AO_BASE_ADDRESS + 0x0D08) 1154 #define SELFREF_HWSAVE_FLAG_SELFREF_HWSAVE_FLAG_FROM_AO Fld(1, 0) //[0:0] 1155 1156 #define DRAMC_REG_DRAMC_IRQ_STATUS1 (DRAMC_AO_BASE_ADDRESS + 0x0F00) 1157 #define DRAMC_IRQ_STATUS1_DRAMC_IRQ_STATUS1_X0 Fld(32, 0) //[31:0] 1158 1159 #define DRAMC_REG_DRAMC_IRQ_STATUS2 (DRAMC_AO_BASE_ADDRESS + 0x0F04) 1160 #define DRAMC_IRQ_STATUS2_DRAMC_IRQ_STATUS2_X0 Fld(32, 0) //[31:0] 1161 1162 #define DRAMC_REG_DRAMC_IRQ_INFO1 (DRAMC_AO_BASE_ADDRESS + 0x0F10) 1163 #define DRAMC_IRQ_INFO1_REFRESH_RATE_FOR_INT_X0 Fld(5, 0) //[4:0] 1164 #define DRAMC_IRQ_INFO1_REFRESH_QUEUE_CNT_FOR_INT_X0 Fld(4, 8) //[11:8] 1165 #define DRAMC_IRQ_INFO1_REFRESH_RATE_CHG_QUEUE_CNT_FOR_INT_X0 Fld(4, 12) //[15:12] 1166 1167 #define DRAMC_REG_DRAMC_IRQ_INFO1A (DRAMC_AO_BASE_ADDRESS + 0x0F14) 1168 #define DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK0_FOR_INT_X0 Fld(5, 0) //[4:0] 1169 #define DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK1_FOR_INT_X0 Fld(5, 8) //[12:8] 1170 #define DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK0_B1_FOR_INT_X0 Fld(5, 16) //[20:16] 1171 #define DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK1_B1_FOR_INT_X0 Fld(5, 24) //[28:24] 1172 1173 #define DRAMC_REG_DRAMC_IRQ_INFO2 (DRAMC_AO_BASE_ADDRESS + 0x0F20) 1174 #define DRAMC_IRQ_INFO2_RK0_MR18_INT1_X0 Fld(16, 0) //[15:0] 1175 #define DRAMC_IRQ_INFO2_RK0_MR19_INT1_X0 Fld(16, 16) //[31:16] 1176 1177 #define DRAMC_REG_DRAMC_IRQ_INFO3 (DRAMC_AO_BASE_ADDRESS + 0x0F24) 1178 #define DRAMC_IRQ_INFO3_RK1_MR18_INT1_X0 Fld(16, 0) //[15:0] 1179 #define DRAMC_IRQ_INFO3_RK1_MR19_INT1_X0 Fld(16, 16) //[31:16] 1180 1181 #define DRAMC_REG_DRAMC_IRQ_INFO4 (DRAMC_AO_BASE_ADDRESS + 0x0F28) 1182 #define DRAMC_IRQ_INFO4_RK0_MR18_INT2_X0 Fld(16, 0) //[15:0] 1183 #define DRAMC_IRQ_INFO4_RK0_MR19_INT2_X0 Fld(16, 16) //[31:16] 1184 1185 #define DRAMC_REG_DRAMC_IRQ_INFO5 (DRAMC_AO_BASE_ADDRESS + 0x0F2C) 1186 #define DRAMC_IRQ_INFO5_RK1_MR18_INT2_X0 Fld(16, 0) //[15:0] 1187 #define DRAMC_IRQ_INFO5_RK1_MR19_INT2_X0 Fld(16, 16) //[31:16] 1188 1189 #define DRAMC_REG_SHURK_SELPH_DQ0 (DRAMC_AO_BASE_ADDRESS + 0x1200) 1190 #define SHURK_SELPH_DQ0_TXDLY_DQ0 Fld(3, 0) //[2:0] 1191 #define SHURK_SELPH_DQ0_TXDLY_DQ1 Fld(3, 4) //[6:4] 1192 #define SHURK_SELPH_DQ0_TXDLY_DQ2 Fld(3, 8) //[10:8] 1193 #define SHURK_SELPH_DQ0_TXDLY_DQ3 Fld(3, 12) //[14:12] 1194 #define SHURK_SELPH_DQ0_TXDLY_OEN_DQ0 Fld(3, 16) //[18:16] 1195 #define SHURK_SELPH_DQ0_TXDLY_OEN_DQ1 Fld(3, 20) //[22:20] 1196 #define SHURK_SELPH_DQ0_TXDLY_OEN_DQ2 Fld(3, 24) //[26:24] 1197 #define SHURK_SELPH_DQ0_TXDLY_OEN_DQ3 Fld(3, 28) //[30:28] 1198 1199 #define DRAMC_REG_SHURK_SELPH_DQ1 (DRAMC_AO_BASE_ADDRESS + 0x1204) 1200 #define SHURK_SELPH_DQ1_TXDLY_DQM0 Fld(3, 0) //[2:0] 1201 #define SHURK_SELPH_DQ1_TXDLY_DQM1 Fld(3, 4) //[6:4] 1202 #define SHURK_SELPH_DQ1_TXDLY_DQM2 Fld(3, 8) //[10:8] 1203 #define SHURK_SELPH_DQ1_TXDLY_DQM3 Fld(3, 12) //[14:12] 1204 #define SHURK_SELPH_DQ1_TXDLY_OEN_DQM0 Fld(3, 16) //[18:16] 1205 #define SHURK_SELPH_DQ1_TXDLY_OEN_DQM1 Fld(3, 20) //[22:20] 1206 #define SHURK_SELPH_DQ1_TXDLY_OEN_DQM2 Fld(3, 24) //[26:24] 1207 #define SHURK_SELPH_DQ1_TXDLY_OEN_DQM3 Fld(3, 28) //[30:28] 1208 1209 #define DRAMC_REG_SHURK_SELPH_DQ2 (DRAMC_AO_BASE_ADDRESS + 0x1208) 1210 #define SHURK_SELPH_DQ2_DLY_DQ0 Fld(4, 0) //[3:0] 1211 #define SHURK_SELPH_DQ2_DLY_DQ1 Fld(4, 4) //[7:4] 1212 #define SHURK_SELPH_DQ2_DLY_DQ2 Fld(4, 8) //[11:8] 1213 #define SHURK_SELPH_DQ2_DLY_DQ3 Fld(4, 12) //[15:12] 1214 #define SHURK_SELPH_DQ2_DLY_OEN_DQ0 Fld(4, 16) //[19:16] 1215 #define SHURK_SELPH_DQ2_DLY_OEN_DQ1 Fld(4, 20) //[23:20] 1216 #define SHURK_SELPH_DQ2_DLY_OEN_DQ2 Fld(4, 24) //[27:24] 1217 #define SHURK_SELPH_DQ2_DLY_OEN_DQ3 Fld(4, 28) //[31:28] 1218 1219 #define DRAMC_REG_SHURK_SELPH_DQ3 (DRAMC_AO_BASE_ADDRESS + 0x120C) 1220 #define SHURK_SELPH_DQ3_DLY_DQM0 Fld(4, 0) //[3:0] 1221 #define SHURK_SELPH_DQ3_DLY_DQM1 Fld(4, 4) //[7:4] 1222 #define SHURK_SELPH_DQ3_DLY_DQM2 Fld(4, 8) //[11:8] 1223 #define SHURK_SELPH_DQ3_DLY_DQM3 Fld(4, 12) //[15:12] 1224 #define SHURK_SELPH_DQ3_DLY_OEN_DQM0 Fld(4, 16) //[19:16] 1225 #define SHURK_SELPH_DQ3_DLY_OEN_DQM1 Fld(4, 20) //[23:20] 1226 #define SHURK_SELPH_DQ3_DLY_OEN_DQM2 Fld(4, 24) //[27:24] 1227 #define SHURK_SELPH_DQ3_DLY_OEN_DQM3 Fld(4, 28) //[31:28] 1228 1229 #define DRAMC_REG_SHURK_DQS2DQ_CAL1 (DRAMC_AO_BASE_ADDRESS + 0x1210) 1230 #define SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0 Fld(11, 0) //[10:0] 1231 #define SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1 Fld(11, 16) //[26:16] 1232 1233 #define DRAMC_REG_SHURK_DQS2DQ_CAL2 (DRAMC_AO_BASE_ADDRESS + 0x1214) 1234 #define SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0 Fld(11, 0) //[10:0] 1235 #define SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1 Fld(11, 16) //[26:16] 1236 1237 #define DRAMC_REG_SHURK_DQS2DQ_CAL3 (DRAMC_AO_BASE_ADDRESS + 0x1218) 1238 #define SHURK_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0 Fld(6, 0) //[5:0] 1239 #define SHURK_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1 Fld(6, 6) //[11:6] 1240 #define SHURK_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0 Fld(5, 12) //[16:12] 1241 #define SHURK_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0 Fld(5, 17) //[21:17] 1242 1243 #define DRAMC_REG_SHURK_DQS2DQ_CAL4 (DRAMC_AO_BASE_ADDRESS + 0x121C) 1244 #define SHURK_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0 Fld(6, 0) //[5:0] 1245 #define SHURK_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1 Fld(6, 6) //[11:6] 1246 #define SHURK_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0 Fld(5, 12) //[16:12] 1247 #define SHURK_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0 Fld(5, 17) //[21:17] 1248 1249 #define DRAMC_REG_SHURK_DQS2DQ_CAL5 (DRAMC_AO_BASE_ADDRESS + 0x1220) 1250 #define SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0 Fld(11, 0) //[10:0] 1251 #define SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1 Fld(11, 16) //[26:16] 1252 1253 #define DRAMC_REG_SHURK_PI (DRAMC_AO_BASE_ADDRESS + 0x1224) 1254 #define SHURK_PI_RK0_ARPI_DQ_B1 Fld(6, 0) //[5:0] 1255 #define SHURK_PI_RK0_ARPI_DQ_B0 Fld(6, 8) //[13:8] 1256 #define SHURK_PI_RK0_ARPI_DQM_B1 Fld(6, 16) //[21:16] 1257 #define SHURK_PI_RK0_ARPI_DQM_B0 Fld(6, 24) //[29:24] 1258 1259 #define DRAMC_REG_SHURK_DQSOSC (DRAMC_AO_BASE_ADDRESS + 0x1228) 1260 #define SHURK_DQSOSC_DQSOSC_BASE_RK0 Fld(16, 0) //[15:0] 1261 #define SHURK_DQSOSC_DQSOSC_BASE_RK0_B1 Fld(16, 16) //[31:16] 1262 1263 #define DRAMC_REG_SHURK_DQSOSC_THRD (DRAMC_AO_BASE_ADDRESS + 0x122C) 1264 #define SHURK_DQSOSC_THRD_DQSOSCTHRD_INC Fld(12, 0) //[11:0] 1265 #define SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC Fld(12, 16) //[27:16] 1266 1267 #define DRAMC_REG_SHURK_APHY_TX_PICG_CTRL (DRAMC_AO_BASE_ADDRESS + 0x1230) 1268 #define SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 Fld(3, 0) //[2:0] 1269 #define SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 Fld(3, 4) //[6:4] 1270 1271 #define DRAMC_REG_SHURK_WCK_WR_MCK (DRAMC_AO_BASE_ADDRESS + 0x1240) 1272 #define SHURK_WCK_WR_MCK_WCK_WR_B0_MCK Fld(4, 0) //[3:0] 1273 #define SHURK_WCK_WR_MCK_WCK_WR_B1_MCK Fld(4, 4) //[7:4] 1274 1275 #define DRAMC_REG_SHURK_WCK_RD_MCK (DRAMC_AO_BASE_ADDRESS + 0x1244) 1276 #define SHURK_WCK_RD_MCK_WCK_RD_B0_MCK Fld(4, 0) //[3:0] 1277 #define SHURK_WCK_RD_MCK_WCK_RD_B1_MCK Fld(4, 4) //[7:4] 1278 1279 #define DRAMC_REG_SHURK_WCK_FS_MCK (DRAMC_AO_BASE_ADDRESS + 0x1248) 1280 #define SHURK_WCK_FS_MCK_WCK_FS_B0_MCK Fld(4, 0) //[3:0] 1281 #define SHURK_WCK_FS_MCK_WCK_FS_B1_MCK Fld(4, 4) //[7:4] 1282 1283 #define DRAMC_REG_SHURK_WCK_WR_UI (DRAMC_AO_BASE_ADDRESS + 0x124C) 1284 #define SHURK_WCK_WR_UI_WCK_WR_B0_UI Fld(4, 0) //[3:0] 1285 #define SHURK_WCK_WR_UI_WCK_WR_B1_UI Fld(4, 4) //[7:4] 1286 1287 #define DRAMC_REG_SHURK_WCK_RD_UI (DRAMC_AO_BASE_ADDRESS + 0x1250) 1288 #define SHURK_WCK_RD_UI_WCK_RD_B0_UI Fld(4, 0) //[3:0] 1289 #define SHURK_WCK_RD_UI_WCK_RD_B1_UI Fld(4, 4) //[7:4] 1290 1291 #define DRAMC_REG_SHURK_WCK_FS_UI (DRAMC_AO_BASE_ADDRESS + 0x1254) 1292 #define SHURK_WCK_FS_UI_WCK_FS_B0_UI Fld(4, 0) //[3:0] 1293 #define SHURK_WCK_FS_UI_WCK_FS_B1_UI Fld(4, 4) //[7:4] 1294 1295 #define DRAMC_REG_SHURK_CKE_CTRL (DRAMC_AO_BASE_ADDRESS + 0x1260) 1296 #define SHURK_CKE_CTRL_CKE_DBE_CNT Fld(4, 0) //[3:0] 1297 1298 #define DRAMC_REG_SHU_MATYPE (DRAMC_AO_BASE_ADDRESS + 0x1600) 1299 #define SHU_MATYPE_MATYPE Fld(2, 0) //[1:0] 1300 #define SHU_MATYPE_NORMPOP_LEN Fld(3, 4) //[6:4] 1301 1302 #define DRAMC_REG_SHU_COMMON0 (DRAMC_AO_BASE_ADDRESS + 0x1604) 1303 #define SHU_COMMON0_FREQDIV4 Fld(1, 0) //[0:0] 1304 #define SHU_COMMON0_FDIV2 Fld(1, 1) //[1:1] 1305 #define SHU_COMMON0_FREQDIV8 Fld(1, 2) //[2:2] 1306 #define SHU_COMMON0_DM64BITEN Fld(1, 4) //[4:4] 1307 #define SHU_COMMON0_DLE256EN Fld(1, 5) //[5:5] 1308 #define SHU_COMMON0_LP5BGEN Fld(1, 6) //[6:6] 1309 #define SHU_COMMON0_LP5WCKON Fld(1, 7) //[7:7] 1310 #define SHU_COMMON0_CL2 Fld(1, 8) //[8:8] 1311 #define SHU_COMMON0_BL2 Fld(1, 9) //[9:9] 1312 #define SHU_COMMON0_BL4 Fld(1, 10) //[10:10] 1313 #define SHU_COMMON0_LP5BGOTF Fld(1, 11) //[11:11] 1314 #define SHU_COMMON0_BC4OTF Fld(1, 12) //[12:12] 1315 #define SHU_COMMON0_LP5HEFF_MODE Fld(1, 13) //[13:13] 1316 #define SHU_COMMON0_LP5WRAPEN Fld(1, 14) //[14:14] 1317 #define SHU_COMMON0_SHU_COMMON0_RSV Fld(17, 15) //[31:15] 1318 1319 #define DRAMC_REG_SHU_SREF_CTRL (DRAMC_AO_BASE_ADDRESS + 0x1608) 1320 #define SHU_SREF_CTRL_CKEHCMD Fld(2, 4) //[5:4] 1321 #define SHU_SREF_CTRL_SREF_CK_DLY Fld(2, 28) //[29:28] 1322 1323 #define DRAMC_REG_SHU_SCHEDULER (DRAMC_AO_BASE_ADDRESS + 0x160C) 1324 #define SHU_SCHEDULER_DUALSCHEN Fld(1, 2) //[2:2] 1325 1326 #define DRAMC_REG_SHU_DCM_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x1610) 1327 #define SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT Fld(1, 7) //[7:7] 1328 #define SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT Fld(3, 8) //[10:8] 1329 #define SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL Fld(4, 12) //[15:12] 1330 #define SHU_DCM_CTRL0_APHYPI_CKCGL_CNT Fld(4, 16) //[19:16] 1331 #define SHU_DCM_CTRL0_APHYPI_CKCGH_CNT Fld(4, 20) //[23:20] 1332 #define SHU_DCM_CTRL0_FASTWAKE2 Fld(1, 29) //[29:29] 1333 #define SHU_DCM_CTRL0_FASTWAKE Fld(1, 31) //[31:31] 1334 1335 #define DRAMC_REG_SHU_HMR4_DVFS_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x1614) 1336 #define SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT Fld(8, 8) //[15:8] 1337 #define SHU_HMR4_DVFS_CTRL0_REFRCNT Fld(12, 16) //[27:16] 1338 1339 #define DRAMC_REG_SHU_SELPH_CA1 (DRAMC_AO_BASE_ADDRESS + 0x1618) 1340 #define SHU_SELPH_CA1_TXDLY_CS Fld(3, 0) //[2:0] 1341 #define SHU_SELPH_CA1_TXDLY_CKE Fld(3, 4) //[6:4] 1342 #define SHU_SELPH_CA1_TXDLY_ODT Fld(3, 8) //[10:8] 1343 #define SHU_SELPH_CA1_TXDLY_RESET Fld(3, 12) //[14:12] 1344 #define SHU_SELPH_CA1_TXDLY_WE Fld(3, 16) //[18:16] 1345 #define SHU_SELPH_CA1_TXDLY_CAS Fld(3, 20) //[22:20] 1346 #define SHU_SELPH_CA1_TXDLY_RAS Fld(3, 24) //[26:24] 1347 #define SHU_SELPH_CA1_TXDLY_CS1 Fld(3, 28) //[30:28] 1348 1349 #define DRAMC_REG_SHU_SELPH_CA2 (DRAMC_AO_BASE_ADDRESS + 0x161C) 1350 #define SHU_SELPH_CA2_TXDLY_BA0 Fld(3, 0) //[2:0] 1351 #define SHU_SELPH_CA2_TXDLY_BA1 Fld(3, 4) //[6:4] 1352 #define SHU_SELPH_CA2_TXDLY_BA2 Fld(3, 8) //[10:8] 1353 #define SHU_SELPH_CA2_TXDLY_CMD Fld(5, 16) //[20:16] 1354 #define SHU_SELPH_CA2_TXDLY_CKE1 Fld(3, 24) //[26:24] 1355 1356 #define DRAMC_REG_SHU_SELPH_CA3 (DRAMC_AO_BASE_ADDRESS + 0x1620) 1357 #define SHU_SELPH_CA3_TXDLY_RA0 Fld(3, 0) //[2:0] 1358 #define SHU_SELPH_CA3_TXDLY_RA1 Fld(3, 4) //[6:4] 1359 #define SHU_SELPH_CA3_TXDLY_RA2 Fld(3, 8) //[10:8] 1360 #define SHU_SELPH_CA3_TXDLY_RA3 Fld(3, 12) //[14:12] 1361 #define SHU_SELPH_CA3_TXDLY_RA4 Fld(3, 16) //[18:16] 1362 #define SHU_SELPH_CA3_TXDLY_RA5 Fld(3, 20) //[22:20] 1363 #define SHU_SELPH_CA3_TXDLY_RA6 Fld(3, 24) //[26:24] 1364 #define SHU_SELPH_CA3_TXDLY_RA7 Fld(3, 28) //[30:28] 1365 1366 #define DRAMC_REG_SHU_SELPH_CA4 (DRAMC_AO_BASE_ADDRESS + 0x1624) 1367 #define SHU_SELPH_CA4_TXDLY_RA8 Fld(3, 0) //[2:0] 1368 #define SHU_SELPH_CA4_TXDLY_RA9 Fld(3, 4) //[6:4] 1369 #define SHU_SELPH_CA4_TXDLY_RA10 Fld(3, 8) //[10:8] 1370 #define SHU_SELPH_CA4_TXDLY_RA11 Fld(3, 12) //[14:12] 1371 #define SHU_SELPH_CA4_TXDLY_RA12 Fld(3, 16) //[18:16] 1372 #define SHU_SELPH_CA4_TXDLY_RA13 Fld(3, 20) //[22:20] 1373 #define SHU_SELPH_CA4_TXDLY_RA14 Fld(3, 24) //[26:24] 1374 #define SHU_SELPH_CA4_TXDLY_RA15 Fld(3, 28) //[30:28] 1375 1376 #define DRAMC_REG_SHU_SELPH_CA5 (DRAMC_AO_BASE_ADDRESS + 0x1628) 1377 #define SHU_SELPH_CA5_DLY_CS Fld(3, 0) //[2:0] 1378 #define SHU_SELPH_CA5_DLY_CKE Fld(3, 4) //[6:4] 1379 #define SHU_SELPH_CA5_DLY_ODT Fld(3, 8) //[10:8] 1380 #define SHU_SELPH_CA5_DLY_RESET Fld(3, 12) //[14:12] 1381 #define SHU_SELPH_CA5_DLY_WE Fld(3, 16) //[18:16] 1382 #define SHU_SELPH_CA5_DLY_CAS Fld(3, 20) //[22:20] 1383 #define SHU_SELPH_CA5_DLY_RAS Fld(3, 24) //[26:24] 1384 #define SHU_SELPH_CA5_DLY_CS1 Fld(3, 28) //[30:28] 1385 1386 #define DRAMC_REG_SHU_SELPH_CA6 (DRAMC_AO_BASE_ADDRESS + 0x162C) 1387 #define SHU_SELPH_CA6_DLY_BA0 Fld(3, 0) //[2:0] 1388 #define SHU_SELPH_CA6_DLY_BA1 Fld(3, 4) //[6:4] 1389 #define SHU_SELPH_CA6_DLY_BA2 Fld(3, 8) //[10:8] 1390 #define SHU_SELPH_CA6_DLY_CKE1 Fld(3, 24) //[26:24] 1391 1392 #define DRAMC_REG_SHU_SELPH_CA7 (DRAMC_AO_BASE_ADDRESS + 0x1630) 1393 #define SHU_SELPH_CA7_DLY_RA0 Fld(3, 0) //[2:0] 1394 #define SHU_SELPH_CA7_DLY_RA1 Fld(3, 4) //[6:4] 1395 #define SHU_SELPH_CA7_DLY_RA2 Fld(3, 8) //[10:8] 1396 #define SHU_SELPH_CA7_DLY_RA3 Fld(3, 12) //[14:12] 1397 #define SHU_SELPH_CA7_DLY_RA4 Fld(3, 16) //[18:16] 1398 #define SHU_SELPH_CA7_DLY_RA5 Fld(3, 20) //[22:20] 1399 #define SHU_SELPH_CA7_DLY_RA6 Fld(3, 24) //[26:24] 1400 #define SHU_SELPH_CA7_DLY_RA7 Fld(3, 28) //[30:28] 1401 1402 #define DRAMC_REG_SHU_SELPH_CA8 (DRAMC_AO_BASE_ADDRESS + 0x1634) 1403 #define SHU_SELPH_CA8_DLY_RA8 Fld(3, 0) //[2:0] 1404 #define SHU_SELPH_CA8_DLY_RA9 Fld(3, 4) //[6:4] 1405 #define SHU_SELPH_CA8_DLY_RA10 Fld(3, 8) //[10:8] 1406 #define SHU_SELPH_CA8_DLY_RA11 Fld(3, 12) //[14:12] 1407 #define SHU_SELPH_CA8_DLY_RA12 Fld(3, 16) //[18:16] 1408 #define SHU_SELPH_CA8_DLY_RA13 Fld(3, 20) //[22:20] 1409 #define SHU_SELPH_CA8_DLY_RA14 Fld(3, 24) //[26:24] 1410 #define SHU_SELPH_CA8_DLY_RA15 Fld(3, 28) //[30:28] 1411 1412 #define DRAMC_REG_SHU_HWSET_MR2 (DRAMC_AO_BASE_ADDRESS + 0x1638) 1413 #define SHU_HWSET_MR2_HWSET_MR2_MRSMA Fld(13, 0) //[12:0] 1414 #define SHU_HWSET_MR2_HWSET_MR2_OP Fld(8, 16) //[23:16] 1415 1416 #define DRAMC_REG_SHU_HWSET_MR13 (DRAMC_AO_BASE_ADDRESS + 0x163C) 1417 #define SHU_HWSET_MR13_HWSET_MR13_MRSMA Fld(13, 0) //[12:0] 1418 #define SHU_HWSET_MR13_HWSET_MR13_OP Fld(8, 16) //[23:16] 1419 1420 #define DRAMC_REG_SHU_HWSET_VRCG (DRAMC_AO_BASE_ADDRESS + 0x1640) 1421 #define SHU_HWSET_VRCG_HWSET_VRCG_MRSMA Fld(13, 0) //[12:0] 1422 #define SHU_HWSET_VRCG_HWSET_VRCG_OP Fld(8, 16) //[23:16] 1423 #define SHU_HWSET_VRCG_VRCGDIS_PRDCNT Fld(8, 24) //[31:24] 1424 1425 #define DRAMC_REG_SHU_ACTIM0 (DRAMC_AO_BASE_ADDRESS + 0x1644) 1426 #define SHU_ACTIM0_TWTR Fld(6, 0) //[5:0] 1427 #define SHU_ACTIM0_TWR Fld(8, 8) //[15:8] 1428 #define SHU_ACTIM0_TRRD Fld(3, 16) //[18:16] 1429 #define SHU_ACTIM0_TRCD Fld(4, 24) //[27:24] 1430 #define SHU_ACTIM0_CKELCKCNT Fld(4, 28) //[31:28] 1431 1432 #define DRAMC_REG_SHU_ACTIM1 (DRAMC_AO_BASE_ADDRESS + 0x1648) 1433 #define SHU_ACTIM1_TRPAB Fld(4, 0) //[3:0] 1434 #define SHU_ACTIM1_TMRWCKEL Fld(4, 4) //[7:4] 1435 #define SHU_ACTIM1_TRP Fld(4, 8) //[11:8] 1436 #define SHU_ACTIM1_TRAS Fld(6, 16) //[21:16] 1437 #define SHU_ACTIM1_TRC Fld(5, 24) //[28:24] 1438 1439 #define DRAMC_REG_SHU_ACTIM2 (DRAMC_AO_BASE_ADDRESS + 0x164C) 1440 #define SHU_ACTIM2_TXP Fld(4, 0) //[3:0] 1441 #define SHU_ACTIM2_TMRRI Fld(5, 4) //[8:4] 1442 #define SHU_ACTIM2_TRTP Fld(3, 12) //[14:12] 1443 #define SHU_ACTIM2_TR2W Fld(6, 16) //[21:16] 1444 #define SHU_ACTIM2_TFAW Fld(5, 24) //[28:24] 1445 1446 #define DRAMC_REG_SHU_ACTIM3 (DRAMC_AO_BASE_ADDRESS + 0x1650) 1447 #define SHU_ACTIM3_TRFCPB Fld(8, 0) //[7:0] 1448 #define SHU_ACTIM3_MANTMRR Fld(4, 8) //[11:8] 1449 #define SHU_ACTIM3_TR2MRR Fld(4, 12) //[15:12] 1450 #define SHU_ACTIM3_TRFC Fld(8, 16) //[23:16] 1451 #define SHU_ACTIM3_TWTR_L Fld(6, 24) //[29:24] 1452 1453 #define DRAMC_REG_SHU_ACTIM4 (DRAMC_AO_BASE_ADDRESS + 0x1654) 1454 #define SHU_ACTIM4_TXREFCNT Fld(10, 0) //[9:0] 1455 #define SHU_ACTIM4_TMRR2MRW Fld(6, 10) //[15:10] 1456 #define SHU_ACTIM4_TMRR2W Fld(6, 16) //[21:16] 1457 #define SHU_ACTIM4_TZQCS Fld(8, 24) //[31:24] 1458 1459 #define DRAMC_REG_SHU_ACTIM5 (DRAMC_AO_BASE_ADDRESS + 0x1658) 1460 #define SHU_ACTIM5_TR2PD Fld(7, 0) //[6:0] 1461 #define SHU_ACTIM5_TWTPD Fld(7, 8) //[14:8] 1462 #define SHU_ACTIM5_TPBR2PBR Fld(8, 16) //[23:16] 1463 #define SHU_ACTIM5_TPBR2ACT Fld(2, 28) //[29:28] 1464 1465 #define DRAMC_REG_SHU_ACTIM6 (DRAMC_AO_BASE_ADDRESS + 0x165C) 1466 #define SHU_ACTIM6_TZQLAT2 Fld(5, 0) //[4:0] 1467 #define SHU_ACTIM6_TMRD Fld(4, 8) //[11:8] 1468 #define SHU_ACTIM6_TMRW Fld(4, 12) //[15:12] 1469 #define SHU_ACTIM6_TW2MRW Fld(6, 20) //[25:20] 1470 #define SHU_ACTIM6_TR2MRW Fld(6, 26) //[31:26] 1471 1472 #define DRAMC_REG_SHU_ACTIM_XRT (DRAMC_AO_BASE_ADDRESS + 0x1660) 1473 #define SHU_ACTIM_XRT_XRTR2R Fld(5, 0) //[4:0] 1474 #define SHU_ACTIM_XRT_XRTR2W Fld(6, 8) //[13:8] 1475 #define SHU_ACTIM_XRT_XRTW2R Fld(4, 16) //[19:16] 1476 #define SHU_ACTIM_XRT_XRTW2W Fld(5, 24) //[28:24] 1477 1478 #define DRAMC_REG_SHU_AC_TIME_05T (DRAMC_AO_BASE_ADDRESS + 0x1664) 1479 #define SHU_AC_TIME_05T_TRC_05T Fld(1, 0) //[0:0] 1480 #define SHU_AC_TIME_05T_TRFCPB_05T Fld(1, 1) //[1:1] 1481 #define SHU_AC_TIME_05T_TRFC_05T Fld(1, 2) //[2:2] 1482 #define SHU_AC_TIME_05T_TPBR2PBR_05T Fld(1, 3) //[3:3] 1483 #define SHU_AC_TIME_05T_TXP_05T Fld(1, 4) //[4:4] 1484 #define SHU_AC_TIME_05T_TRTP_05T Fld(1, 5) //[5:5] 1485 #define SHU_AC_TIME_05T_TRCD_05T Fld(1, 6) //[6:6] 1486 #define SHU_AC_TIME_05T_TRP_05T Fld(1, 7) //[7:7] 1487 #define SHU_AC_TIME_05T_TRPAB_05T Fld(1, 8) //[8:8] 1488 #define SHU_AC_TIME_05T_TRAS_05T Fld(1, 9) //[9:9] 1489 #define SHU_AC_TIME_05T_TWR_M05T Fld(1, 10) //[10:10] 1490 #define SHU_AC_TIME_05T_TRRD_05T Fld(1, 12) //[12:12] 1491 #define SHU_AC_TIME_05T_TFAW_05T Fld(1, 13) //[13:13] 1492 #define SHU_AC_TIME_05T_TCKEPRD_05T Fld(1, 14) //[14:14] 1493 #define SHU_AC_TIME_05T_TR2PD_05T Fld(1, 15) //[15:15] 1494 #define SHU_AC_TIME_05T_TWTPD_M05T Fld(1, 16) //[16:16] 1495 #define SHU_AC_TIME_05T_TMRRI_05T Fld(1, 17) //[17:17] 1496 #define SHU_AC_TIME_05T_TMRWCKEL_05T Fld(1, 18) //[18:18] 1497 #define SHU_AC_TIME_05T_BGTRRD_05T Fld(1, 19) //[19:19] 1498 #define SHU_AC_TIME_05T_BGTCCD_05T Fld(1, 20) //[20:20] 1499 #define SHU_AC_TIME_05T_BGTWTR_M05T Fld(1, 21) //[21:21] 1500 #define SHU_AC_TIME_05T_TR2W_05T Fld(1, 22) //[22:22] 1501 #define SHU_AC_TIME_05T_TWTR_M05T Fld(1, 23) //[23:23] 1502 #define SHU_AC_TIME_05T_XRTR2W_05T Fld(1, 24) //[24:24] 1503 #define SHU_AC_TIME_05T_TMRD_05T Fld(1, 25) //[25:25] 1504 #define SHU_AC_TIME_05T_TMRW_05T Fld(1, 26) //[26:26] 1505 #define SHU_AC_TIME_05T_TMRR2MRW_05T Fld(1, 27) //[27:27] 1506 #define SHU_AC_TIME_05T_TW2MRW_05T Fld(1, 28) //[28:28] 1507 #define SHU_AC_TIME_05T_TR2MRW_05T Fld(1, 29) //[29:29] 1508 #define SHU_AC_TIME_05T_TPBR2ACT_05T Fld(1, 30) //[30:30] 1509 #define SHU_AC_TIME_05T_XRTW2R_M05T Fld(1, 31) //[31:31] 1510 1511 #define DRAMC_REG_SHU_AC_DERATING0 (DRAMC_AO_BASE_ADDRESS + 0x1668) 1512 #define SHU_AC_DERATING0_ACDERATEEN Fld(1, 0) //[0:0] 1513 #define SHU_AC_DERATING0_TRRD_DERATE Fld(3, 16) //[18:16] 1514 #define SHU_AC_DERATING0_TRCD_DERATE Fld(4, 24) //[27:24] 1515 1516 #define DRAMC_REG_SHU_AC_DERATING1 (DRAMC_AO_BASE_ADDRESS + 0x166C) 1517 #define SHU_AC_DERATING1_TRPAB_DERATE Fld(4, 0) //[3:0] 1518 #define SHU_AC_DERATING1_TRP_DERATE Fld(4, 8) //[11:8] 1519 #define SHU_AC_DERATING1_TRAS_DERATE Fld(6, 16) //[21:16] 1520 #define SHU_AC_DERATING1_TRC_DERATE Fld(5, 24) //[28:24] 1521 1522 #define DRAMC_REG_SHU_AC_DERATING_05T (DRAMC_AO_BASE_ADDRESS + 0x1670) 1523 #define SHU_AC_DERATING_05T_TRC_05T_DERATE Fld(1, 0) //[0:0] 1524 #define SHU_AC_DERATING_05T_TRCD_05T_DERATE Fld(1, 6) //[6:6] 1525 #define SHU_AC_DERATING_05T_TRP_05T_DERATE Fld(1, 7) //[7:7] 1526 #define SHU_AC_DERATING_05T_TRPAB_05T_DERATE Fld(1, 8) //[8:8] 1527 #define SHU_AC_DERATING_05T_TRAS_05T_DERATE Fld(1, 9) //[9:9] 1528 #define SHU_AC_DERATING_05T_TRRD_05T_DERATE Fld(1, 12) //[12:12] 1529 1530 #define DRAMC_REG_SHU_ACTIMING_CONF (DRAMC_AO_BASE_ADDRESS + 0x1674) 1531 #define SHU_ACTIMING_CONF_SCINTV Fld(6, 0) //[5:0] 1532 #define SHU_ACTIMING_CONF_TRFCPBIG Fld(1, 8) //[8:8] 1533 #define SHU_ACTIMING_CONF_REFBW_FR Fld(10, 16) //[25:16] 1534 #define SHU_ACTIMING_CONF_TREFBWIG Fld(1, 31) //[31:31] 1535 1536 #define DRAMC_REG_SHU_CKECTRL (DRAMC_AO_BASE_ADDRESS + 0x1678) 1537 #define SHU_CKECTRL_TPDE_05T Fld(1, 0) //[0:0] 1538 #define SHU_CKECTRL_TPDX_05T Fld(1, 1) //[1:1] 1539 #define SHU_CKECTRL_TPDE Fld(3, 12) //[14:12] 1540 #define SHU_CKECTRL_TPDX Fld(3, 16) //[18:16] 1541 #define SHU_CKECTRL_TCKEPRD Fld(3, 20) //[22:20] 1542 #define SHU_CKECTRL_TCKESRX Fld(2, 24) //[25:24] 1543 1544 #define DRAMC_REG_SHU_SELPH_DQS0 (DRAMC_AO_BASE_ADDRESS + 0x167C) 1545 #define SHU_SELPH_DQS0_TXDLY_DQS0 Fld(3, 0) //[2:0] 1546 #define SHU_SELPH_DQS0_TXDLY_DQS1 Fld(3, 4) //[6:4] 1547 #define SHU_SELPH_DQS0_TXDLY_DQS2 Fld(3, 8) //[10:8] 1548 #define SHU_SELPH_DQS0_TXDLY_DQS3 Fld(3, 12) //[14:12] 1549 #define SHU_SELPH_DQS0_TXDLY_OEN_DQS0 Fld(3, 16) //[18:16] 1550 #define SHU_SELPH_DQS0_TXDLY_OEN_DQS1 Fld(3, 20) //[22:20] 1551 #define SHU_SELPH_DQS0_TXDLY_OEN_DQS2 Fld(3, 24) //[26:24] 1552 #define SHU_SELPH_DQS0_TXDLY_OEN_DQS3 Fld(3, 28) //[30:28] 1553 1554 #define DRAMC_REG_SHU_SELPH_DQS1 (DRAMC_AO_BASE_ADDRESS + 0x1680) 1555 #define SHU_SELPH_DQS1_DLY_DQS0 Fld(4, 0) //[3:0] 1556 #define SHU_SELPH_DQS1_DLY_DQS1 Fld(4, 4) //[7:4] 1557 #define SHU_SELPH_DQS1_DLY_DQS2 Fld(4, 8) //[11:8] 1558 #define SHU_SELPH_DQS1_DLY_DQS3 Fld(4, 12) //[15:12] 1559 #define SHU_SELPH_DQS1_DLY_OEN_DQS0 Fld(4, 16) //[19:16] 1560 #define SHU_SELPH_DQS1_DLY_OEN_DQS1 Fld(4, 20) //[23:20] 1561 #define SHU_SELPH_DQS1_DLY_OEN_DQS2 Fld(4, 24) //[27:24] 1562 #define SHU_SELPH_DQS1_DLY_OEN_DQS3 Fld(4, 28) //[31:28] 1563 1564 #define DRAMC_REG_SHU_WODT (DRAMC_AO_BASE_ADDRESS + 0x1684) 1565 #define SHU_WODT_DISWODT Fld(3, 0) //[2:0] 1566 #define SHU_WODT_WODTFIX Fld(1, 3) //[3:3] 1567 #define SHU_WODT_WODTFIXOFF Fld(1, 4) //[4:4] 1568 #define SHU_WODT_DISWODTE Fld(1, 5) //[5:5] 1569 #define SHU_WODT_DISWODTE2 Fld(1, 6) //[6:6] 1570 #define SHU_WODT_WODTPDEN Fld(1, 7) //[7:7] 1571 #define SHU_WODT_WOEN Fld(1, 8) //[8:8] 1572 #define SHU_WODT_DQS2DQ_WARN_PITHRD Fld(6, 9) //[14:9] 1573 #define SHU_WODT_TWODT Fld(7, 16) //[22:16] 1574 1575 #define DRAMC_REG_SHU_TX_SET0 (DRAMC_AO_BASE_ADDRESS + 0x1688) 1576 #define SHU_TX_SET0_DQOE_CNT Fld(4, 0) //[3:0] 1577 #define SHU_TX_SET0_DQOE_OPT Fld(1, 4) //[4:4] 1578 #define SHU_TX_SET0_WR_NEW_OPT Fld(1, 5) //[5:5] 1579 #define SHU_TX_SET0_TXUPD_SEL Fld(2, 6) //[7:6] 1580 #define SHU_TX_SET0_TXUPD_W2R_SEL Fld(3, 8) //[10:8] 1581 #define SHU_TX_SET0_WECC_EN Fld(1, 11) //[11:11] 1582 #define SHU_TX_SET0_DBIWR Fld(1, 12) //[12:12] 1583 #define SHU_TX_SET0_WDATRGO Fld(1, 13) //[13:13] 1584 #define SHU_TX_SET0_TXUPD_W2R_OPT Fld(1, 14) //[14:14] 1585 #define SHU_TX_SET0_WPST1P5T Fld(1, 15) //[15:15] 1586 #define SHU_TX_SET0_TXOEN_AUTOSET_OFFSET Fld(4, 16) //[19:16] 1587 #define SHU_TX_SET0_TWCKPST Fld(2, 20) //[21:20] 1588 #define SHU_TX_SET0_OE_EXT2UI Fld(3, 22) //[24:22] 1589 #define SHU_TX_SET0_DQS2DQ_FILT_PITHRD Fld(6, 25) //[30:25] 1590 #define SHU_TX_SET0_TXOEN_AUTOSET_EN Fld(1, 31) //[31:31] 1591 1592 #define DRAMC_REG_SHU_RX_CG_SET0 (DRAMC_AO_BASE_ADDRESS + 0x168C) 1593 #define SHU_RX_CG_SET0_DLE_LAST_EXTEND3 Fld(1, 0) //[0:0] 1594 #define SHU_RX_CG_SET0_READ_START_EXTEND3 Fld(1, 1) //[1:1] 1595 #define SHU_RX_CG_SET0_DLE_LAST_EXTEND2 Fld(1, 2) //[2:2] 1596 #define SHU_RX_CG_SET0_READ_START_EXTEND2 Fld(1, 3) //[3:3] 1597 #define SHU_RX_CG_SET0_DLE_LAST_EXTEND1 Fld(1, 4) //[4:4] 1598 #define SHU_RX_CG_SET0_READ_START_EXTEND1 Fld(1, 5) //[5:5] 1599 1600 #define DRAMC_REG_SHU_DQSOSC_SET0 (DRAMC_AO_BASE_ADDRESS + 0x1690) 1601 #define SHU_DQSOSC_SET0_DQSOSCENDIS Fld(1, 0) //[0:0] 1602 #define SHU_DQSOSC_SET0_DQSOSC_PRDCNT Fld(10, 4) //[13:4] 1603 #define SHU_DQSOSC_SET0_DQSOSCENCNT Fld(16, 16) //[31:16] 1604 1605 #define DRAMC_REG_SHU_DQSOSCR (DRAMC_AO_BASE_ADDRESS + 0x1694) 1606 #define SHU_DQSOSCR_DQSOSCRCNT Fld(8, 0) //[7:0] 1607 #define SHU_DQSOSCR_DQSOSC_ADV_SEL Fld(2, 8) //[9:8] 1608 #define SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL Fld(2, 10) //[11:10] 1609 #define SHU_DQSOSCR_TX_SW_FORCE_UPD_SEL Fld(3, 12) //[14:12] 1610 #define SHU_DQSOSCR_DQSOSC_DELTA Fld(16, 16) //[31:16] 1611 1612 #define DRAMC_REG_SHU_TX_RANKCTL (DRAMC_AO_BASE_ADDRESS + 0x1698) 1613 #define SHU_TX_RANKCTL_TXRANKINCTL_TXDLY Fld(4, 0) //[3:0] 1614 #define SHU_TX_RANKCTL_TXRANKINCTL Fld(4, 4) //[7:4] 1615 #define SHU_TX_RANKCTL_TXRANKINCTL_ROOT Fld(4, 8) //[11:8] 1616 1617 #define DRAMC_REG_SHU_ZQ_SET0 (DRAMC_AO_BASE_ADDRESS + 0x169C) 1618 #define SHU_ZQ_SET0_ZQCSCNT Fld(16, 0) //[15:0] 1619 #define SHU_ZQ_SET0_TZQLAT Fld(5, 27) //[31:27] 1620 1621 #define DRAMC_REG_SHU_CONF0 (DRAMC_AO_BASE_ADDRESS + 0x16A0) 1622 #define SHU_CONF0_DMPGTIM Fld(7, 0) //[6:0] 1623 #define SHU_CONF0_ADVPREEN Fld(1, 7) //[7:7] 1624 #define SHU_CONF0_PBREFEN Fld(1, 8) //[8:8] 1625 #define SHU_CONF0_REFTHD Fld(4, 12) //[15:12] 1626 #define SHU_CONF0_REQQUE_DEPTH Fld(4, 16) //[19:16] 1627 #define SHU_CONF0_ADVREFEN Fld(1, 31) //[31:31] 1628 1629 #define DRAMC_REG_SHU_MISC (DRAMC_AO_BASE_ADDRESS + 0x16A4) 1630 #define SHU_MISC_REQQUE_MAXCNT Fld(4, 0) //[3:0] 1631 #define SHU_MISC_DCMDLYREF Fld(3, 16) //[18:16] 1632 #define SHU_MISC_DAREFEN Fld(1, 30) //[30:30] 1633 1634 #define DRAMC_REG_SHU_NEW_XRW2W_CTRL (DRAMC_AO_BASE_ADDRESS + 0x16A8) 1635 #define SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0 Fld(3, 16) //[18:16] 1636 #define SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1 Fld(3, 24) //[26:24] 1637 #define SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE Fld(1, 31) //[31:31] 1638 1639 #define DRAMC_REG_SHU_APHY_TX_PICG_CTRL (DRAMC_AO_BASE_ADDRESS + 0x16AC) 1640 #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT Fld(4, 0) //[3:0] 1641 #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 Fld(3, 4) //[6:4] 1642 #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 Fld(3, 8) //[10:8] 1643 #define SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT Fld(4, 12) //[15:12] 1644 #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT Fld(1, 31) //[31:31] 1645 1646 #define DRAMC_REG_SHU_FREQ_RATIO_SET0 (DRAMC_AO_BASE_ADDRESS + 0x16B0) 1647 #define SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3 Fld(8, 0) //[7:0] 1648 #define SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2 Fld(8, 8) //[15:8] 1649 #define SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1 Fld(8, 16) //[23:16] 1650 #define SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0 Fld(8, 24) //[31:24] 1651 1652 #define DRAMC_REG_SHU_FREQ_RATIO_SET1 (DRAMC_AO_BASE_ADDRESS + 0x16B4) 1653 #define SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO7 Fld(8, 0) //[7:0] 1654 #define SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6 Fld(8, 8) //[15:8] 1655 #define SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5 Fld(8, 16) //[23:16] 1656 #define SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4 Fld(8, 24) //[31:24] 1657 1658 #define DRAMC_REG_SHU_FREQ_RATIO_SET2 (DRAMC_AO_BASE_ADDRESS + 0x16B8) 1659 #define SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9 Fld(8, 16) //[23:16] 1660 #define SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO8 Fld(8, 24) //[31:24] 1661 1662 #define DRAMC_REG_SHUREG_RSV (DRAMC_AO_BASE_ADDRESS + 0x16BC) 1663 #define SHUREG_RSV_SHUREG_RSV Fld(32, 0) //[31:0] 1664 1665 #define DRAMC_REG_SHU_WCKCTRL (DRAMC_AO_BASE_ADDRESS + 0x16C0) 1666 #define SHU_WCKCTRL_WCKRDOFF Fld(6, 0) //[5:0] 1667 #define SHU_WCKCTRL_WCKRDOFF_05T Fld(1, 7) //[7:7] 1668 #define SHU_WCKCTRL_WCKWROFF Fld(6, 8) //[13:8] 1669 #define SHU_WCKCTRL_WCKWROFF_05T Fld(1, 15) //[15:15] 1670 #define SHU_WCKCTRL_WCKDUAL Fld(1, 16) //[16:16] 1671 1672 #define DRAMC_REG_SHU_WCKCTRL_1 (DRAMC_AO_BASE_ADDRESS + 0x16C4) 1673 #define SHU_WCKCTRL_1_WCKSYNC_PRE_MODE Fld(1, 0) //[0:0] 1674 1675 #define DRAMC_REG_SHU_RX_SET0 (DRAMC_AO_BASE_ADDRESS + 0x16D0) 1676 #define SHU_RX_SET0_RECC_EN Fld(1, 31) //[31:31] 1677 1678 #define DRAMC_REG_SHU_REF0 (DRAMC_AO_BASE_ADDRESS + 0x16D4) 1679 #define SHU_REF0_MPENDREF_CNT Fld(3, 0) //[2:0] 1680 1681 #define DRAMC_REG_SHU_LP5_CMD (DRAMC_AO_BASE_ADDRESS + 0x16E0) 1682 #define SHU_LP5_CMD_LP5_CMD1TO2EN Fld(1, 0) //[0:0] 1683 #define SHU_LP5_CMD_TCSH Fld(4, 4) //[7:4] 1684 1685 #define DRAMC_REG_SHU_LP5_SACT (DRAMC_AO_BASE_ADDRESS + 0x16E4) 1686 #define SHU_LP5_SACT_LP5_SEPARATE_ACT Fld(1, 0) //[0:0] 1687 1688 #define DRAMC_REG_SHU_ACTIM7 (DRAMC_AO_BASE_ADDRESS + 0x16E8) 1689 #define SHU_ACTIM7_TCSH_CSCAL Fld(4, 0) //[3:0] 1690 #define SHU_ACTIM7_TCACSH Fld(4, 4) //[7:4] 1691 1692 #endif // __DRAMC_AO_REGS_H__ 1693