| /aosp_15_r20/external/llvm/unittests/Analysis/ |
| H A D | LazyCallGraphTest.cpp | 494 LazyCallGraph::RefSCC &DRC = *CG.lookupRefSCC(D); in TEST() local
619 LazyCallGraph::RefSCC &DRC = *CG.lookupRefSCC(D1); in TEST() local
683 LazyCallGraph::RefSCC &DRC = *I; in TEST() local
|
| /aosp_15_r20/external/coreboot/src/northbridge/intel/e7505/ |
| H A D | e7505.h | 33 #define DRC 0x7C /* DRAM Controller Mode register, 32 bit */ macro
|
| /aosp_15_r20/external/llvm/lib/CodeGen/ |
| H A D | MachineVerifier.cpp | 978 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
1028 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
|
| H A D | MachineSink.cpp | 171 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | MachineVerifier.cpp | 1687 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
1787 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
|
| H A D | MachineSink.cpp | 232 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/ |
| H A D | MachineVerifier.cpp | 2112 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
2226 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
|
| H A D | MachineSink.cpp | 283 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonEarlyIfConv.cpp | 778 MachineBasicBlock::iterator At, const TargetRegisterClass *DRC, in buildMux()
|
| H A D | HexagonBitSimplify.cpp | 961 auto *DRC = getFinalVRegClass(RD, MRI); in isTransparentCopy() local
1511 const BitTracker::RegisterCell &DRC = BT.lookup(DR); in processBlock() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonEarlyIfConv.cpp | 778 MachineBasicBlock::iterator At, const TargetRegisterClass *DRC, in buildMux()
|
| H A D | HexagonBitSimplify.cpp | 932 auto *DRC = getFinalVRegClass(RD, MRI); in isTransparentCopy() local
1474 const BitTracker::RegisterCell &DRC = BT.lookup(DR); in processBlock() local
|
| /aosp_15_r20/external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 886 auto *DRC = getFinalVRegClass(RD, MRI); in isTransparentCopy() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 3933 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass); in isLegalRegOperand() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 5063 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass); in isLegalRegOperand() local
|