1package xiangshan.backend.ctrlblock 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.XSBundle 7import xiangshan.mem.LoadReplayCauses 8 9class DebugMdpInfo(implicit p: Parameters) extends XSBundle{ 10 val ssid = UInt(SSIDWidth.W) 11 val waitAllStore = Bool() 12} 13 14class DebugLsInfo(implicit p: Parameters) extends XSBundle{ 15 val s1_isTlbFirstMiss = Bool() // in s1 16 val s1_isLoadToLoadForward = Bool() 17 val s2_isBankConflict = Bool() 18 val s2_isDcacheFirstMiss = Bool() // in s2 (predicted result is in s1 when using WPU, real result is in s2) 19 val s2_isForwardFail = Bool() // in s2 20 val s3_isReplayFast = Bool() 21 val s3_isReplaySlow = Bool() 22 val s3_isReplayRS = Bool() 23 val s3_isReplay = Bool() 24 val replayCause = Vec(LoadReplayCauses.allCauses, Bool()) 25 val replayCnt = UInt(XLEN.W) 26 27 def s1SignalEnable(ena: DebugLsInfo) = { 28 when(ena.s1_isTlbFirstMiss) { s1_isTlbFirstMiss := true.B } 29 when(ena.s1_isLoadToLoadForward) { s1_isLoadToLoadForward := true.B } 30 } 31 32 def s2SignalEnable(ena: DebugLsInfo) = { 33 when(ena.s2_isBankConflict) { s2_isBankConflict := true.B } 34 when(ena.s2_isDcacheFirstMiss) { s2_isDcacheFirstMiss := true.B } 35 when(ena.s2_isForwardFail) { s2_isForwardFail := true.B } 36 } 37 def s3SignalEnable(ena: DebugLsInfo) = { 38 when(ena.s3_isReplayFast) { s3_isReplayFast := true.B } 39 when(ena.s3_isReplaySlow) { s3_isReplaySlow := true.B } 40 when(ena.s3_isReplayRS) { s3_isReplayRS := true.B } 41 when(ena.s3_isReplay) { 42 s3_isReplay := true.B 43 replayCnt := replayCnt + 1.U 44 when((ena.replayCause.asUInt ^ replayCause.asUInt).orR) { 45 replayCause := ena.replayCause.zipWithIndex.map{ case (x, i) => x | replayCause(i) } 46 } 47 } 48 } 49} 50 51object DebugLsInfo { 52 def init(implicit p: Parameters): DebugLsInfo = { 53 val lsInfo = Wire(new DebugLsInfo) 54 lsInfo.s1_isTlbFirstMiss := false.B 55 lsInfo.s1_isLoadToLoadForward := false.B 56 lsInfo.s2_isBankConflict := false.B 57 lsInfo.s2_isDcacheFirstMiss := false.B 58 lsInfo.s2_isForwardFail := false.B 59 lsInfo.s3_isReplayFast := false.B 60 lsInfo.s3_isReplaySlow := false.B 61 lsInfo.s3_isReplayRS := false.B 62 lsInfo.s3_isReplay := false.B 63 lsInfo.replayCnt := 0.U 64 lsInfo.replayCause := Seq.fill(LoadReplayCauses.allCauses)(false.B) 65 lsInfo 66 } 67} 68 69class DebugLsInfoBundle(implicit p: Parameters) extends DebugLsInfo { 70 // unified processing at the end stage of load/store ==> s2 ==> bug that will write error robIdx data 71 val s1_robIdx = UInt(log2Ceil(RobSize).W) 72 val s2_robIdx = UInt(log2Ceil(RobSize).W) 73 val s3_robIdx = UInt(log2Ceil(RobSize).W) 74} 75 76class DebugLSIO(implicit p: Parameters) extends XSBundle { 77 val debugLsInfo = Vec(backendParams.LduCnt + backendParams.HyuCnt + backendParams.StaCnt + backendParams.HyuCnt, Output(new DebugLsInfoBundle)) 78} 79class LsTopdownInfo(implicit p: Parameters) extends XSBundle { 80 val s1 = new Bundle { 81 val robIdx = UInt(log2Ceil(RobSize).W) 82 val vaddr_valid = Bool() 83 val vaddr_bits = UInt(VAddrBits.W) 84 } 85 val s2 = new Bundle { 86 val robIdx = UInt(log2Ceil(RobSize).W) 87 val paddr_valid = Bool() 88 val paddr_bits = UInt(PAddrBits.W) 89 val cache_miss_en = Bool() 90 val first_real_miss = Bool() 91 } 92 93 def s1SignalEnable(ena: LsTopdownInfo) = { 94 when(ena.s1.vaddr_valid) { 95 s1.vaddr_valid := true.B 96 s1.vaddr_bits := ena.s1.vaddr_bits 97 } 98 } 99 100 def s2SignalEnable(ena: LsTopdownInfo) = { 101 when(ena.s2.paddr_valid) { 102 s2.paddr_valid := true.B 103 s2.paddr_bits := ena.s2.paddr_bits 104 } 105 when(ena.s2.cache_miss_en) { 106 s2.first_real_miss := ena.s2.first_real_miss 107 } 108 } 109} 110 111object LsTopdownInfo { 112 def init(implicit p: Parameters): LsTopdownInfo = 0.U.asTypeOf(new LsTopdownInfo) 113}