1{
2  "License": [
3    "Copyright (C) 2023 The Android Open Source Project",
4    "",
5    "Licensed under the Apache License, Version 2.0 (the “License”);",
6    "you may not use this file except in compliance with the License.",
7    "You may obtain a copy of the License at",
8    "",
9    "     http://www.apache.org/licenses/LICENSE-2.0",
10    "",
11    "Unless required by applicable law or agreed to in writing, software",
12    "distributed under the License is distributed on an “AS IS” BASIS,",
13    "WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.",
14    "See the License for the specific language governing permissions and",
15    "limitations under the License."
16  ],
17  "arch": "common_x86",
18  "insns": [
19    {
20      "encodings": {
21        "Adcb": { "opcodes": [ "80", "2" ] },
22        "Rclb": { "opcodes": [ "C0", "2" ] },
23        "Rcrb": { "opcodes": [ "C0", "3" ] },
24        "Sbbb": { "opcodes": [ "80", "3" ] }
25      },
26      "args": [
27        { "class": "GeneralReg8/Mem8", "usage": "use_def" },
28        { "class": "Imm8" },
29        { "class": "FLAGS", "usage": "use_def" }
30      ]
31    },
32    {
33      "encodings": {
34        "Adcb": { "opcode": "12" },
35        "Sbbb": { "opcode": "1A" }
36      },
37      "args": [
38        { "class": "GeneralReg8", "usage": "use_def" },
39        { "class": "Mem8", "usage": "use" },
40        { "class": "FLAGS", "usage": "use_def" }
41      ]
42    },
43    {
44      "encodings": {
45        "Adcb": { "opcode": "10", "type": "reg_to_rm" },
46        "Sbbb": { "opcode": "18", "type": "reg_to_rm" }
47      },
48      "args": [
49        { "class": "GeneralReg8/Mem8", "usage": "use_def" },
50        { "class": "GeneralReg8", "usage": "use" },
51        { "class": "FLAGS", "usage": "use_def" }
52      ]
53    },
54    {
55      "encodings": {
56        "AdcbAccumulator": { "opcode": "14" },
57        "SbbbAccumulator": { "opcode": "1C" }
58      },
59      "args": [
60        { "class": "AL", "usage": "use_def" },
61        { "class": "Imm8" },
62        { "class": "FLAGS", "usage": "use_def" }
63      ]
64    },
65    {
66      "encodings": {
67        "Adcl": { "opcode": "13" },
68        "Sbbl": { "opcode": "1B" }
69      },
70      "args": [
71        { "class": "GeneralReg32", "usage": "use_def" },
72        { "class": "Mem32", "usage": "use" },
73        { "class": "FLAGS", "usage": "use_def" }
74      ]
75    },
76    {
77      "encodings": {
78        "Adcl": { "opcode": "11", "type": "reg_to_rm" },
79        "Sbbl": { "opcode": "19", "type": "reg_to_rm" }
80      },
81      "args": [
82        { "class": "GeneralReg32/Mem32", "usage": "use_def" },
83        { "class": "GeneralReg32", "usage": "use" },
84        { "class": "FLAGS", "usage": "use_def" }
85      ]
86    },
87    {
88      "encodings": {
89        "Adcl": { "opcodes": [ "81", "2" ] },
90        "Sbbl": { "opcodes": [ "81", "3" ] }
91      },
92      "args": [
93        { "class": "GeneralReg32/Mem32", "usage": "use_def" },
94        { "class": "Imm32" },
95        { "class": "FLAGS", "usage": "use_def" }
96      ]
97    },
98    {
99      "encodings": {
100        "AdclAccumulator": { "opcode": "15" },
101        "SbblAccumulator": { "opcode": "1D" }
102      },
103      "args": [
104        { "class": "EAX", "usage": "use_def" },
105        { "class": "Imm32" },
106        { "class": "FLAGS", "usage": "use_def" }
107      ]
108    },
109    {
110      "encodings": {
111        "AdclImm8": { "opcodes": [ "83", "2" ] },
112        "Rcll": { "opcodes": [ "C1", "2" ] },
113        "Rcrl": { "opcodes": [ "C1", "3" ] },
114        "SbblImm8": { "opcodes": [ "83", "3" ] }
115      },
116      "args": [
117        { "class": "GeneralReg32/Mem32", "usage": "use_def" },
118        { "class": "Imm8" },
119        { "class": "FLAGS", "usage": "use_def" }
120      ]
121    },
122    {
123      "encodings": {
124        "Adcw": { "opcodes": [ "66", "13" ] },
125        "Sbbw": { "opcodes": [ "66", "1B" ] }
126      },
127      "args": [
128        { "class": "GeneralReg16", "usage": "use_def" },
129        { "class": "Mem16", "usage": "use" },
130        { "class": "FLAGS", "usage": "use_def" }
131      ]
132    },
133    {
134      "encodings": {
135        "Adcw": { "opcodes": [ "66", "11" ], "type": "reg_to_rm" },
136        "Sbbw": { "opcodes": [ "66", "19" ], "type": "reg_to_rm" }
137      },
138      "args": [
139        { "class": "GeneralReg16/Mem16", "usage": "use_def" },
140        { "class": "GeneralReg16", "usage": "use" },
141        { "class": "FLAGS", "usage": "use_def" }
142      ]
143    },
144    {
145      "encodings": {
146        "Adcw": { "opcodes": [ "66", "81", "2" ] },
147        "Sbbw": { "opcodes": [ "66", "81", "3" ] }
148      },
149      "args": [
150        { "class": "GeneralReg16/Mem16", "usage": "use_def" },
151        { "class": "Imm16" },
152        { "class": "FLAGS", "usage": "use_def" }
153      ]
154    },
155    {
156      "encodings": {
157        "AdcwAccumulator": { "opcodes": [ "66", "15" ] },
158        "SbbwAccumulator": { "opcodes": [ "66", "1D" ] }
159      },
160      "args": [
161        { "class": "AX", "usage": "use_def" },
162        { "class": "Imm16" },
163        { "class": "FLAGS", "usage": "use_def" }
164      ]
165    },
166    {
167      "encodings": {
168        "AdcwImm8": { "opcodes": [ "66", "83", "2" ] },
169        "Rclw": { "opcodes": [ "66", "C1", "2" ] },
170        "Rcrw": { "opcodes": [ "66", "C1", "3" ] },
171        "SbbwImm8": { "opcodes": [ "66", "83", "3" ] }
172      },
173      "args": [
174        { "class": "GeneralReg16/Mem16", "usage": "use_def" },
175        { "class": "Imm8" },
176        { "class": "FLAGS", "usage": "use_def" }
177      ]
178    },
179    {
180      "encodings": {
181        "Addb": { "opcodes": [ "80", "0" ] },
182        "Andb": { "opcodes": [ "80", "4" ] },
183        "Orb": { "opcodes": [ "80", "1" ] },
184        "Rolb": { "opcodes": [ "C0", "0" ] },
185        "Rorb": { "opcodes": [ "C0", "1" ] },
186        "Sarb": { "opcodes": [ "C0", "7" ] },
187        "Shlb": { "opcodes": [ "C0", "4" ] },
188        "Shrb": { "opcodes": [ "C0", "5" ] },
189        "Subb": { "opcodes": [ "80", "5" ] },
190        "Xorb": { "opcodes": [ "80", "6" ] }
191      },
192      "args": [
193        { "class": "GeneralReg8/Mem8", "usage": "use_def" },
194        { "class": "Imm8" },
195        { "class": "FLAGS", "usage": "def" }
196      ]
197    },
198    {
199      "encodings": {
200        "Addb": { "opcode": "02" },
201        "Andb": { "opcode": "22" },
202        "Orb": { "opcode": "0A" },
203        "Subb": { "opcode": "2A" },
204        "Xorb": { "opcode": "32" }
205      },
206      "args": [
207        { "class": "GeneralReg8", "usage": "use_def" },
208        { "class": "Mem8", "usage": "use" },
209        { "class": "FLAGS", "usage": "def" }
210      ]
211    },
212    {
213      "encodings": {
214        "Addb": { "opcode": "00", "type": "reg_to_rm" },
215        "Andb": { "opcode": "20", "type": "reg_to_rm" },
216        "Orb": { "opcode": "08", "type": "reg_to_rm" },
217        "Subb": { "opcode": "28", "type": "reg_to_rm" },
218        "Xorb": { "opcode": "30", "type": "reg_to_rm" }
219      },
220      "args": [
221        { "class": "GeneralReg8/Mem8", "usage": "use_def" },
222        { "class": "GeneralReg8", "usage": "use" },
223        { "class": "FLAGS", "usage": "def" }
224      ]
225    },
226    {
227      "encodings": {
228        "AddbAccumulator": { "opcode": "04" },
229        "AndbAccumulator": { "opcode": "24" },
230        "OrbAccumulator": { "opcode": "0C" },
231        "SubbAccumulator": { "opcode": "2C" },
232        "XorbAccumulator": { "opcode": "34" }
233      },
234      "args": [
235        { "class": "AL", "usage": "use_def" },
236        { "class": "Imm8" },
237        { "class": "FLAGS", "usage": "def" }
238      ]
239    },
240    {
241      "encodings": {
242        "Addl": { "opcode": "01", "type": "reg_to_rm" },
243        "Andl": { "opcode": "21", "type": "reg_to_rm" },
244        "Btcl": { "opcodes": [ "0F", "BB" ], "type": "reg_to_rm" },
245        "Btrl": { "opcodes": [ "0F", "B3" ], "type": "reg_to_rm" },
246        "Btsl": { "opcodes": [ "0F", "AB" ], "type": "reg_to_rm" },
247        "Orl": { "opcode": "09", "type": "reg_to_rm" },
248        "Subl": { "opcode": "29", "type": "reg_to_rm" },
249        "Xorl": { "opcode": "31", "type": "reg_to_rm" }
250      },
251      "args": [
252        { "class": "GeneralReg32/Mem32", "usage": "use_def" },
253        { "class": "GeneralReg32", "usage": "use" },
254        { "class": "FLAGS", "usage": "def" }
255      ]
256    },
257    {
258      "encodings": {
259        "Addl": { "opcode": "03" },
260        "Andl": { "opcode": "23" },
261        "Orl": { "opcode": "0B" },
262        "Subl": { "opcode": "2B" },
263        "Xorl": { "opcode": "33" }
264      },
265      "args": [
266        { "class": "GeneralReg32", "usage": "use_def" },
267        { "class": "Mem32", "usage": "use" },
268        { "class": "FLAGS", "usage": "def" }
269      ]
270    },
271    {
272      "encodings": {
273        "Addl": { "opcodes": [ "81", "0" ] },
274        "Andl": { "opcodes": [ "81", "4" ] },
275        "Orl": { "opcodes": [ "81", "1" ] },
276        "Subl": { "opcodes": [ "81", "5" ] },
277        "Xorl": { "opcodes": [ "81", "6" ] }
278      },
279      "args": [
280        { "class": "GeneralReg32/Mem32", "usage": "use_def" },
281        { "class": "Imm32" },
282        { "class": "FLAGS", "usage": "def" }
283      ]
284    },
285    {
286      "encodings": {
287        "AddlAccumulator": { "opcode": "05" },
288        "AndlAccumulator": { "opcode": "25" },
289        "OrlAccumulator": { "opcode": "0D" },
290        "SublAccumulator": { "opcode": "2D" },
291        "XorlAccumulator": { "opcode": "35" }
292      },
293      "args": [
294        { "class": "EAX", "usage": "use_def" },
295        { "class": "Imm32" },
296        { "class": "FLAGS", "usage": "def" }
297      ]
298    },
299    {
300      "encodings": {
301        "AddlImm8": { "opcodes": [ "83", "0" ] },
302        "AndlImm8": { "opcodes": [ "83", "4" ] },
303        "Btcl": { "opcodes": [ "0F", "BA", "7" ] },
304        "Btl": { "opcodes": [ "0F", "BA", "4" ] },
305        "Btrl": { "opcodes": [ "0F", "BA", "6" ] },
306        "Btsl": { "opcodes": [ "0F", "BA", "5" ] },
307        "OrlImm8": { "opcodes": [ "83", "1" ] },
308        "Roll": { "opcodes": [ "C1", "0" ] },
309        "Rorl": { "opcodes": [ "C1", "1" ] },
310        "Sarl": { "opcodes": [ "C1", "7" ] },
311        "Shll": { "opcodes": [ "C1", "4" ] },
312        "Shrl": { "opcodes": [ "C1", "5" ] },
313        "SublImm8": { "opcodes": [ "83", "5" ] },
314        "XorlImm8": { "opcodes": [ "83", "6" ] }
315      },
316      "args": [
317        { "class": "GeneralReg32/Mem32", "usage": "use_def" },
318        { "class": "Imm8" },
319        { "class": "FLAGS", "usage": "def" }
320      ]
321    },
322    {
323      "encodings": {
324        "Addpd": { "opcodes": [ "66", "0F", "58" ] },
325        "Addps": { "opcodes": [ "0F", "58" ] },
326        "Andpd": { "opcodes": [ "66", "0F", "54" ] },
327        "Andps": { "opcodes": [ "0F", "54" ] },
328        "Cmpeqpd": { "opcodes": [ "66", "0F", "C2", "00" ] },
329        "Cmpeqps": { "opcodes": [ "0F", "C2", "00" ] },
330        "Cmplepd": { "opcodes": [ "66", "0F", "C2", "02" ] },
331        "Cmpleps": { "opcodes": [ "0F", "C2", "02" ] },
332        "Cmpltpd": { "opcodes": [ "66", "0F", "C2", "01" ] },
333        "Cmpltps": { "opcodes": [ "0F", "C2", "01" ] },
334        "Cmpneqpd": { "opcodes": [ "66", "0F", "C2", "04" ] },
335        "Cmpneqps": { "opcodes": [ "0F", "C2", "04" ] },
336        "Cmpnlepd": { "opcodes": [ "66", "0F", "C2", "06" ] },
337        "Cmpnleps": { "opcodes": [ "0F", "C2", "06" ] },
338        "Cmpnltpd": { "opcodes": [ "66", "0F", "C2", "05" ] },
339        "Cmpnltps": { "opcodes": [ "0F", "C2", "05" ] },
340        "Cmpordpd": { "opcodes": [ "66", "0F", "C2", "07" ] },
341        "Cmpordps": { "opcodes": [ "0F", "C2", "07" ] },
342        "Cmpunordpd": { "opcodes": [ "66", "0F", "C2", "03" ] },
343        "Cmpunordps": { "opcodes": [ "0F", "C2", "03" ] },
344        "Divpd": { "opcodes": [ "66", "0F", "5E" ] },
345        "Divps": { "opcodes": [ "0F", "5E" ] },
346        "Haddpd": { "feature": "SSE3", "opcodes": [ "66", "0F", "7C" ] },
347        "Haddps": { "feature": "SSE3", "opcodes": [ "F2", "0F", "7C" ] },
348        "Maxpd": { "opcodes": [ "66", "0F", "5F" ] },
349        "Maxps": { "opcodes": [ "0F", "5F" ] },
350        "Minpd": { "opcodes": [ "66", "0F", "5D" ] },
351        "Minps": { "opcodes": [ "0F", "5D" ] },
352        "Mulpd": { "opcodes": [ "66", "0F", "59" ] },
353        "Mulps": { "opcodes": [ "0F", "59" ] },
354        "Orpd": { "opcodes": [ "66", "0F", "56" ] },
355        "Orps": { "opcodes": [ "0F", "56" ] },
356        "Packssdw": { "opcodes": [ "66", "0F", "6B" ] },
357        "Packsswb": { "opcodes": [ "66", "0F", "63" ] },
358        "Packusdw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "2B" ] },
359        "Packuswb": { "opcodes": [ "66", "0F", "67" ] },
360        "Paddb": { "opcodes": [ "66", "0F", "FC" ] },
361        "Paddd": { "opcodes": [ "66", "0F", "FE" ] },
362        "Paddq": { "opcodes": [ "66", "0F", "D4" ] },
363        "Paddsb": { "opcodes": [ "66", "0F", "EC" ] },
364        "Paddsw": { "opcodes": [ "66", "0F", "ED" ] },
365        "Paddusb": { "opcodes": [ "66", "0F", "DC" ] },
366        "Paddusw": { "opcodes": [ "66", "0F", "DD" ] },
367        "Paddw": { "opcodes": [ "66", "0F", "FD" ] },
368        "Pand": { "opcodes": [ "66", "0F", "DB" ] },
369        "Pandn": { "opcodes": [ "66", "0F", "DF" ] },
370        "Pavgb": { "opcodes": [ "66", "0F", "E0" ] },
371        "Pavgw": { "opcodes": [ "66", "0F", "E3" ] },
372        "Pcmpeqb": { "opcodes": [ "66", "0F", "74" ] },
373        "Pcmpeqd": { "opcodes": [ "66", "0F", "76" ] },
374        "Pcmpeqq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "29" ] },
375        "Pcmpeqw": { "opcodes": [ "66", "0F", "75" ] },
376        "Pcmpgtb": { "opcodes": [ "66", "0F", "64" ] },
377        "Pcmpgtd": { "opcodes": [ "66", "0F", "66" ] },
378        "Pcmpgtq": { "feature": "SSE4_2", "opcodes": [ "66", "0F", "38", "37" ] },
379        "Pcmpgtw": { "opcodes": [ "66", "0F", "65" ] },
380        "Phaddd": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "02" ] },
381        "Phaddw": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "01" ] },
382        "Pmaxsb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3C" ] },
383        "Pmaxsd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3D" ] },
384        "Pmaxsw": { "opcodes": [ "66", "0F", "EE" ] },
385        "Pmaxub": { "opcodes": [ "66", "0F", "DE" ] },
386        "Pmaxud": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3F" ] },
387        "Pmaxuw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3E" ] },
388        "Pminsb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "38" ] },
389        "Pminsd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "39" ] },
390        "Pminsw": { "opcodes": [ "66", "0F", "EA" ] },
391        "Pminub": { "opcodes": [ "66", "0F", "DA" ] },
392        "Pminud": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3B" ] },
393        "Pminuw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "3A" ] },
394        "Pmulhrsw": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "0B" ] },
395        "Pmulhw": { "opcodes": [ "66", "0F", "E5" ] },
396        "Pmulld": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "40" ] },
397        "Pmullw": { "opcodes": [ "66", "0F", "D5" ] },
398        "Pmuludq": { "opcodes": [ "66", "0F", "F4" ] },
399        "Por": { "opcodes": [ "66", "0F", "EB" ] },
400        "Psadbw": { "opcodes": [ "66", "0F", "F6" ] },
401        "Pshufb": { "feature": "SSSE3", "opcodes": [ "66", "0F", "38", "00" ] },
402        "Pslld": { "opcodes": [ "66", "0F", "F2" ] },
403        "Psllq": { "opcodes": [ "66", "0F", "F3" ] },
404        "Psllw": { "opcodes": [ "66", "0F", "F1" ] },
405        "Psrad": { "opcodes": [ "66", "0F", "E2" ] },
406        "Psraw": { "opcodes": [ "66", "0F", "E1" ] },
407        "Psrld": { "opcodes": [ "66", "0F", "D2" ] },
408        "Psrlq": { "opcodes": [ "66", "0F", "D3" ] },
409        "Psrlw": { "opcodes": [ "66", "0F", "D1" ] },
410        "Psubb": { "opcodes": [ "66", "0F", "F8" ] },
411        "Psubd": { "opcodes": [ "66", "0F", "FA" ] },
412        "Psubq": { "opcodes": [ "66", "0F", "FB" ] },
413        "Psubsb": { "opcodes": [ "66", "0F", "E8" ] },
414        "Psubsw": { "opcodes": [ "66", "0F", "E9" ] },
415        "Psubusb": { "opcodes": [ "66", "0F", "D8" ] },
416        "Psubusw": { "opcodes": [ "66", "0F", "D9" ] },
417        "Psubw": { "opcodes": [ "66", "0F", "F9" ] },
418        "Punpckhbw": { "opcodes": [ "66", "0F", "68" ] },
419        "Punpckhdq": { "opcodes": [ "66", "0F", "6A" ] },
420        "Punpckhqdq": { "opcodes": [ "66", "0F", "6D" ] },
421        "Punpckhwd": { "opcodes": [ "66", "0F", "69" ] },
422        "Punpcklbw": { "opcodes": [ "66", "0F", "60" ] },
423        "Punpckldq": { "opcodes": [ "66", "0F", "62" ] },
424        "Punpcklqdq": { "opcodes": [ "66", "0F", "6C" ] },
425        "Punpcklwd": { "opcodes": [ "66", "0F", "61" ] },
426        "Pxor": { "opcodes": [ "66", "0F", "EF" ] },
427        "Rsqrtps": { "opcodes": [ "0F", "52" ] },
428        "Subpd": { "opcodes": [ "66", "0F", "5C" ] },
429        "Subps": { "opcodes": [ "0F", "5C" ] },
430        "Vrsqrtps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "52" ] },
431        "Xorpd": { "opcodes": [ "66", "0F", "57" ] },
432        "Xorps": { "opcodes": [ "0F", "57" ] }
433      },
434      "args": [
435        { "class": "VecReg128", "usage": "use_def" },
436        { "class": "VecReg128/VecMem128", "usage": "use" }
437      ]
438    },
439    {
440      "encodings": {
441        "Addsd": { "opcodes": [ "F2", "0F", "58" ] },
442        "Cmpeqsd": { "opcodes": [ "F2", "0F", "C2", "00" ] },
443        "Cmplesd": { "opcodes": [ "F2", "0F", "C2", "02" ] },
444        "Cmpltsd": { "opcodes": [ "F2", "0F", "C2", "01" ] },
445        "Cmpneqsd": { "opcodes": [ "F2", "0F", "C2", "04" ] },
446        "Cmpnlesd": { "opcodes": [ "F2", "0F", "C2", "06" ] },
447        "Cmpnltsd": { "opcodes": [ "F2", "0F", "C2", "05" ] },
448        "Cmpordsd": { "opcodes": [ "F2", "0F", "C2", "07" ] },
449        "Cmpunordsd": { "opcodes": [ "F2", "0F", "C2", "03" ] },
450        "Divsd": { "opcodes": [ "F2", "0F", "5E" ] },
451        "Mulsd": { "opcodes": [ "F2", "0F", "59" ] },
452        "Subsd": { "opcodes": [ "F2", "0F", "5C" ] }
453      },
454      "args": [
455        { "class": "FpReg64", "usage": "use_def" },
456        { "class": "FpReg64/VecMem64", "usage": "use" }
457      ]
458    },
459    {
460      "encodings": {
461        "Addss": { "opcodes": [ "F3", "0F", "58" ] },
462        "Cmpeqss": { "opcodes": [ "F3", "0F", "C2", "00" ] },
463        "Cmpless": { "opcodes": [ "F3", "0F", "C2", "02" ] },
464        "Cmpltss": { "opcodes": [ "F3", "0F", "C2", "01" ] },
465        "Cmpneqss": { "opcodes": [ "F3", "0F", "C2", "04" ] },
466        "Cmpnless": { "opcodes": [ "F3", "0F", "C2", "06" ] },
467        "Cmpnltss": { "opcodes": [ "F3", "0F", "C2", "05" ] },
468        "Cmpordss": { "opcodes": [ "F3", "0F", "C2", "07" ] },
469        "Cmpunordss": { "opcodes": [ "F3", "0F", "C2", "03" ] },
470        "Divss": { "opcodes": [ "F3", "0F", "5E" ] },
471        "Mulss": { "opcodes": [ "F3", "0F", "59" ] },
472        "Subss": { "opcodes": [ "F3", "0F", "5C" ] }
473      },
474      "args": [
475        { "class": "FpReg32", "usage": "use_def" },
476        { "class": "FpReg32/VecMem32", "usage": "use" }
477      ]
478    },
479    {
480      "encodings": {
481        "Addw": { "opcodes": [ "66", "01" ], "type": "reg_to_rm" },
482        "Andw": { "opcodes": [ "66", "21" ], "type": "reg_to_rm" },
483        "Btcw": { "opcodes": [ "66", "0F", "BB" ], "type": "reg_to_rm" },
484        "Btrw": { "opcodes": [ "66", "0F", "B3" ], "type": "reg_to_rm" },
485        "Btsw": { "opcodes": [ "66", "0F", "AB" ], "type": "reg_to_rm" },
486        "Orw": { "opcodes": [ "66", "09" ], "type": "reg_to_rm" },
487        "Subw": { "opcodes": [ "66", "29" ], "type": "reg_to_rm" },
488        "Xorw": { "opcodes": [ "66", "31" ], "type": "reg_to_rm" }
489      },
490      "args": [
491        { "class": "GeneralReg16/Mem16", "usage": "use_def" },
492        { "class": "GeneralReg16", "usage": "use" },
493        { "class": "FLAGS", "usage": "def" }
494      ]
495    },
496    {
497      "encodings": {
498        "Addw": { "opcodes": [ "66", "03" ] },
499        "Andw": { "opcodes": [ "66", "23" ] },
500        "Orw": { "opcodes": [ "66", "0B" ] },
501        "Subw": { "opcodes": [ "66", "2B" ] },
502        "Xorw": { "opcodes": [ "66", "33" ] }
503      },
504      "args": [
505        { "class": "GeneralReg16", "usage": "use_def" },
506        { "class": "Mem16", "usage": "use" },
507        { "class": "FLAGS", "usage": "def" }
508      ]
509    },
510    {
511      "encodings": {
512        "Addw": { "opcodes": [ "66", "81", "0" ] },
513        "Andw": { "opcodes": [ "66", "81", "4" ] },
514        "Orw": { "opcodes": [ "66", "81", "1" ] },
515        "Subw": { "opcodes": [ "66", "81", "5" ] },
516        "Xorw": { "opcodes": [ "66", "81", "6" ] }
517      },
518      "args": [
519        { "class": "GeneralReg16/Mem16", "usage": "use_def" },
520        { "class": "Imm16" },
521        { "class": "FLAGS", "usage": "def" }
522      ]
523    },
524    {
525      "encodings": {
526        "AddwAccumulator": { "opcodes": [ "66", "05" ] },
527        "AndwAccumulator": { "opcodes": [ "66", "25" ] },
528        "OrwAccumulator": { "opcodes": [ "66", "0D" ] },
529        "SubwAccumulator": { "opcodes": [ "66", "2D" ] },
530        "XorwAccumulator": { "opcodes": [ "66", "35" ] }
531      },
532      "args": [
533        { "class": "AX", "usage": "use_def" },
534        { "class": "Imm16" },
535        { "class": "FLAGS", "usage": "def" }
536      ]
537    },
538    {
539      "encodings": {
540        "AddwImm8": { "opcodes": [ "66", "83", "0" ] },
541        "AndwImm8": { "opcodes": [ "66", "83", "4" ] },
542        "OrwImm8": { "opcodes": [ "66", "83", "1" ] },
543        "Rolw": { "opcodes": [ "66", "C1", "0" ] },
544        "Rorw": { "opcodes": [ "66", "C1", "1" ] },
545        "Sarw": { "opcodes": [ "66", "C1", "7" ] },
546        "Shlw": { "opcodes": [ "66", "C1", "4" ] },
547        "Shrw": { "opcodes": [ "66", "C1", "5" ] },
548        "SubwImm8": { "opcodes": [ "66", "83", "5" ] },
549        "XorwImm8": { "opcodes": [ "66", "83", "6" ] }
550      },
551      "args": [
552        { "class": "GeneralReg16/Mem16", "usage": "use_def" },
553        { "class": "Imm8" },
554        { "class": "FLAGS", "usage": "def" }
555      ]
556    },
557    {
558      "encodings": {
559        "Andnl": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F2" ], "type": "vex_rm_to_reg" }
560      },
561      "args": [
562        { "class": "GeneralReg32", "usage": "def" },
563        { "class": "GeneralReg32", "usage": "use" },
564        { "class": "GeneralReg32/Mem32", "usage": "use" },
565        { "class": "FLAGS", "usage": "def" }
566      ]
567    },
568    {
569      "encodings": {
570        "Bextrl": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F7" ] },
571        "Bzhil": { "feature": "BMI2", "opcodes": [ "C4", "02", "00", "F5" ] }
572      },
573      "args": [
574        { "class": "GeneralReg32", "usage": "use_def" },
575        { "class": "GeneralReg32/Mem32", "usage": "use" },
576        { "class": "GeneralReg32", "usage": "use" },
577        { "class": "FLAGS", "usage": "def" }
578      ]
579    },
580    {
581      "encodings": {
582        "Blsil": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F3", "3" ], "type": "rm_to_vex" },
583        "Blsmskl": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F3", "2" ], "type": "rm_to_vex" },
584        "Blsrl": { "feature": "BMI", "opcodes": [ "C4", "02", "00", "F3", "1" ], "type": "rm_to_vex" },
585        "Bsfl": { "opcodes": [ "0F", "BC" ] },
586        "Bsrl": { "opcodes": [ "0F", "BD" ] },
587        "Lzcntl": { "feature": "LZCNT", "opcodes": [ "F3", "0F", "BD" ] },
588        "Popcntl": { "feature": "POPCNT", "opcodes": [ "F3", "0F", "B8" ] },
589        "Tzcntl": { "feature": "BMI", "opcodes": [ "F3", "0F", "BC" ] }
590      },
591      "args": [
592        { "class": "GeneralReg32", "usage": "def" },
593        { "class": "GeneralReg32/Mem32", "usage": "use" },
594        { "class": "FLAGS", "usage": "def" }
595      ]
596    },
597    {
598      "encodings": {
599        "Bsfw": { "opcodes": [ "66", "0F", "BC" ] },
600        "Bsrw": { "opcodes": [ "66", "0F", "BD" ] },
601        "Lzcntw": { "feature": "LZCNT", "opcodes": [ "66", "F3", "0F", "BD" ] },
602        "Popcntw": { "feature": "POPCNT", "opcodes": [ "66", "F3", "0F", "B8" ] },
603        "Tzcntw": { "feature": "BMI", "opcodes": [ "66", "F3", "0F", "BC" ] }
604      },
605      "args": [
606        { "class": "GeneralReg16", "usage": "def" },
607        { "class": "GeneralReg16/Mem16", "usage": "use" },
608        { "class": "FLAGS", "usage": "def" }
609      ]
610    },
611    {
612      "encodings": {
613        "Bswapl": { "opcodes": [ "0F", "C8" ] }
614      },
615      "args": [
616        { "class": "GeneralReg32", "usage": "use_def" }
617      ]
618    },
619    {
620      "encodings": {
621        "Btl": { "opcodes": [ "0F", "A3" ], "type": "reg_to_rm" },
622        "Cmpl": { "opcode": "39", "type": "reg_to_rm" },
623        "Testl": { "opcode": "85", "type": "reg_to_rm" }
624      },
625      "args": [
626        { "class": "GeneralReg32/Mem32", "usage": "use" },
627        { "class": "GeneralReg32", "usage": "use" },
628        { "class": "FLAGS", "usage": "def" }
629      ]
630    },
631    {
632      "encodings": {
633        "Btw": { "opcodes": [ "66", "0F", "A3" ], "type": "reg_to_rm" },
634        "Cmpw": { "opcodes": [ "66", "39" ], "type": "reg_to_rm" },
635        "Testw": { "opcodes": [ "66", "85" ], "type": "reg_to_rm" }
636      },
637      "args": [
638        { "class": "GeneralReg16/Mem16", "usage": "use" },
639        { "class": "GeneralReg16", "usage": "use" },
640        { "class": "FLAGS", "usage": "def" }
641      ]
642    },
643    {
644      "encodings": {
645        "Call": { "opcodes": [ "FF", "02" ] },
646        "Push": { "opcode": "50" }
647      },
648      "args": [
649        { "class": "RSP", "usage": "use_def" },
650        { "class": "GeneralReg", "usage": "use" }
651      ]
652    },
653    {
654      "stems": [ "Call" ],
655      "args": [
656        { "class": "RSP", "usage": "use_def" },
657        { "class": "Label" }
658      ]
659    },
660    {
661      "encodings": {
662        "Cbtw": { "opcodes": [ "66", "98" ] },
663        "Cbw": { "opcodes": [ "66", "98" ] }
664      },
665      "args": [
666        { "class": "AL", "usage": "use" },
667        { "class": "AX", "usage": "def" }
668      ]
669    },
670    {
671      "encodings": {
672        "Cdq": { "opcode": "99" },
673        "Cltd": { "opcode": "99" }
674      },
675      "args": [
676        { "class": "EAX", "usage": "use" },
677        { "class": "EDX", "usage": "def" }
678      ]
679    },
680    {
681      "encodings": {
682        "Clc": { "opcode": "F8" },
683        "Cmc": { "opcode": "F5" },
684        "Stc": { "opcode": "F9" }
685      },
686      "args": [
687        { "class": "FLAGS", "usage": "use_def" }
688      ]
689    },
690    {
691      "encodings": {
692        "Cmovl": { "opcodes": [ "0F", "40" ] }
693      },
694      "args": [
695        { "class": "Cond" },
696        { "class": "GeneralReg32", "usage": "use_def" },
697        { "class": "GeneralReg32/Mem32", "usage": "use" },
698        { "class": "FLAGS", "usage": "use" }
699      ]
700    },
701    {
702      "encodings": {
703        "Cmovw": { "opcodes": [ "66", "0F", "40" ] }
704      },
705      "args": [
706        { "class": "Cond" },
707        { "class": "GeneralReg16", "usage": "use_def" },
708        { "class": "GeneralReg16/Mem16", "usage": "use" },
709        { "class": "FLAGS", "usage": "use" }
710      ]
711    },
712    {
713      "encodings": {
714        "CmpXchg8b": { "opcodes": [ "0F", "C7", "1" ] },
715        "Lock CmpXchg8b": { "opcodes": [ "F0", "0F", "C7", "1" ] }
716      },
717      "args": [
718        { "class": "EAX", "usage": "use_def" },
719        { "class": "EDX", "usage": "use_def" },
720        { "class": "EBX", "usage": "use" },
721        { "class": "ECX", "usage": "use" },
722        { "class": "VecMem64", "usage": "use_def" },
723        { "class": "FLAGS", "usage": "def" }
724      ]
725    },
726    {
727      "encodings": {
728        "CmpXchgl": { "opcodes": [ "0F", "B1" ], "type": "reg_to_rm" }
729      },
730      "args": [
731        { "class": "EAX", "usage": "use_def" },
732        { "class": "GeneralReg32/Mem32", "usage": "use_def" },
733        { "class": "GeneralReg32", "usage": "use" },
734        { "class": "FLAGS", "usage": "def" }
735      ]
736    },
737    {
738      "encodings": {
739        "Cmpb": { "opcode": "38", "type": "reg_to_rm" },
740        "Testb": { "opcode": "84", "type": "reg_to_rm" }
741      },
742      "args": [
743        { "class": "GeneralReg8/Mem8", "usage": "use" },
744        { "class": "GeneralReg8", "usage": "use" },
745        { "class": "FLAGS", "usage": "def" }
746      ]
747    },
748    {
749      "encodings": {
750        "Cmpb": { "opcodes": [ "80", "7" ] },
751        "Testb": { "opcodes": [ "F6", "0" ] }
752      },
753      "args": [
754        { "class": "GeneralReg8/Mem8", "usage": "use" },
755        { "class": "Imm8" },
756        { "class": "FLAGS", "usage": "def" }
757      ]
758    },
759    {
760      "encodings": {
761        "Cmpb": { "opcode": "3A" }
762      },
763      "args": [
764        { "class": "GeneralReg8", "usage": "use" },
765        { "class": "Mem8", "usage": "use" },
766        { "class": "FLAGS", "usage": "def" }
767      ]
768    },
769    {
770      "encodings": {
771        "CmpbAccumulator": { "opcode": "3C" },
772        "TestbAccumulator": { "opcode": "A8" }
773      },
774      "args": [
775        { "class": "AL", "usage": "use" },
776        { "class": "Imm8" },
777        { "class": "FLAGS", "usage": "def" }
778      ]
779    },
780    {
781      "encodings": {
782        "Cmpl": { "opcodes": [ "81", "7" ] },
783        "Testl": { "opcodes": [ "F7", "0" ] }
784      },
785      "args": [
786        { "class": "GeneralReg32/Mem32", "usage": "use" },
787        { "class": "Imm32" },
788        { "class": "FLAGS", "usage": "def" }
789      ]
790    },
791    {
792      "encodings": {
793        "Cmpl": { "opcode": "3B" }
794      },
795      "args": [
796        { "class": "GeneralReg32", "usage": "use" },
797        { "class": "Mem32", "usage": "use" },
798        { "class": "FLAGS", "usage": "def" }
799      ]
800    },
801    {
802      "encodings": {
803        "CmplAccumulator": { "opcode": "3D" },
804        "TestlAccumulator": { "opcode": "A9" }
805      },
806      "args": [
807        { "class": "EAX", "usage": "use" },
808        { "class": "Imm32" },
809        { "class": "FLAGS", "usage": "def" }
810      ]
811    },
812    {
813      "encodings": {
814        "CmplImm8": { "opcodes": [ "83", "7" ] }
815      },
816      "args": [
817        { "class": "GeneralReg32/Mem32", "usage": "use" },
818        { "class": "Imm8" },
819        { "class": "FLAGS", "usage": "def" }
820      ]
821    },
822    {
823      "encodings": {
824        "Cmpw": { "opcodes": [ "66", "81", "7" ] },
825        "Testw": { "opcodes": [ "66", "F7", "0" ] }
826      },
827      "args": [
828        { "class": "GeneralReg16/Mem16", "usage": "use" },
829        { "class": "Imm16" },
830        { "class": "FLAGS", "usage": "def" }
831      ]
832    },
833    {
834      "encodings": {
835        "Cmpw": { "opcodes": [ "66", "3B" ] }
836      },
837      "args": [
838        { "class": "GeneralReg16", "usage": "use" },
839        { "class": "Mem16", "usage": "use" },
840        { "class": "FLAGS", "usage": "def" }
841      ]
842    },
843    {
844      "encodings": {
845        "CmpwAccumulator": { "opcodes": [ "66", "3D" ] },
846        "TestwAccumulator": { "opcodes": [ "66", "A9" ] }
847      },
848      "args": [
849        { "class": "AX", "usage": "use" },
850        { "class": "Imm16" },
851        { "class": "FLAGS", "usage": "def" }
852      ]
853    },
854    {
855      "encodings": {
856        "CmpwImm8": { "opcodes": [ "66", "83", "7" ] }
857      },
858      "args": [
859        { "class": "GeneralReg16/Mem16", "usage": "use" },
860        { "class": "Imm8" },
861        { "class": "FLAGS", "usage": "def" }
862      ]
863    },
864    {
865      "encodings": {
866        "Cvtdq2pd": { "opcodes": [ "F3", "0F", "E6" ] },
867        "Cvtdq2ps": { "opcodes": [ "0F", "5B" ] },
868        "Cvtpd2dq": { "opcodes": [ "F2", "0F", "E6" ] },
869        "Cvtpd2ps": { "opcodes": [ "66", "0F", "5A" ] },
870        "Cvtps2dq": { "opcodes": [ "66", "0F", "5B" ] },
871        "Cvtps2pd": { "opcodes": [ "0F", "5A" ] },
872        "Cvttpd2dq": { "opcodes": [ "66", "0F", "E6" ] },
873        "Cvttps2dq": { "opcodes": [ "F3", "0F", "5B" ] },
874        "Vcvtdq2pd": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "E6" ] },
875        "Vcvtdq2ps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "5B" ] },
876        "Vcvtpd2dq": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "E6" ] },
877        "Vcvtpd2ps": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "5A" ] },
878        "Vcvtps2dq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "5B" ] },
879        "Vcvtps2pd": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "5A" ] },
880        "Vcvttpd2dq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "E6" ] },
881        "Vcvttps2dq": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "5B" ] }
882      },
883      "args": [
884        { "class": "VecReg128", "usage": "def" },
885        { "class": "VecReg128/VecMem128", "usage": "use" }
886      ]
887    },
888    {
889      "encodings": {
890        "Cvtsd2sil": { "opcodes": [ "F2", "0F", "2D" ] },
891        "Cvttsd2sil": { "opcodes": [ "F2", "0F", "2C" ] },
892        "Vcvtsd2sil": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "2D" ] },
893        "Vcvttsd2sil": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "2C" ] }
894      },
895      "args": [
896        { "class": "GeneralReg32", "usage": "def" },
897        { "class": "FpReg64/VecMem64", "usage": "use" }
898      ]
899    },
900    {
901      "encodings": {
902        "Cvtsd2ss": { "opcodes": [ "F2", "0F", "5A" ] }
903      },
904      "args": [
905        { "class": "FpReg32", "usage": "def" },
906        { "class": "FpReg64/VecMem64", "usage": "use" }
907      ]
908    },
909    {
910      "encodings": {
911        "Cvtsi2sdl": { "opcodes": [ "F2", "0F", "2A" ] }
912      },
913      "args": [
914        { "class": "FpReg64", "usage": "def" },
915        { "class": "GeneralReg32/Mem32", "usage": "use" }
916      ]
917    },
918    {
919      "encodings": {
920        "Cvtsi2ssl": { "opcodes": [ "F3", "0F", "2A" ] }
921      },
922      "args": [
923        { "class": "FpReg32", "usage": "def" },
924        { "class": "GeneralReg32/Mem32", "usage": "use" }
925      ]
926    },
927    {
928      "encodings": {
929        "Cvtss2sd": { "opcodes": [ "F3", "0F", "5A" ] }
930      },
931      "args": [
932        { "class": "FpReg64", "usage": "def" },
933        { "class": "FpReg32/VecMem32", "usage": "use" }
934      ]
935    },
936    {
937      "encodings": {
938        "Cvtss2sil": { "opcodes": [ "F3", "0F", "2D" ] },
939        "Cvttss2sil": { "opcodes": [ "F3", "0F", "2C" ] },
940        "Vcvtss2sil": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "2D" ] },
941        "Vcvttss2sil": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "2C" ] }
942      },
943      "args": [
944        { "class": "GeneralReg32", "usage": "def" },
945        { "class": "FpReg32/VecMem32", "usage": "use" }
946      ]
947    },
948    {
949      "encodings": {
950        "Cwd": { "opcodes": [ "66", "99" ] },
951        "Cwtd": { "opcodes": [ "66", "99" ] }
952      },
953      "args": [
954        { "class": "AX", "usage": "use" },
955        { "class": "DX", "usage": "def" }
956      ]
957    },
958    {
959      "encodings": {
960        "Cwde": { "opcode": "98" },
961        "Cwtl": { "opcode": "98" }
962      },
963      "args": [
964        { "class": "AX", "usage": "use" },
965        { "class": "EAX", "usage": "def" }
966      ]
967    },
968    {
969      "encodings": {
970        "Decb": { "opcodes": [ "FE", "1" ] },
971        "Incb": { "opcodes": [ "FE", "0" ] },
972        "Negb": { "opcodes": [ "F6", "3" ] },
973        "RolbByOne": { "opcodes": [ "D0", "0" ] },
974        "RorbByOne": { "opcodes": [ "D0", "1" ] },
975        "SarbByOne": { "opcodes": [ "D0", "7" ] },
976        "ShlbByOne": { "opcodes": [ "D0", "4" ] },
977        "ShrbByOne": { "opcodes": [ "D0", "5" ] }
978      },
979      "args": [
980        { "class": "GeneralReg8/Mem8", "usage": "use_def" },
981        { "class": "FLAGS", "usage": "def" }
982      ]
983    },
984    {
985      "encodings": {
986        "Decl": { "opcodes": [ "FF", "1" ] },
987        "Incl": { "opcodes": [ "FF", "0" ] }
988      },
989      "args": [
990        { "class": "Mem32", "usage": "use_def" },
991        { "class": "FLAGS", "usage": "def" }
992      ]
993    },
994    {
995      "encodings": {
996        "Decw": { "opcodes": [ "66", "FF", "1" ] },
997        "Incw": { "opcodes": [ "66", "FF", "0" ] }
998      },
999      "args": [
1000        { "class": "Mem16", "usage": "use_def" },
1001        { "class": "FLAGS", "usage": "def" }
1002      ]
1003    },
1004    {
1005      "encodings": {
1006        "Divb": { "opcodes": [ "F6", "6" ] },
1007        "Idivb": { "opcodes": [ "F6", "7" ] }
1008      },
1009      "args": [
1010        { "class": "AX", "usage": "use_def" },
1011        { "class": "GeneralReg8/Mem8", "usage": "use" },
1012        { "class": "FLAGS", "usage": "def" }
1013      ]
1014    },
1015    {
1016      "encodings": {
1017        "Divl": { "opcodes": [ "F7", "6" ] },
1018        "Idivl": { "opcodes": [ "F7", "7" ] }
1019      },
1020      "args": [
1021        { "class": "EAX", "usage": "use_def" },
1022        { "class": "EDX", "usage": "use_def" },
1023        { "class": "GeneralReg32/Mem32", "usage": "use" },
1024        { "class": "FLAGS", "usage": "def" }
1025      ]
1026    },
1027    {
1028      "encodings": {
1029        "Divw": { "opcodes": [ "66", "F7", "6" ] },
1030        "Idivw": { "opcodes": [ "66", "F7", "7" ] }
1031      },
1032      "args": [
1033        { "class": "AX", "usage": "use_def" },
1034        { "class": "DX", "usage": "use_def" },
1035        { "class": "GeneralReg16/Mem16", "usage": "use" },
1036        { "class": "FLAGS", "usage": "def" }
1037      ]
1038    },
1039    {
1040      "encodings": {
1041        "F2xm1": { "opcodes": [ "D9", "F0" ] },
1042        "Fabs": { "opcodes": [ "D9", "E1" ] },
1043        "Fchs": { "opcodes": [ "D9", "E0" ] },
1044        "Fcos": { "opcodes": [ "D9", "FF" ] },
1045        "Frndint": { "opcodes": [ "D9", "FC" ] },
1046        "Fscale": { "opcodes": [ "D9", "FD" ] },
1047        "Fsin": { "opcodes": [ "D9", "FE" ] },
1048        "Fsqrt": { "opcodes": [ "D9", "FA" ] },
1049        "Ftst": { "opcodes": [ "D9", "E4" ] }
1050      },
1051      "args": [
1052        { "class": "ST", "usage": "use_def" }
1053      ]
1054    },
1055    {
1056      "encodings": {
1057        "FaddFromSt": { "opcodes": [ "DC", "0" ] },
1058        "FaddpFromSt": { "opcodes": [ "DE", "0" ] },
1059        "FdivFromSt": { "opcodes": [ "DC", "6" ] },
1060        "FdivpFromSt": { "opcodes": [ "DE", "6" ] },
1061        "FdivrFromSt": { "opcodes": [ "DC", "7" ] },
1062        "FdivrpFromSt": { "opcodes": [ "DE", "7" ] },
1063        "FmulFromSt": { "opcodes": [ "DC", "1" ] },
1064        "FmulpFromSt": { "opcodes": [ "DE", "1" ] },
1065        "FsubFromSt": { "opcodes": [ "DC", "4" ] },
1066        "FsubpFromSt": { "opcodes": [ "DE", "4" ] },
1067        "FsubrFromSt": { "opcodes": [ "DC", "5" ] },
1068        "FsubrpFromSt": { "opcodes": [ "DE", "5" ] }
1069      },
1070      "args": [
1071        { "class": "RegX87", "usage": "use_def" },
1072        { "class": "ST", "usage": "use" }
1073      ]
1074    },
1075    {
1076      "encodings": {
1077        "FaddToSt": { "opcodes": [ "D8", "0" ] },
1078        "FdivToSt": { "opcodes": [ "D8", "6" ] },
1079        "FdivrToSt": { "opcodes": [ "D8", "7" ] },
1080        "FmulToSt": { "opcodes": [ "D8", "1" ] },
1081        "FsubToSt": { "opcodes": [ "D8", "4" ] },
1082        "FsubrToSt": { "opcodes": [ "D8", "5" ] }
1083      },
1084      "args": [
1085        { "class": "ST", "usage": "use_def" },
1086        { "class": "RegX87", "usage": "use" }
1087      ]
1088    },
1089    {
1090      "encodings": {
1091        "Faddl": { "opcodes": [ "DC", "0" ] },
1092        "Fdivl": { "opcodes": [ "DC", "6" ] },
1093        "Fdivrl": { "opcodes": [ "DC", "7" ] },
1094        "Fmull": { "opcodes": [ "DC", "1" ] },
1095        "Fsubl": { "opcodes": [ "DC", "4" ] },
1096        "Fsubrl": { "opcodes": [ "DC", "5" ] }
1097      },
1098      "args": [
1099        { "class": "ST", "usage": "use_def" },
1100        { "class": "MemX8764", "usage": "use" }
1101      ]
1102    },
1103    {
1104      "encodings": {
1105        "Fadds": { "opcodes": [ "D8", "0" ] },
1106        "Fdivrs": { "opcodes": [ "D8", "7" ] },
1107        "Fdivs": { "opcodes": [ "D8", "6" ] },
1108        "Fiaddl": { "opcodes": [ "DA", "0" ] },
1109        "Fidivl": { "opcodes": [ "DA", "6" ] },
1110        "Fidivrl": { "opcodes": [ "DA", "7" ] },
1111        "Fimull": { "opcodes": [ "DA", "1" ] },
1112        "Fisubl": { "opcodes": [ "DA", "4" ] },
1113        "Fisubrl": { "opcodes": [ "DA", "5" ] },
1114        "Fmuls": { "opcodes": [ "D8", "1" ] },
1115        "Fsubrs": { "opcodes": [ "D8", "5" ] },
1116        "Fsubs": { "opcodes": [ "D8", "4" ] }
1117      },
1118      "args": [
1119        { "class": "ST", "usage": "use_def" },
1120        { "class": "MemX8732", "usage": "use" }
1121      ]
1122    },
1123    {
1124      "encodings": {
1125        "Fbld": { "opcodes": [ "DF", "4" ] },
1126        "Fldt": { "opcodes": [ "DB", "5" ] }
1127      },
1128      "args": [
1129        { "class": "ST", "usage": "def" },
1130        { "class": "MemX8780", "usage": "use" }
1131      ]
1132    },
1133    {
1134      "encodings": {
1135        "Fbstp": { "opcodes": [ "DF", "6" ] },
1136        "Fstpt": { "opcodes": [ "DB", "7" ] }
1137      },
1138      "args": [
1139        { "class": "MemX8780", "usage": "def" },
1140        { "class": "ST", "usage": "use" }
1141      ]
1142    },
1143    {
1144      "encodings": {
1145        "FcmovbToSt": { "opcodes": [ "DA", "0" ] },
1146        "FcmovbeToSt": { "opcodes": [ "DA", "2" ] },
1147        "FcmoveToSt": { "opcodes": [ "DA", "1" ] },
1148        "FcmovnbToSt": { "opcodes": [ "DB", "0" ] },
1149        "FcmovnbeToSt": { "opcodes": [ "DB", "2" ] },
1150        "FcmovneToSt": { "opcodes": [ "DB", "1" ] },
1151        "FcmovnuToSt": { "opcodes": [ "DB", "3" ] },
1152        "FcmovuToSt": { "opcodes": [ "DA", "3" ] }
1153      },
1154      "args": [
1155        { "class": "ST", "usage": "use_def" },
1156        { "class": "RegX87", "usage": "use" },
1157        { "class": "FLAGS", "usage": "use" }
1158      ]
1159    },
1160    {
1161      "encodings": {
1162        "Fcom": { "opcodes": [ "D8", "2" ] },
1163        "Fcomp": { "opcodes": [ "D8", "3" ] },
1164        "Fucom": { "opcodes": [ "DD", "4" ] },
1165        "Fucomp": { "opcodes": [ "DD", "5" ] }
1166      },
1167      "args": [
1168        { "class": "ST", "usage": "use" },
1169        { "class": "RegX87", "usage": "use" },
1170        { "class": "CC", "usage": "def" }
1171      ]
1172    },
1173    {
1174      "encodings": {
1175        "Fcomi": { "opcodes": [ "DB", "6" ] },
1176        "Fcomip": { "opcodes": [ "DF", "6" ] },
1177        "Fucomi": { "opcodes": [ "DB", "5" ] },
1178        "Fucomip": { "opcodes": [ "DF", "5" ] }
1179      },
1180      "args": [
1181        { "class": "ST", "usage": "use" },
1182        { "class": "RegX87", "usage": "use" },
1183        { "class": "FLAGS", "usage": "def" }
1184      ]
1185    },
1186    {
1187      "encodings": {
1188        "Fcoml": { "opcodes": [ "DC", "2" ] },
1189        "Fcompl": { "opcodes": [ "DC", "3" ] }
1190      },
1191      "args": [
1192        { "class": "ST", "usage": "use" },
1193        { "class": "MemX8764", "usage": "use" },
1194        { "class": "CC", "usage": "def" }
1195      ]
1196    },
1197    {
1198      "encodings": {
1199        "Fcompp": { "opcodes": [ "DE", "D9" ] },
1200        "Fucompp": { "opcodes": [ "DA", "E9" ] }
1201      },
1202      "args": [
1203        { "class": "ST", "usage": "use" },
1204        { "class": "ST1", "usage": "use" },
1205        { "class": "CC", "usage": "def" }
1206      ]
1207    },
1208    {
1209      "encodings": {
1210        "Fcomps": { "opcodes": [ "D8", "3" ] },
1211        "Fcoms": { "opcodes": [ "D8", "2" ] },
1212        "Ficoml": { "opcodes": [ "DA", "2" ] },
1213        "Ficompl": { "opcodes": [ "DA", "3" ] }
1214      },
1215      "args": [
1216        { "class": "ST", "usage": "use" },
1217        { "class": "MemX8732", "usage": "use" },
1218        { "class": "CC", "usage": "def" }
1219      ]
1220    },
1221    {
1222      "encodings": {
1223        "Fdecstp": { "opcodes": [ "D9", "F6" ] },
1224        "Fincstp": { "opcodes": [ "D9", "F7" ] },
1225        "Fnop": { "opcodes": [ "D9", "D0" ] },
1226        "Fwait": { "opcode": "9B" },
1227        "Int3": { "opcode": "CC" },
1228        "Lfence": { "opcodes": [ "0F", "AE", "E8" ] },
1229        "Mfence": { "opcodes": [ "0F", "AE", "F0" ] },
1230        "Nop": { "opcode": "90" },
1231        "Sfence": { "opcodes": [ "0F", "AE", "F8" ] },
1232        "UD2": { "opcodes": [ "0F", "0B" ] },
1233        "Wait": { "opcode": "9B" }
1234      },
1235      "args": []
1236    },
1237    {
1238      "encodings": {
1239        "Ffree": { "opcodes": [ "DD", "0" ] }
1240      },
1241      "args": [
1242        { "class": "RegX87", "usage": "use" }
1243      ]
1244    },
1245    {
1246      "encodings": {
1247        "Fiadds": { "opcodes": [ "DE", "0" ] },
1248        "Fidivrs": { "opcodes": [ "DE", "7" ] },
1249        "Fidivs": { "opcodes": [ "DE", "6" ] },
1250        "Fimuls": { "opcodes": [ "DE", "1" ] },
1251        "Fisubrs": { "opcodes": [ "DE", "5" ] },
1252        "Fisubs": { "opcodes": [ "DE", "4" ] }
1253      },
1254      "args": [
1255        { "class": "ST", "usage": "use_def" },
1256        { "class": "MemX8716", "usage": "use" }
1257      ]
1258    },
1259    {
1260      "encodings": {
1261        "Ficomps": { "opcodes": [ "DE", "3" ] },
1262        "Ficoms": { "opcodes": [ "DE", "2" ] }
1263      },
1264      "args": [
1265        { "class": "ST", "usage": "use" },
1266        { "class": "MemX8716", "usage": "use" },
1267        { "class": "CC", "usage": "def" }
1268      ]
1269    },
1270    {
1271      "encodings": {
1272        "Fildl": { "opcodes": [ "DB", "0" ] },
1273        "Flds": { "opcodes": [ "D9", "0" ] }
1274      },
1275      "args": [
1276        { "class": "ST", "usage": "def" },
1277        { "class": "MemX8732", "usage": "use" }
1278      ]
1279    },
1280    {
1281      "encodings": {
1282        "Fildll": { "opcodes": [ "DF", "5" ] },
1283        "Fldl": { "opcodes": [ "DD", "0" ] }
1284      },
1285      "args": [
1286        { "class": "ST", "usage": "def" },
1287        { "class": "MemX8764", "usage": "use" }
1288      ]
1289    },
1290    {
1291      "encodings": {
1292        "Filds": { "opcodes": [ "DF", "0" ] }
1293      },
1294      "args": [
1295        { "class": "ST", "usage": "def" },
1296        { "class": "MemX8716", "usage": "use" }
1297      ]
1298    },
1299    {
1300      "encodings": {
1301        "Fistl": { "opcodes": [ "DB", "2" ] },
1302        "Fistpl": { "opcodes": [ "DB", "3" ] },
1303        "Fisttpl": { "feature": "SSE3", "opcodes": [ "DB", "1" ] },
1304        "Fstps": { "opcodes": [ "D9", "3" ] },
1305        "Fsts": { "opcodes": [ "D9", "2" ] }
1306      },
1307      "args": [
1308        { "class": "MemX8732", "usage": "def" },
1309        { "class": "ST", "usage": "use" }
1310      ]
1311    },
1312    {
1313      "encodings": {
1314        "Fistpll": { "opcodes": [ "DF", "7" ] },
1315        "Fisttpll": { "feature": "SSE3", "opcodes": [ "DD", "1" ] },
1316        "Fstl": { "opcodes": [ "DD", "2" ] },
1317        "Fstpl": { "opcodes": [ "DD", "3" ] }
1318      },
1319      "args": [
1320        { "class": "MemX8764", "usage": "def" },
1321        { "class": "ST", "usage": "use" }
1322      ]
1323    },
1324    {
1325      "encodings": {
1326        "Fistps": { "opcodes": [ "DF", "3" ] },
1327        "Fists": { "opcodes": [ "DF", "2" ] },
1328        "Fisttps": { "feature": "SSE3", "opcodes": [ "DF", "1" ] }
1329      },
1330      "args": [
1331        { "class": "MemX8716", "usage": "def" },
1332        { "class": "ST", "usage": "use" }
1333      ]
1334    },
1335    {
1336      "encodings": {
1337        "Fld1": { "opcodes": [ "D9", "E8" ] },
1338        "Fldl2e": { "opcodes": [ "D9", "EA" ] },
1339        "Fldl2t": { "opcodes": [ "D9", "E9" ] },
1340        "Fldlg2": { "opcodes": [ "D9", "EC" ] },
1341        "Fldln2": { "opcodes": [ "D9", "ED" ] },
1342        "Fldpi": { "opcodes": [ "D9", "EB" ] },
1343        "Fldz": { "opcodes": [ "D9", "EE" ] }
1344      },
1345      "args": [
1346        { "class": "ST", "usage": "use_def" }
1347      ]
1348    },
1349    {
1350      "encodings": {
1351        "Fld": { "opcodes": [ "D9", "0" ] }
1352      },
1353      "args": [
1354        { "class": "ST", "usage": "def" },
1355        { "class": "RegX87", "usage": "use" }
1356      ]
1357    },
1358    {
1359      "encodings": {
1360        "Fldcw": { "opcodes": [ "D9", "5" ] }
1361      },
1362      "args": [
1363        { "class": "CC", "usage": "def" },
1364        { "class": "MemX8732", "usage": "use" }
1365      ]
1366    },
1367    {
1368      "encodings": {
1369        "Fldenv": { "opcodes": [ "D9", "4" ] },
1370        "Frstor": { "opcodes": [ "DD", "4" ] },
1371        "Fxrstor": { "opcodes": [ "0F", "AE", "1" ] }
1372      },
1373      "args": [
1374        { "class": "MemX87", "usage": "use" },
1375        { "class": "CC", "usage": "def" }
1376      ]
1377    },
1378    {
1379      "encodings": {
1380        "Fnclex": { "opcodes": [ "DB", "E2" ] },
1381        "Fndisi": { "opcodes": [ "DB", "E1" ] },
1382        "Fneni": { "opcodes": [ "DB", "E0" ] },
1383        "Fninit": { "opcodes": [ "DB", "E3" ] },
1384        "Fnsetpm": { "opcodes": [ "DB", "E4" ] }
1385      },
1386      "args": [
1387        { "class": "CC", "usage": "def" }
1388      ]
1389    },
1390    {
1391      "encodings": {
1392        "Fnsave": { "opcodes": [ "DD", "6" ] },
1393        "Fnstenv": { "opcodes": [ "D9", "6" ] },
1394        "Fxsave": { "opcodes": [ "0F", "AE", "0" ] }
1395      },
1396      "args": [
1397        { "class": "CC", "usage": "def" },
1398        { "class": "MemX87", "usage": "use" }
1399      ]
1400    },
1401    {
1402      "encodings": {
1403        "Fnstcw": { "opcodes": [ "D9", "7" ] }
1404      },
1405      "args": [
1406        { "class": "MemX8732", "usage": "def" },
1407        { "class": "CC", "usage": "use" }
1408      ]
1409    },
1410    {
1411      "encodings": {
1412        "Fnstsw": { "opcodes": [ "DF", "E0" ] }
1413      },
1414      "args": [
1415        { "class": "AX", "usage": "def" },
1416        { "class": "SW", "usage": "use" }
1417      ]
1418    },
1419    {
1420      "encodings": {
1421        "Fnstsw": { "opcodes": [ "DD", "7" ] }
1422      },
1423      "args": [
1424        { "class": "MemX8732", "usage": "def" },
1425        { "class": "SW", "usage": "use" }
1426      ]
1427    },
1428    {
1429      "encodings": {
1430        "Fpatan": { "opcodes": [ "D9", "F3" ] },
1431        "Fprem": { "opcodes": [ "D9", "F8" ] },
1432        "Fprem1": { "opcodes": [ "D9", "F5" ] },
1433        "Fyl2x": { "opcodes": [ "D9", "F1" ] },
1434        "Fyl2xp1": { "opcodes": [ "D9", "F9" ] }
1435      },
1436      "args": [
1437        { "class": "ST", "usage": "use_def" },
1438        { "class": "ST1", "usage": "use" }
1439      ]
1440    },
1441    {
1442      "encodings": {
1443        "Fptan": { "opcodes": [ "D9", "F2" ] },
1444        "Fsincos": { "opcodes": [ "D9", "FB" ] },
1445        "Fxtract": { "opcodes": [ "D9", "F4" ] }
1446      },
1447      "args": [
1448        { "class": "ST", "usage": "use_def" },
1449        { "class": "ST1", "usage": "def" }
1450      ]
1451    },
1452    {
1453      "encodings": {
1454        "Fst": { "opcodes": [ "DD", "2" ] },
1455        "Fstp": { "opcodes": [ "DD", "3" ] }
1456      },
1457      "args": [
1458        { "class": "RegX87", "usage": "def" },
1459        { "class": "ST", "usage": "use" }
1460      ]
1461    },
1462    {
1463      "encodings": {
1464        "Fxam": { "opcodes": [ "D9", "E5" ] }
1465      },
1466      "args": [
1467        { "class": "ST", "usage": "use" },
1468        { "class": "CC", "usage": "def" }
1469      ]
1470    },
1471    {
1472      "encodings": {
1473        "Fxch": { "opcodes": [ "D9", "1" ] }
1474      },
1475      "args": [
1476        { "class": "RegX87", "usage": "use_def" },
1477        { "class": "ST", "usage": "use_def" }
1478      ]
1479    },
1480    {
1481      "encodings": {
1482        "Imulb": { "opcodes": [ "F6", "5" ] },
1483        "Mulb": { "opcodes": [ "F6", "4" ] }
1484      },
1485      "args": [
1486        { "class": "AL", "usage": "use" },
1487        { "class": "AX", "usage": "def" },
1488        { "class": "GeneralReg8/Mem8", "usage": "use" },
1489        { "class": "FLAGS", "usage": "def" }
1490      ]
1491    },
1492    {
1493      "encodings": {
1494        "Imull": { "opcodes": [ "F7", "5" ] },
1495        "Mull": { "opcodes": [ "F7", "4" ] }
1496      },
1497      "args": [
1498        { "class": "EAX", "usage": "use_def" },
1499        { "class": "EDX", "usage": "def" },
1500        { "class": "GeneralReg32/Mem32", "usage": "use" },
1501        { "class": "FLAGS", "usage": "def" }
1502      ]
1503    },
1504    {
1505      "encodings": {
1506        "Imull": { "opcode": "69" }
1507      },
1508      "args": [
1509        { "class": "GeneralReg32", "usage": "def" },
1510        { "class": "GeneralReg32/Mem32", "usage": "use" },
1511        { "class": "Imm32" },
1512        { "class": "FLAGS", "usage": "def" }
1513      ]
1514    },
1515    {
1516      "encodings": {
1517        "Imull": { "opcodes": [ "0F", "AF" ] }
1518      },
1519      "args": [
1520        { "class": "GeneralReg32", "usage": "use_def" },
1521        { "class": "GeneralReg32/Mem32", "usage": "use" },
1522        { "class": "FLAGS", "usage": "def" }
1523      ]
1524    },
1525    {
1526      "encodings": {
1527        "ImullImm8": { "opcode": "6B" }
1528      },
1529      "args": [
1530        { "class": "GeneralReg32", "usage": "def" },
1531        { "class": "GeneralReg32/Mem32", "usage": "use" },
1532        { "class": "Imm8" },
1533        { "class": "FLAGS", "usage": "def" }
1534      ]
1535    },
1536    {
1537      "encodings": {
1538        "Imulw": { "opcodes": [ "66", "F7", "5" ] },
1539        "Mulw": { "opcodes": [ "66", "F7", "4" ] }
1540      },
1541      "args": [
1542        { "class": "AX", "usage": "use_def" },
1543        { "class": "DX", "usage": "def" },
1544        { "class": "GeneralReg16/Mem16", "usage": "use" },
1545        { "class": "FLAGS", "usage": "def" }
1546      ]
1547    },
1548    {
1549      "encodings": {
1550        "Imulw": { "opcodes": [ "66", "69" ] }
1551      },
1552      "args": [
1553        { "class": "GeneralReg16", "usage": "def" },
1554        { "class": "GeneralReg16/Mem16", "usage": "use" },
1555        { "class": "Imm16" },
1556        { "class": "FLAGS", "usage": "def" }
1557      ]
1558    },
1559    {
1560      "encodings": {
1561        "Imulw": { "opcodes": [ "66", "0F", "AF" ] }
1562      },
1563      "args": [
1564        { "class": "GeneralReg16", "usage": "use_def" },
1565        { "class": "GeneralReg16/Mem16", "usage": "use" },
1566        { "class": "FLAGS", "usage": "def" }
1567      ]
1568    },
1569    {
1570      "encodings": {
1571        "ImulwImm8": { "opcodes": [ "66", "6B" ] }
1572      },
1573      "args": [
1574        { "class": "GeneralReg16", "usage": "def" },
1575        { "class": "GeneralReg16/Mem16", "usage": "use" },
1576        { "class": "Imm8" },
1577        { "class": "FLAGS", "usage": "def" }
1578      ]
1579    },
1580    {
1581      "stems": [ "Jcc" ],
1582      "args": [
1583        { "class": "Cond" },
1584        { "class": "Label" },
1585        { "class": "FLAGS", "usage": "use" }
1586      ]
1587    },
1588    {
1589      "encodings": {
1590        "Jmp": { "opcodes": [ "FF", "4" ] }
1591      },
1592      "args": [
1593        { "class": "GeneralReg", "usage": "use" }
1594      ]
1595    },
1596    {
1597      "stems": [ "Jmp" ],
1598      "args": [
1599        { "class": "Label" }
1600      ]
1601    },
1602    {
1603      "encodings": {
1604        "Lahf": { "opcode": "9F" }
1605      },
1606      "args": [
1607        { "class": "EAX", "usage": "use_def" },
1608        { "class": "FLAGS", "usage": "use" }
1609      ],
1610      "comment": "Use use_def below because LAHF writes to AH while preserving the rest of RAX"
1611    },
1612    {
1613      "encodings": {
1614        "Ldmxcsr": { "opcodes": [ "0F", "AE", "2" ] },
1615        "Vldmxcsr": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "AE", "2" ] }
1616      },
1617      "args": [
1618        { "class": "Mem32", "usage": "use" }
1619      ]
1620    },
1621    {
1622      "encodings": {
1623        "Leal": { "opcode": "8D" }
1624      },
1625      "args": [
1626        { "class": "GeneralReg32", "usage": "def" },
1627        { "class": "Mem", "usage": "use" }
1628      ]
1629    },
1630    {
1631      "encodings": {
1632        "Lock CmpXchgb": { "opcodes": [ "F0", "0F", "B0" ], "type": "reg_to_rm" }
1633      },
1634      "args": [
1635        { "class": "AL", "usage": "use_def" },
1636        { "class": "Mem8", "usage": "use_def" },
1637        { "class": "GeneralReg8", "usage": "use" },
1638        { "class": "FLAGS", "usage": "def" }
1639      ]
1640    },
1641    {
1642      "encodings": {
1643        "Lock CmpXchgl": { "opcodes": [ "F0", "0F", "B1" ], "type": "reg_to_rm" }
1644      },
1645      "args": [
1646        { "class": "EAX", "usage": "use_def" },
1647        { "class": "Mem32", "usage": "use_def" },
1648        { "class": "GeneralReg32", "usage": "use" },
1649        { "class": "FLAGS", "usage": "def" }
1650      ]
1651    },
1652    {
1653      "encodings": {
1654        "Lock CmpXchgw": { "opcodes": [ "F0", "66", "0F", "B1" ], "type": "reg_to_rm" }
1655      },
1656      "args": [
1657        { "class": "AX", "usage": "use_def" },
1658        { "class": "Mem16", "usage": "use_def" },
1659        { "class": "GeneralReg16", "usage": "use" },
1660        { "class": "FLAGS", "usage": "def" }
1661      ]
1662    },
1663    {
1664      "encodings": {
1665        "Lock Xaddb": { "opcodes": [ "F0", "0F", "C0" ], "type": "reg_to_rm" },
1666        "Xaddb": { "opcodes": [ "0F", "C0" ], "type": "reg_to_rm" }
1667      },
1668      "args": [
1669        { "class": "Mem8", "usage": "use_def" },
1670        { "class": "GeneralReg8", "usage": "use_def" },
1671        { "class": "FLAGS", "usage": "use_def" }
1672      ]
1673    },
1674    {
1675      "encodings": {
1676        "Lock Xaddl": { "opcodes": [ "F0", "0F", "C1" ], "type": "reg_to_rm" },
1677        "Xaddl": { "opcodes": [ "0F", "C1" ], "type": "reg_to_rm" }
1678      },
1679      "args": [
1680        { "class": "Mem32", "usage": "use_def" },
1681        { "class": "GeneralReg32", "usage": "use_def" },
1682        { "class": "FLAGS", "usage": "use_def" }
1683      ]
1684    },
1685    {
1686      "encodings": {
1687        "Lock Xaddw": { "opcodes": [ "F0", "66", "0F", "C1" ], "type": "reg_to_rm" },
1688        "Xaddw": { "opcodes": [ "66", "0F", "C1" ], "type": "reg_to_rm" }
1689      },
1690      "args": [
1691        { "class": "Mem16", "usage": "use_def" },
1692        { "class": "GeneralReg16", "usage": "use_def" },
1693        { "class": "FLAGS", "usage": "use_def" }
1694      ]
1695    },
1696    {
1697      "encodings": {
1698        "Movapd": { "opcodes": [ "66", "0F", "29" ] },
1699        "Movaps": { "opcodes": [ "0F", "29" ] },
1700        "Vmovapd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "29" ] },
1701        "Vmovaps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "29" ] }
1702      },
1703      "args": [
1704        { "class": "VecMem128", "usage": "def" },
1705        { "class": "XmmReg", "usage": "use" }
1706      ]
1707    },
1708    {
1709      "encodings": {
1710        "Movapd": { "opcodes": [ "66", "0F", "28" ] },
1711        "Movaps": { "opcodes": [ "0F", "28" ] }
1712      },
1713      "args": [
1714        { "class": "XmmReg", "usage": "def" },
1715        { "class": "XmmReg/VecMem128", "usage": "use" }
1716      ]
1717    },
1718    {
1719      "encodings": {
1720        "Movb": { "opcode": "B0" }
1721      },
1722      "args": [
1723        { "class": "GeneralReg8", "usage": "def" },
1724        { "class": "Imm8" }
1725      ]
1726    },
1727    {
1728      "encodings": {
1729        "Movb": { "opcode": "8A" }
1730      },
1731      "args": [
1732        { "class": "GeneralReg8", "usage": "def" },
1733        { "class": "Mem8", "usage": "use" }
1734      ]
1735    },
1736    {
1737      "encodings": {
1738        "Movb": { "opcode": "88", "type": "reg_to_rm" }
1739      },
1740      "args": [
1741        { "class": "GeneralReg8/Mem8", "usage": "def" },
1742        { "class": "GeneralReg8", "usage": "use" }
1743      ]
1744    },
1745    {
1746      "encodings": {
1747        "Movb": { "opcodes": [ "C6", "0" ] }
1748      },
1749      "args": [
1750        { "class": "Mem8", "usage": "def" },
1751        { "class": "Imm8" }
1752      ]
1753    },
1754    {
1755      "encodings": {
1756        "Movd": { "opcodes": [ "66", "0F", "7E" ], "type": "reg_to_rm" },
1757        "Vmovd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "7E" ], "type": "reg_to_rm" }
1758      },
1759      "args": [
1760        { "class": "GeneralReg32/Mem32", "usage": "def" },
1761        { "class": "XmmReg", "usage": "use" }
1762      ]
1763    },
1764    {
1765      "encodings": {
1766        "Movd": { "opcodes": [ "66", "0F", "6E" ] },
1767        "Vmovd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "6E" ] }
1768      },
1769      "args": [
1770        { "class": "XmmReg", "usage": "def" },
1771        { "class": "GeneralReg32/Mem32", "usage": "use" }
1772      ]
1773    },
1774    {
1775      "name": "MovdqRegReg",
1776      "args": [
1777        { "class": "XmmReg", "usage": "def" },
1778        { "class": "XmmReg", "usage": "use" }
1779      ],
1780      "asm": "Pmov",
1781      "mnemo": "MOVDQ"
1782    },
1783    {
1784      "encodings": {
1785        "Movdqa": { "opcodes": [ "66", "0F", "7F" ] },
1786        "Movdqu": { "opcodes": [ "F3", "0F", "7F" ] },
1787        "Vmovdqa": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "7F" ] },
1788        "Vmovdqu": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "7F" ] }
1789      },
1790      "args": [
1791        { "class": "VecMem128", "usage": "def" },
1792        { "class": "XmmReg", "usage": "use" }
1793      ]
1794    },
1795    {
1796      "encodings": {
1797        "Movdqa": { "opcodes": [ "66", "0F", "6F" ] },
1798        "Movdqu": { "opcodes": [ "F3", "0F", "6F" ] }
1799      },
1800      "args": [
1801        { "class": "XmmReg", "usage": "def" },
1802        { "class": "XmmReg/VecMem128", "usage": "use" }
1803      ]
1804    },
1805    {
1806      "encodings": {
1807        "Movhlps": { "opcodes": [ "0F", "12" ] },
1808        "Movlhps": { "opcodes": [ "0F", "16" ] },
1809        "Movsd": { "opcodes": [ "F2", "0F", "10" ] },
1810        "Movss": { "opcodes": [ "F3", "0F", "10" ] }
1811      },
1812      "args": [
1813        { "class": "XmmReg", "usage": "use_def" },
1814        { "class": "XmmReg", "usage": "use" }
1815      ],
1816      "comment": "Upper bits (lower bits for Movlhps) are unchanged"
1817    },
1818    {
1819      "encodings": {
1820        "Movhpd": { "opcodes": [ "66", "0F", "17" ] },
1821        "Movhps": { "opcodes": [ "0F", "17" ] },
1822        "Movlpd": { "opcodes": [ "66", "0F", "13" ] },
1823        "Movlps": { "opcodes": [ "0F", "13" ] },
1824        "Vmovhpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "17" ] },
1825        "Vmovhps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "17" ] },
1826        "Vmovlpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "13" ] },
1827        "Vmovlps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "13" ] }
1828      },
1829      "args": [
1830        { "class": "VecMem64", "usage": "use_def" },
1831        { "class": "XmmReg", "usage": "use" }
1832      ]
1833    },
1834    {
1835      "encodings": {
1836        "Movhpd": { "opcodes": [ "66", "0F", "16" ] },
1837        "Movhps": { "opcodes": [ "0F", "16" ] },
1838        "Movlpd": { "opcodes": [ "66", "0F", "12" ] },
1839        "Movlps": { "opcodes": [ "0F", "12" ] }
1840      },
1841      "args": [
1842        { "class": "XmmReg", "usage": "use_def" },
1843        { "class": "VecMem64", "usage": "use" }
1844      ]
1845    },
1846    {
1847      "encodings": {
1848        "Movl": { "opcode": "B8" }
1849      },
1850      "args": [
1851        { "class": "GeneralReg32", "usage": "def" },
1852        { "class": "Imm32" }
1853      ]
1854    },
1855    {
1856      "encodings": {
1857        "Movl": { "opcode": "8B" }
1858      },
1859      "args": [
1860        { "class": "GeneralReg32", "usage": "def" },
1861        { "class": "Mem32", "usage": "use" }
1862      ]
1863    },
1864    {
1865      "encodings": {
1866        "Movl": { "opcode": "89", "type": "reg_to_rm" }
1867      },
1868      "args": [
1869        { "class": "GeneralReg32/Mem32", "usage": "def" },
1870        { "class": "GeneralReg32", "usage": "use" }
1871      ]
1872    },
1873    {
1874      "encodings": {
1875        "Movl": { "opcodes": [ "C7", "0" ] }
1876      },
1877      "args": [
1878        { "class": "Mem32", "usage": "def" },
1879        { "class": "Imm32" }
1880      ]
1881    },
1882    {
1883      "encodings": {
1884        "Movmskpd": { "opcodes": [ "66", "0F", "50" ] },
1885        "Movmskps": { "opcodes": [ "0F", "50" ] },
1886        "Vmovmskpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "50" ] },
1887        "Vmovmskps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "50" ] }
1888      },
1889      "args": [
1890        { "class": "GeneralReg32", "usage": "def" },
1891        { "class": "XmmReg", "usage": "use" }
1892      ]
1893    },
1894    {
1895      "encodings": {
1896        "Movq": { "opcodes": [ "66", "0F", "D6" ] },
1897        "Movsd": { "opcodes": [ "F2", "0F", "11" ] },
1898        "Vmovq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "D6" ] },
1899        "Vmovsd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "11" ] }
1900      },
1901      "args": [
1902        { "class": "VecMem64", "usage": "def" },
1903        { "class": "XmmReg", "usage": "use" }
1904      ]
1905    },
1906    {
1907      "encodings": {
1908        "Movq": { "opcodes": [ "F3", "0F", "7E" ] },
1909        "Pmovsxbw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "20" ] },
1910        "Pmovsxdq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "25" ] },
1911        "Pmovsxwd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "23" ] },
1912        "Pmovzxbw": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "30" ] },
1913        "Pmovzxdq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "35" ] },
1914        "Pmovzxwd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "33" ] },
1915        "Vmovq": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "7E" ] }
1916      },
1917      "args": [
1918        { "class": "XmmReg", "usage": "def" },
1919        { "class": "XmmReg/VecMem64", "usage": "use" }
1920      ],
1921      "comment": "Upper bits are zero-filled for Movq/Vmovq"
1922    },
1923    {
1924      "encodings": {
1925        "Movsd": { "opcodes": [ "F2", "0F", "10" ] },
1926        "Vmovsd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "10" ] }
1927      },
1928      "args": [
1929        { "class": "XmmReg", "usage": "def" },
1930        { "class": "VecMem64", "usage": "use" }
1931      ],
1932      "comment": "Upper bits are zero-filled"
1933    },
1934    {
1935      "encodings": {
1936        "Movss": { "opcodes": [ "F3", "0F", "10" ] },
1937        "Vmovss": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "10" ] }
1938      },
1939      "args": [
1940        { "class": "XmmReg", "usage": "def" },
1941        { "class": "VecMem32", "usage": "use" }
1942      ],
1943      "comment": "Upper bits are zero-filled"
1944    },
1945    {
1946      "encodings": {
1947        "Movss": { "opcodes": [ "F3", "0F", "11" ] }
1948      },
1949      "args": [
1950        { "class": "Mem32", "usage": "def" },
1951        { "class": "XmmReg", "usage": "use" }
1952      ]
1953    },
1954    {
1955      "encodings": {
1956        "Movsxbl": { "opcodes": [ "0F", "BE" ] },
1957        "Movzxbl": { "opcodes": [ "0F", "B6" ] }
1958      },
1959      "args": [
1960        { "class": "GeneralReg32", "usage": "def" },
1961        { "class": "GeneralReg8/Mem8", "usage": "use" }
1962      ]
1963    },
1964    {
1965      "encodings": {
1966        "Movsxwl": { "opcodes": [ "0F", "BF" ] },
1967        "Movzxwl": { "opcodes": [ "0F", "B7" ] }
1968      },
1969      "args": [
1970        { "class": "GeneralReg32", "usage": "def" },
1971        { "class": "GeneralReg16/Mem16", "usage": "use" }
1972      ]
1973    },
1974    {
1975      "encodings": {
1976        "Movw": { "opcodes": [ "66", "B8" ] }
1977      },
1978      "args": [
1979        { "class": "GeneralReg16", "usage": "def" },
1980        { "class": "Imm16" }
1981      ]
1982    },
1983    {
1984      "encodings": {
1985        "Movw": { "opcodes": [ "66", "8B" ] }
1986      },
1987      "args": [
1988        { "class": "GeneralReg16", "usage": "def" },
1989        { "class": "Mem16", "usage": "use" }
1990      ]
1991    },
1992    {
1993      "encodings": {
1994        "Movw": { "opcodes": [ "66", "89" ], "type": "reg_to_rm" }
1995      },
1996      "args": [
1997        { "class": "GeneralReg16/Mem16", "usage": "def" },
1998        { "class": "GeneralReg16", "usage": "use" }
1999      ]
2000    },
2001    {
2002      "encodings": {
2003        "Movw": { "opcodes": [ "66", "C7", "0" ] }
2004      },
2005      "args": [
2006        { "class": "Mem16", "usage": "def" },
2007        { "class": "Imm16" }
2008      ]
2009    },
2010    {
2011      "encodings": {
2012        "Mulxl": { "feature": "BMI2", "opcodes": [ "C4", "02", "03", "F6" ], "type": "vex_rm_to_reg" },
2013        "Pdepl": { "feature": "BMI2", "opcodes": [ "C4", "02", "03", "F5" ], "type": "vex_rm_to_reg" },
2014        "Pextl": { "feature": "BMI2", "opcodes": [ "C4", "02", "02", "F5" ], "type": "vex_rm_to_reg" }
2015      },
2016      "args": [
2017        { "class": "GeneralReg32", "usage": "use_def" },
2018        { "class": "GeneralReg32", "usage": "use" },
2019        { "class": "GeneralReg32/Mem32", "usage": "use" }
2020      ]
2021    },
2022    {
2023      "encodings": {
2024        "Negl": { "opcodes": [ "F7", "3" ] },
2025        "RollByOne": { "opcodes": [ "D1", "0" ] },
2026        "RorlByOne": { "opcodes": [ "D1", "1" ] },
2027        "SarlByOne": { "opcodes": [ "D1", "7" ] },
2028        "ShllByOne": { "opcodes": [ "D1", "4" ] },
2029        "ShrlByOne": { "opcodes": [ "D1", "5" ] }
2030      },
2031      "args": [
2032        { "class": "GeneralReg32/Mem32", "usage": "use_def" },
2033        { "class": "FLAGS", "usage": "def" }
2034      ]
2035    },
2036    {
2037      "encodings": {
2038        "Negw": { "opcodes": [ "66", "F7", "3" ] },
2039        "RolwByOne": { "opcodes": [ "66", "D1", "0" ] },
2040        "RorwByOne": { "opcodes": [ "66", "D1", "1" ] },
2041        "SarwByOne": { "opcodes": [ "66", "D1", "7" ] },
2042        "ShlwByOne": { "opcodes": [ "66", "D1", "4" ] },
2043        "ShrwByOne": { "opcodes": [ "66", "D1", "5" ] }
2044      },
2045      "args": [
2046        { "class": "GeneralReg16/Mem16", "usage": "use_def" },
2047        { "class": "FLAGS", "usage": "def" }
2048      ]
2049    },
2050    {
2051      "encodings": {
2052        "Notb": { "opcodes": [ "F6", "2" ] }
2053      },
2054      "args": [
2055        { "class": "GeneralReg8/Mem8", "usage": "use_def" }
2056      ]
2057    },
2058    {
2059      "encodings": {
2060        "Notl": { "opcodes": [ "F7", "2" ] }
2061      },
2062      "args": [
2063        { "class": "GeneralReg32/Mem32", "usage": "use_def" }
2064      ]
2065    },
2066    {
2067      "encodings": {
2068        "Notw": { "opcodes": [ "66", "F7", "2" ] }
2069      },
2070      "args": [
2071        { "class": "GeneralReg16/Mem16", "usage": "use_def" }
2072      ]
2073    },
2074    {
2075      "encodings": {
2076        "Pextrb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "14" ], "type": "reg_to_rm" },
2077        "Pextrd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "16" ], "type": "reg_to_rm" },
2078        "Pextrw": { "opcodes": [ "66", "0F", "C5" ] },
2079        "Vpextrb": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "14" ], "type": "reg_to_rm" },
2080        "Vpextrd": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "16" ], "type": "reg_to_rm" },
2081        "Vpextrw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C5" ] }
2082      },
2083      "args": [
2084        { "class": "GeneralReg32", "usage": "def" },
2085        { "class": "VecReg128", "usage": "use" },
2086        { "class": "Imm8" }
2087      ]
2088    },
2089    {
2090      "encodings": {
2091        "Pinsrb": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "20" ] },
2092        "Pinsrd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "22" ] },
2093        "Pinsrw": { "opcodes": [ "66", "0F", "C4" ] }
2094      },
2095      "args": [
2096        { "class": "VecReg128", "usage": "use_def" },
2097        { "class": "GeneralReg32", "usage": "use" },
2098        { "class": "Imm8" }
2099      ]
2100    },
2101    {
2102      "encodings": {
2103        "Pmovmskb": { "opcodes": [ "66", "0F", "D7" ] },
2104        "Vpmovmskb": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "D7" ] }
2105      },
2106      "args": [
2107        { "class": "GeneralReg32", "usage": "def" },
2108        { "class": "VecReg128", "usage": "use" }
2109      ]
2110    },
2111    {
2112      "encodings": {
2113        "Pmovsxbd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "21" ] },
2114        "Pmovsxwq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "24" ] },
2115        "Pmovzxbd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "31" ] },
2116        "Pmovzxwq": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "38", "34" ] }
2117      },
2118      "args": [
2119        { "class": "XmmReg", "usage": "def" },
2120        { "class": "XmmReg/VecMem32", "usage": "use" }
2121      ]
2122    },
2123    {
2124      "encodings": {
2125        "Pop": { "opcode": "58" }
2126      },
2127      "args": [
2128        { "class": "RSP", "usage": "use_def" },
2129        { "class": "GeneralReg", "usage": "def" }
2130      ]
2131    },
2132    {
2133      "encodings": {
2134        "Pshufd": { "opcodes": [ "66", "0F", "70" ] },
2135        "Pshufhw": { "opcodes": [ "F3", "0F", "70" ] },
2136        "Pshuflw": { "opcodes": [ "F2", "0F", "70" ] },
2137        "Roundpd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "09" ] },
2138        "Roundps": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "08" ] },
2139        "Vpshufd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "70" ] },
2140        "Vpshufhw": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "70" ] },
2141        "Vpshuflw": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "70" ] },
2142        "Vroundpd": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "09" ] },
2143        "Vroundps": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "08" ] }
2144      },
2145      "args": [
2146        { "class": "VecReg128", "usage": "def" },
2147        { "class": "VecReg128/VecMem128", "usage": "use" },
2148        { "class": "Imm8" }
2149      ]
2150    },
2151    {
2152      "encodings": {
2153        "Pslld": { "opcodes": [ "66", "0F", "72", "6" ] },
2154        "Pslldq": { "opcodes": [ "66", "0F", "73", "7" ] },
2155        "Psllq": { "opcodes": [ "66", "0F", "73", "6" ] },
2156        "Psllw": { "opcodes": [ "66", "0F", "71", "6" ] },
2157        "Psrad": { "opcodes": [ "66", "0F", "72", "4" ] },
2158        "Psraw": { "opcodes": [ "66", "0F", "71", "4" ] },
2159        "Psrld": { "opcodes": [ "66", "0F", "72", "2" ] },
2160        "Psrldq": { "opcodes": [ "66", "0F", "73", "3" ] },
2161        "Psrlq": { "opcodes": [ "66", "0F", "73", "2" ] },
2162        "Psrlw": { "opcodes": [ "66", "0F", "71", "2" ] }
2163      },
2164      "args": [
2165        { "class": "VecReg128", "usage": "use_def" },
2166        { "class": "Imm8" }
2167      ]
2168    },
2169    {
2170      "encodings": {
2171        "Push": { "opcode": "68" }
2172      },
2173      "args": [
2174        { "class": "RSP", "usage": "use_def" },
2175        { "class": "Imm32" }
2176      ]
2177    },
2178    {
2179      "encodings": {
2180        "PushImm8": { "opcode": "6A" }
2181      },
2182      "args": [
2183        { "class": "RSP", "usage": "use_def" },
2184        { "class": "Imm8" }
2185      ]
2186    },
2187    {
2188      "encodings": {
2189        "RclbByCl": { "opcodes": [ "D2", "2" ] },
2190        "RcrbByCl": { "opcodes": [ "D2", "3" ] }
2191      },
2192      "args": [
2193        { "class": "GeneralReg8/Mem8", "usage": "use_def" },
2194        { "class": "CL", "usage": "use" },
2195        { "class": "FLAGS", "usage": "use_def" }
2196      ]
2197    },
2198    {
2199      "encodings": {
2200        "RclbByOne": { "opcodes": [ "D0", "2" ] },
2201        "RcrbByOne": { "opcodes": [ "D0", "3" ] }
2202      },
2203      "args": [
2204        { "class": "GeneralReg8/Mem8", "usage": "use_def" },
2205        { "class": "FLAGS", "usage": "use_def" }
2206      ]
2207    },
2208    {
2209      "encodings": {
2210        "RcllByCl": { "opcodes": [ "D3", "2" ] },
2211        "RcrlByCl": { "opcodes": [ "D3", "3" ] }
2212      },
2213      "args": [
2214        { "class": "GeneralReg32/Mem32", "usage": "use_def" },
2215        { "class": "CL", "usage": "use" },
2216        { "class": "FLAGS", "usage": "use_def" }
2217      ]
2218    },
2219    {
2220      "encodings": {
2221        "RcllByOne": { "opcodes": [ "D1", "2" ] },
2222        "RcrlByOne": { "opcodes": [ "D1", "3" ] }
2223      },
2224      "args": [
2225        { "class": "GeneralReg32/Mem32", "usage": "use_def" },
2226        { "class": "FLAGS", "usage": "use_def" }
2227      ]
2228    },
2229    {
2230      "encodings": {
2231        "RclwByCl": { "opcodes": [ "66", "D3", "2" ] },
2232        "RcrwByCl": { "opcodes": [ "66", "D3", "3" ] }
2233      },
2234      "args": [
2235        { "class": "GeneralReg16/Mem16", "usage": "use_def" },
2236        { "class": "CL", "usage": "use" },
2237        { "class": "FLAGS", "usage": "use_def" }
2238      ]
2239    },
2240    {
2241      "encodings": {
2242        "RclwByOne": { "opcodes": [ "66", "D1", "2" ] },
2243        "RcrwByOne": { "opcodes": [ "66", "D1", "3" ] }
2244      },
2245      "args": [
2246        { "class": "GeneralReg16/Mem16", "usage": "use_def" },
2247        { "class": "FLAGS", "usage": "use_def" }
2248      ]
2249    },
2250    {
2251      "encodings": {
2252        "Ret": { "opcode": "C3" }
2253      },
2254      "args": [
2255        { "class": "RSP", "usage": "use_def" }
2256      ]
2257    },
2258    {
2259      "encodings": {
2260        "RolbByCl": { "opcodes": [ "D2", "0" ] },
2261        "RorbByCl": { "opcodes": [ "D2", "1" ] },
2262        "SarbByCl": { "opcodes": [ "D2", "7" ] },
2263        "ShlbByCl": { "opcodes": [ "D2", "4" ] },
2264        "ShrbByCl": { "opcodes": [ "D2", "5" ] }
2265      },
2266      "args": [
2267        { "class": "GeneralReg8/Mem8", "usage": "use_def" },
2268        { "class": "CL", "usage": "use" },
2269        { "class": "FLAGS", "usage": "def" }
2270      ]
2271    },
2272    {
2273      "encodings": {
2274        "RollByCl": { "opcodes": [ "D3", "0" ] },
2275        "RorlByCl": { "opcodes": [ "D3", "1" ] },
2276        "SarlByCl": { "opcodes": [ "D3", "7" ] },
2277        "ShllByCl": { "opcodes": [ "D3", "4" ] },
2278        "ShrlByCl": { "opcodes": [ "D3", "5" ] }
2279      },
2280      "args": [
2281        { "class": "GeneralReg32/Mem32", "usage": "use_def" },
2282        { "class": "CL", "usage": "use" },
2283        { "class": "FLAGS", "usage": "def" }
2284      ]
2285    },
2286    {
2287      "encodings": {
2288        "RolwByCl": { "opcodes": [ "66", "D3", "0" ] },
2289        "RorwByCl": { "opcodes": [ "66", "D3", "1" ] },
2290        "SarwByCl": { "opcodes": [ "66", "D3", "7" ] },
2291        "ShlwByCl": { "opcodes": [ "66", "D3", "4" ] },
2292        "ShrwByCl": { "opcodes": [ "66", "D3", "5" ] }
2293      },
2294      "args": [
2295        { "class": "GeneralReg16/Mem16", "usage": "use_def" },
2296        { "class": "CL", "usage": "use" },
2297        { "class": "FLAGS", "usage": "def" }
2298      ]
2299    },
2300    {
2301      "encodings": {
2302        "Rorxl": { "feature": "BMI2", "opcodes": [ "C4", "03", "03", "F0" ] }
2303      },
2304      "args": [
2305        { "class": "GeneralReg32", "usage": "def" },
2306        { "class": "GeneralReg32/Mem32", "usage": "use" },
2307        { "class": "Imm8" }
2308      ]
2309    },
2310    {
2311      "encodings": {
2312        "Roundsd": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "0B" ] }
2313      },
2314      "args": [
2315        { "class": "FpReg64", "usage": "def" },
2316        { "class": "FpReg64/VecMem64", "usage": "use" },
2317        { "class": "Imm8" }
2318      ]
2319    },
2320    {
2321      "encodings": {
2322        "Roundss": { "feature": "SSE4_1", "opcodes": [ "66", "0F", "3A", "0A" ] }
2323      },
2324      "args": [
2325        { "class": "FpReg32", "usage": "def" },
2326        { "class": "FpReg32/VecMem32", "usage": "use" },
2327        { "class": "Imm8" }
2328      ]
2329    },
2330    {
2331      "encodings": {
2332        "Sahf": { "opcode": "9E" }
2333      },
2334      "args": [
2335        { "class": "EAX", "usage": "use" },
2336        { "class": "FLAGS", "usage": "def" }
2337      ]
2338    },
2339    {
2340      "encodings": {
2341        "Sarxl": { "feature": "BMI2", "opcodes": [ "C4", "02", "02", "F7" ] },
2342        "Shlxl": { "feature": "BMI2", "opcodes": [ "C4", "02", "01", "F7" ] },
2343        "Shrxl": { "feature": "BMI2", "opcodes": [ "C4", "02", "03", "F7" ] }
2344      },
2345      "args": [
2346        { "class": "GeneralReg32", "usage": "use_def" },
2347        { "class": "GeneralReg32/Mem32", "usage": "use" },
2348        { "class": "GeneralReg32", "usage": "use" }
2349      ]
2350    },
2351    {
2352      "encodings": {
2353        "Setcc": { "opcodes": [ "0F", "90", "0" ] }
2354      },
2355      "args": [
2356        { "class": "Cond" },
2357        { "class": "GeneralReg8/Mem8", "usage": "def" },
2358        { "class": "FLAGS", "usage": "use" }
2359      ]
2360    },
2361    {
2362      "encodings": {
2363        "Shldl": { "opcodes": [ "0F", "A4" ], "type": "reg_to_rm" },
2364        "Shrdl": { "opcodes": [ "0F", "AC" ], "type": "reg_to_rm" }
2365      },
2366      "args": [
2367        { "class": "GeneralReg32/Mem32", "usage": "use_def" },
2368        { "class": "GeneralReg32", "usage": "use" },
2369        { "class": "Imm8" },
2370        { "class": "FLAGS", "usage": "def" }
2371      ]
2372    },
2373    {
2374      "encodings": {
2375        "ShldlByCl": { "opcodes": [ "0F", "A5" ], "type": "reg_to_rm" },
2376        "ShrdlByCl": { "opcodes": [ "0F", "AD" ], "type": "reg_to_rm" }
2377      },
2378      "args": [
2379        { "class": "GeneralReg32/Mem32", "usage": "use_def" },
2380        { "class": "GeneralReg32", "usage": "use" },
2381        { "class": "CL", "usage": "use" },
2382        { "class": "FLAGS", "usage": "def" }
2383      ]
2384    },
2385    {
2386      "encodings": {
2387        "Shufpd": { "opcodes": [ "66", "0F", "C6" ] },
2388        "Shufps": { "opcodes": [ "0F", "C6" ] }
2389      },
2390      "args": [
2391        { "class": "VecReg128", "usage": "use_def" },
2392        { "class": "VecReg128/VecMem128", "usage": "use" },
2393        { "class": "Imm8" }
2394      ]
2395    },
2396    {
2397      "encodings": {
2398        "Sqrtsd": { "opcodes": [ "F2", "0F", "51" ] }
2399      },
2400      "args": [
2401        { "class": "FpReg64", "usage": "def" },
2402        { "class": "FpReg64/VecMem64", "usage": "use" }
2403      ]
2404    },
2405    {
2406      "encodings": {
2407        "Sqrtss": { "opcodes": [ "F3", "0F", "51" ] }
2408      },
2409      "args": [
2410        { "class": "FpReg32", "usage": "def" },
2411        { "class": "FpReg32/VecMem32", "usage": "use" }
2412      ]
2413    },
2414    {
2415      "encodings": {
2416        "Stmxcsr": { "opcodes": [ "0F", "AE", "3" ] },
2417        "Vstmxcsr": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "AE", "3" ] }
2418      },
2419      "args": [
2420        { "class": "Mem32", "usage": "def" }
2421      ]
2422    },
2423    {
2424      "encodings": {
2425        "Ucomisd": { "opcodes": [ "66", "0F", "2E" ] }
2426      },
2427      "args": [
2428        { "class": "FpReg64", "usage": "use" },
2429        { "class": "FpReg64/VecMem64", "usage": "use" },
2430        { "class": "FLAGS", "usage": "def" }
2431      ]
2432    },
2433    {
2434      "encodings": {
2435        "Ucomiss": { "opcodes": [ "0F", "2E" ] }
2436      },
2437      "args": [
2438        { "class": "FpReg32", "usage": "use" },
2439        { "class": "FpReg32/VecMem32", "usage": "use" },
2440        { "class": "FLAGS", "usage": "def" }
2441      ]
2442    },
2443    {
2444      "encodings": {
2445        "Vaddpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "58" ], "type": "optimizable_using_commutation" },
2446        "Vaddps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "58" ], "type": "optimizable_using_commutation" },
2447        "Vandpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "54" ], "type": "optimizable_using_commutation" },
2448        "Vandps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "54" ], "type": "optimizable_using_commutation" },
2449        "Vcmpeqpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "00" ], "type": "optimizable_using_commutation" },
2450        "Vcmpeqps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "00" ], "type": "optimizable_using_commutation" },
2451        "Vcmplepd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "02" ], "type": "vex_rm_to_reg" },
2452        "Vcmpleps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "02" ], "type": "vex_rm_to_reg" },
2453        "Vcmpltpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "01" ], "type": "vex_rm_to_reg" },
2454        "Vcmpltps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "01" ], "type": "vex_rm_to_reg" },
2455        "Vcmpneqpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "04" ], "type": "optimizable_using_commutation" },
2456        "Vcmpneqps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "04" ], "type": "optimizable_using_commutation" },
2457        "Vcmpnlepd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "06" ], "type": "vex_rm_to_reg" },
2458        "Vcmpnleps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "06" ], "type": "vex_rm_to_reg" },
2459        "Vcmpnltpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "05" ], "type": "vex_rm_to_reg" },
2460        "Vcmpnltps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "05" ], "type": "vex_rm_to_reg" },
2461        "Vcmpordpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "07" ], "type": "optimizable_using_commutation" },
2462        "Vcmpordps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "07" ], "type": "optimizable_using_commutation" },
2463        "Vcmpunordpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C2", "03" ], "type": "optimizable_using_commutation" },
2464        "Vcmpunordps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C2", "03" ], "type": "optimizable_using_commutation" },
2465        "Vdivpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "5E" ], "type": "vex_rm_to_reg" },
2466        "Vdivps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "5E" ], "type": "vex_rm_to_reg" },
2467        "Vhaddpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "7C" ], "type": "vex_rm_to_reg" },
2468        "Vhaddps": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "7C" ], "type": "vex_rm_to_reg" },
2469        "Vmaxpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "5F" ], "type": "vex_rm_to_reg" },
2470        "Vmaxps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "5F" ], "type": "vex_rm_to_reg" },
2471        "Vminpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "5D" ], "type": "vex_rm_to_reg" },
2472        "Vminps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "5D" ], "type": "vex_rm_to_reg" },
2473        "Vmulpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "59" ], "type": "optimizable_using_commutation" },
2474        "Vmulps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "59" ], "type": "optimizable_using_commutation" },
2475        "Vorpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "56" ], "type": "optimizable_using_commutation" },
2476        "Vorps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "56" ], "type": "optimizable_using_commutation" },
2477        "Vpackssdw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "6B" ], "type": "vex_rm_to_reg" },
2478        "Vpacksswb": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "63" ], "type": "vex_rm_to_reg" },
2479        "Vpackusdw": { "feature": "AVX", "opcodes": [ "C4", "02", "01", "2B" ], "type": "vex_rm_to_reg" },
2480        "Vpackuswb": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "67" ], "type": "vex_rm_to_reg" },
2481        "Vpaddb": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "FC" ], "type": "optimizable_using_commutation" },
2482        "Vpaddd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "FE" ], "type": "optimizable_using_commutation" },
2483        "Vpaddq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "D4" ], "type": "optimizable_using_commutation" },
2484        "Vpaddsb": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "EC" ], "type": "optimizable_using_commutation" },
2485        "Vpaddsw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "ED" ], "type": "optimizable_using_commutation" },
2486        "Vpaddusb": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "DC" ], "type": "optimizable_using_commutation" },
2487        "Vpaddusw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "DD" ], "type": "optimizable_using_commutation" },
2488        "Vpaddw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "FD" ], "type": "optimizable_using_commutation" },
2489        "Vpand": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "DB" ], "type": "optimizable_using_commutation" },
2490        "Vpandn": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "DF" ], "type": "vex_rm_to_reg" },
2491        "Vpavgb": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "E0" ], "type": "optimizable_using_commutation" },
2492        "Vpavgw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "E3" ], "type": "optimizable_using_commutation" },
2493        "Vpcmpeqb": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "74" ], "type": "optimizable_using_commutation" },
2494        "Vpcmpeqd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "76" ], "type": "optimizable_using_commutation" },
2495        "Vpcmpeqq": { "feature": "AVX", "opcodes": [ "C4", "02", "01", "29" ], "type": "vex_rm_to_reg" },
2496        "Vpcmpeqw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "75" ], "type": "optimizable_using_commutation" },
2497        "Vpcmpgtb": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "64" ], "type": "vex_rm_to_reg" },
2498        "Vpcmpgtd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "66" ], "type": "vex_rm_to_reg" },
2499        "Vpcmpgtq": { "feature": "AVX", "opcodes": [ "C4", "02", "01", "37" ], "type": "vex_rm_to_reg" },
2500        "Vpcmpgtw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "65" ], "type": "vex_rm_to_reg" },
2501        "Vpmaxsb": { "feature": "AVX", "opcodes": [ "C4", "02", "01", "3C" ], "type": "vex_rm_to_reg" },
2502        "Vpmaxsd": { "feature": "AVX", "opcodes": [ "C4", "02", "01", "3D" ], "type": "vex_rm_to_reg" },
2503        "Vpmaxsw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "EE" ], "type": "optimizable_using_commutation" },
2504        "Vpmaxub": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "DE" ], "type": "optimizable_using_commutation" },
2505        "Vpmaxud": { "feature": "AVX", "opcodes": [ "C4", "02", "01", "3F" ], "type": "vex_rm_to_reg" },
2506        "Vpmaxuw": { "feature": "AVX", "opcodes": [ "C4", "02", "01", "3E" ], "type": "vex_rm_to_reg" },
2507        "Vpminsb": { "feature": "AVX", "opcodes": [ "C4", "02", "01", "38" ], "type": "vex_rm_to_reg" },
2508        "Vpminsd": { "feature": "AVX", "opcodes": [ "C4", "02", "01", "39" ], "type": "vex_rm_to_reg" },
2509        "Vpminsw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "EA" ], "type": "optimizable_using_commutation" },
2510        "Vpminub": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "DA" ], "type": "optimizable_using_commutation" },
2511        "Vpminud": { "feature": "AVX", "opcodes": [ "C4", "02", "01", "3B" ], "type": "vex_rm_to_reg" },
2512        "Vpminuw": { "feature": "AVX", "opcodes": [ "C4", "02", "01", "3A" ], "type": "vex_rm_to_reg" },
2513        "Vpmulhrsw": { "feature": "AVX", "opcodes": [ "C4", "02", "01", "0B" ], "type": "vex_rm_to_reg" },
2514        "Vpmulhw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "E5" ], "type": "optimizable_using_commutation" },
2515        "Vpmulld": { "feature": "AVX", "opcodes": [ "C4", "02", "01", "40" ], "type": "vex_rm_to_reg" },
2516        "Vpmullw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "D5" ], "type": "optimizable_using_commutation" },
2517        "Vpmuludq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "F4" ], "type": "optimizable_using_commutation" },
2518        "Vpor": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "EB" ], "type": "optimizable_using_commutation" },
2519        "Vpsadbw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "F6" ], "type": "optimizable_using_commutation" },
2520        "Vpshufb": { "feature": "AVX", "opcodes": [ "C4", "02", "01", "00" ], "type": "vex_rm_to_reg" },
2521        "Vpslld": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "F2" ], "type": "vex_rm_to_reg" },
2522        "Vpsllq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "F3" ], "type": "vex_rm_to_reg" },
2523        "Vpsllw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "F1" ], "type": "vex_rm_to_reg" },
2524        "Vpsrad": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "E2" ], "type": "vex_rm_to_reg" },
2525        "Vpsraw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "E1" ], "type": "vex_rm_to_reg" },
2526        "Vpsrld": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "D2" ], "type": "vex_rm_to_reg" },
2527        "Vpsrlq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "D3" ], "type": "vex_rm_to_reg" },
2528        "Vpsrlw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "D1" ], "type": "vex_rm_to_reg" },
2529        "Vpsubb": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "F8" ], "type": "vex_rm_to_reg" },
2530        "Vpsubd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "FA" ], "type": "vex_rm_to_reg" },
2531        "Vpsubq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "FB" ], "type": "vex_rm_to_reg" },
2532        "Vpsubsb": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "E8" ], "type": "vex_rm_to_reg" },
2533        "Vpsubsw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "E9" ], "type": "vex_rm_to_reg" },
2534        "Vpsubusb": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "D8" ], "type": "vex_rm_to_reg" },
2535        "Vpsubusw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "D9" ], "type": "vex_rm_to_reg" },
2536        "Vpsubw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "F9" ], "type": "vex_rm_to_reg" },
2537        "Vpunpckhbw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "68" ], "type": "vex_rm_to_reg" },
2538        "Vpunpckhdq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "6A" ], "type": "vex_rm_to_reg" },
2539        "Vpunpckhqdq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "6D" ], "type": "vex_rm_to_reg" },
2540        "Vpunpckhwd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "69" ], "type": "vex_rm_to_reg" },
2541        "Vpunpcklbw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "60" ], "type": "vex_rm_to_reg" },
2542        "Vpunpckldq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "62" ], "type": "vex_rm_to_reg" },
2543        "Vpunpcklqdq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "6C" ], "type": "vex_rm_to_reg" },
2544        "Vpunpcklwd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "61" ], "type": "vex_rm_to_reg" },
2545        "Vpxor": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "EF" ], "type": "optimizable_using_commutation" },
2546        "Vsubpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "5C" ], "type": "vex_rm_to_reg" },
2547        "Vsubps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "5C" ], "type": "vex_rm_to_reg" },
2548        "Vxorpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "57" ], "type": "optimizable_using_commutation" },
2549        "Vxorps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "57" ], "type": "optimizable_using_commutation" }
2550      },
2551      "args": [
2552        { "class": "VecReg128", "usage": "def" },
2553        { "class": "VecReg128", "usage": "use" },
2554        { "class": "VecReg128/VecMem128", "usage": "use" }
2555      ]
2556    },
2557    {
2558      "encodings": {
2559        "Vaddpd": { "feature": "AVX", "opcodes": [ "C4", "01", "05", "58" ], "type": "optimizable_using_commutation" },
2560        "Vaddps": { "feature": "AVX", "opcodes": [ "C4", "01", "04", "58" ], "type": "optimizable_using_commutation" },
2561        "Vandpd": { "feature": "AVX", "opcodes": [ "C4", "01", "05", "54" ], "type": "optimizable_using_commutation" },
2562        "Vandps": { "feature": "AVX", "opcodes": [ "C4", "01", "04", "54" ], "type": "optimizable_using_commutation" },
2563        "Vcmpeqpd": { "feature": "AVX", "opcodes": [ "C4", "01", "05", "C2", "00" ], "type": "optimizable_using_commutation" },
2564        "Vcmpeqps": { "feature": "AVX", "opcodes": [ "C4", "01", "04", "C2", "00" ], "type": "optimizable_using_commutation" },
2565        "Vcmplepd": { "feature": "AVX", "opcodes": [ "C4", "01", "05", "C2", "02" ], "type": "vex_rm_to_reg" },
2566        "Vcmpleps": { "feature": "AVX", "opcodes": [ "C4", "01", "04", "C2", "02" ], "type": "vex_rm_to_reg" },
2567        "Vcmpltpd": { "feature": "AVX", "opcodes": [ "C4", "01", "05", "C2", "01" ], "type": "vex_rm_to_reg" },
2568        "Vcmpltps": { "feature": "AVX", "opcodes": [ "C4", "01", "04", "C2", "01" ], "type": "vex_rm_to_reg" },
2569        "Vcmpneqpd": { "feature": "AVX", "opcodes": [ "C4", "01", "05", "C2", "04" ], "type": "optimizable_using_commutation" },
2570        "Vcmpneqps": { "feature": "AVX", "opcodes": [ "C4", "01", "04", "C2", "04" ], "type": "optimizable_using_commutation" },
2571        "Vcmpnlepd": { "feature": "AVX", "opcodes": [ "C4", "01", "05", "C2", "06" ], "type": "vex_rm_to_reg" },
2572        "Vcmpnleps": { "feature": "AVX", "opcodes": [ "C4", "01", "04", "C2", "06" ], "type": "vex_rm_to_reg" },
2573        "Vcmpnltpd": { "feature": "AVX", "opcodes": [ "C4", "01", "05", "C2", "05" ], "type": "vex_rm_to_reg" },
2574        "Vcmpnltps": { "feature": "AVX", "opcodes": [ "C4", "01", "04", "C2", "05" ], "type": "vex_rm_to_reg" },
2575        "Vcmpordpd": { "feature": "AVX", "opcodes": [ "C4", "01", "05", "C2", "07" ], "type": "optimizable_using_commutation" },
2576        "Vcmpordps": { "feature": "AVX", "opcodes": [ "C4", "01", "04", "C2", "07" ], "type": "optimizable_using_commutation" },
2577        "Vcmpunordpd": { "feature": "AVX", "opcodes": [ "C4", "01", "05", "C2", "03" ], "type": "optimizable_using_commutation" },
2578        "Vcmpunordps": { "feature": "AVX", "opcodes": [ "C4", "01", "04", "C2", "03" ], "type": "optimizable_using_commutation" },
2579        "Vdivpd": { "feature": "AVX", "opcodes": [ "C4", "01", "05", "5E" ], "type": "vex_rm_to_reg" },
2580        "Vdivps": { "feature": "AVX", "opcodes": [ "C4", "01", "04", "5E" ], "type": "vex_rm_to_reg" },
2581        "Vhaddpd": { "feature": "AVX", "opcodes": [ "C4", "01", "05", "7C" ], "type": "vex_rm_to_reg" },
2582        "Vhaddps": { "feature": "AVX", "opcodes": [ "C4", "01", "07", "7C" ], "type": "vex_rm_to_reg" },
2583        "Vmaxpd": { "feature": "AVX", "opcodes": [ "C4", "01", "05", "5F" ], "type": "vex_rm_to_reg" },
2584        "Vmaxps": { "feature": "AVX", "opcodes": [ "C4", "01", "04", "5F" ], "type": "vex_rm_to_reg" },
2585        "Vminpd": { "feature": "AVX", "opcodes": [ "C4", "01", "05", "5D" ], "type": "vex_rm_to_reg" },
2586        "Vminps": { "feature": "AVX", "opcodes": [ "C4", "01", "04", "5D" ], "type": "vex_rm_to_reg" },
2587        "Vmulpd": { "feature": "AVX", "opcodes": [ "C4", "01", "05", "59" ], "type": "optimizable_using_commutation" },
2588        "Vmulps": { "feature": "AVX", "opcodes": [ "C4", "01", "04", "59" ], "type": "optimizable_using_commutation" },
2589        "Vorpd": { "feature": "AVX", "opcodes": [ "C4", "01", "05", "56" ], "type": "optimizable_using_commutation" },
2590        "Vorps": { "feature": "AVX", "opcodes": [ "C4", "01", "04", "56" ], "type": "optimizable_using_commutation" },
2591        "Vpackssdw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "6B" ], "type": "vex_rm_to_reg" },
2592        "Vpacksswb": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "63" ], "type": "vex_rm_to_reg" },
2593        "Vpackusdw": { "feature": "AVX2", "opcodes": [ "C4", "02", "05", "2B" ], "type": "vex_rm_to_reg" },
2594        "Vpackuswb": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "67" ], "type": "vex_rm_to_reg" },
2595        "Vpaddb": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "FC" ], "type": "optimizable_using_commutation" },
2596        "Vpaddd": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "FE" ], "type": "optimizable_using_commutation" },
2597        "Vpaddq": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "D4" ], "type": "optimizable_using_commutation" },
2598        "Vpaddsb": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "EC" ], "type": "optimizable_using_commutation" },
2599        "Vpaddsw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "ED" ], "type": "optimizable_using_commutation" },
2600        "Vpaddusb": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "DC" ], "type": "optimizable_using_commutation" },
2601        "Vpaddusw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "DD" ], "type": "optimizable_using_commutation" },
2602        "Vpaddw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "FD" ], "type": "optimizable_using_commutation" },
2603        "Vpand": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "DB" ], "type": "optimizable_using_commutation" },
2604        "Vpandn": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "DF" ], "type": "vex_rm_to_reg" },
2605        "Vpavgb": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "E0" ], "type": "optimizable_using_commutation" },
2606        "Vpavgw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "E3" ], "type": "optimizable_using_commutation" },
2607        "Vpcmpeqb": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "74" ], "type": "optimizable_using_commutation" },
2608        "Vpcmpeqd": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "76" ], "type": "optimizable_using_commutation" },
2609        "Vpcmpeqq": { "feature": "AVX2", "opcodes": [ "C4", "02", "05", "29" ], "type": "vex_rm_to_reg" },
2610        "Vpcmpeqw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "75" ], "type": "optimizable_using_commutation" },
2611        "Vpcmpgtb": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "64" ], "type": "vex_rm_to_reg" },
2612        "Vpcmpgtd": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "66" ], "type": "vex_rm_to_reg" },
2613        "Vpcmpgtq": { "feature": "AVX2", "opcodes": [ "C4", "02", "05", "37" ], "type": "vex_rm_to_reg" },
2614        "Vpcmpgtw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "65" ], "type": "vex_rm_to_reg" },
2615        "Vpmaxsb": { "feature": "AVX2", "opcodes": [ "C4", "02", "05", "3C" ], "type": "vex_rm_to_reg" },
2616        "Vpmaxsd": { "feature": "AVX2", "opcodes": [ "C4", "02", "05", "3D" ], "type": "vex_rm_to_reg" },
2617        "Vpmaxsw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "EE" ], "type": "optimizable_using_commutation" },
2618        "Vpmaxub": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "DE" ], "type": "optimizable_using_commutation" },
2619        "Vpmaxud": { "feature": "AVX2", "opcodes": [ "C4", "02", "05", "3F" ], "type": "vex_rm_to_reg" },
2620        "Vpmaxuw": { "feature": "AVX2", "opcodes": [ "C4", "02", "05", "3E" ], "type": "vex_rm_to_reg" },
2621        "Vpminsb": { "feature": "AVX2", "opcodes": [ "C4", "02", "05", "38" ], "type": "vex_rm_to_reg" },
2622        "Vpminsd": { "feature": "AVX2", "opcodes": [ "C4", "02", "05", "39" ], "type": "vex_rm_to_reg" },
2623        "Vpminsw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "EA" ], "type": "optimizable_using_commutation" },
2624        "Vpminub": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "DA" ], "type": "optimizable_using_commutation" },
2625        "Vpminud": { "feature": "AVX2", "opcodes": [ "C4", "02", "05", "3B" ], "type": "vex_rm_to_reg" },
2626        "Vpminuw": { "feature": "AVX2", "opcodes": [ "C4", "02", "05", "3A" ], "type": "vex_rm_to_reg" },
2627        "Vpmulhrsw": { "feature": "AVX2", "opcodes": [ "C4", "02", "05", "0B" ], "type": "vex_rm_to_reg" },
2628        "Vpmulhw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "E5" ], "type": "optimizable_using_commutation" },
2629        "Vpmulld": { "feature": "AVX2", "opcodes": [ "C4", "02", "05", "40" ], "type": "vex_rm_to_reg" },
2630        "Vpmullw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "D5" ], "type": "optimizable_using_commutation" },
2631        "Vpmuludq": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "F4" ], "type": "optimizable_using_commutation" },
2632        "Vpor": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "EB" ], "type": "optimizable_using_commutation" },
2633        "Vpsadbw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "F6" ], "type": "optimizable_using_commutation" },
2634        "Vpshufb": { "feature": "AVX2", "opcodes": [ "C4", "02", "05", "00" ], "type": "vex_rm_to_reg" },
2635        "Vpsubb": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "F8" ], "type": "vex_rm_to_reg" },
2636        "Vpsubd": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "FA" ], "type": "vex_rm_to_reg" },
2637        "Vpsubq": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "FB" ], "type": "vex_rm_to_reg" },
2638        "Vpsubsb": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "E8" ], "type": "vex_rm_to_reg" },
2639        "Vpsubsw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "E9" ], "type": "vex_rm_to_reg" },
2640        "Vpsubusb": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "D8" ], "type": "vex_rm_to_reg" },
2641        "Vpsubusw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "D9" ], "type": "vex_rm_to_reg" },
2642        "Vpsubw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "F9" ], "type": "vex_rm_to_reg" },
2643        "Vpunpckhbw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "68" ], "type": "vex_rm_to_reg" },
2644        "Vpunpckhdq": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "6A" ], "type": "vex_rm_to_reg" },
2645        "Vpunpckhqdq": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "6D" ], "type": "vex_rm_to_reg" },
2646        "Vpunpckhwd": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "69" ], "type": "vex_rm_to_reg" },
2647        "Vpunpcklbw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "60" ], "type": "vex_rm_to_reg" },
2648        "Vpunpckldq": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "62" ], "type": "vex_rm_to_reg" },
2649        "Vpunpcklqdq": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "6C" ], "type": "vex_rm_to_reg" },
2650        "Vpunpcklwd": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "61" ], "type": "vex_rm_to_reg" },
2651        "Vpxor": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "EF" ], "type": "optimizable_using_commutation" },
2652        "Vsubpd": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "5C" ], "type": "vex_rm_to_reg" },
2653        "Vsubps": { "feature": "AVX2", "opcodes": [ "C4", "01", "04", "5C" ], "type": "vex_rm_to_reg" },
2654        "Vxorpd": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "57" ], "type": "optimizable_using_commutation" },
2655        "Vxorps": { "feature": "AVX2", "opcodes": [ "C4", "01", "04", "57" ], "type": "optimizable_using_commutation" }
2656      },
2657      "args": [
2658        { "class": "VecReg256", "usage": "def" },
2659        { "class": "VecReg256", "usage": "use" },
2660        { "class": "VecReg256/VecMem256", "usage": "use" }
2661      ]
2662    },
2663    {
2664      "encodings": {
2665        "Vaddsd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "58" ], "type": "optimizable_using_commutation" },
2666        "Vcmpeqsd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "C2", "00" ], "type": "optimizable_using_commutation" },
2667        "Vcmplesd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "C2", "02" ], "type": "vex_rm_to_reg" },
2668        "Vcmpltsd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "C2", "01" ], "type": "vex_rm_to_reg" },
2669        "Vcmpneqsd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "C2", "04" ], "type": "optimizable_using_commutation" },
2670        "Vcmpnlesd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "C2", "06" ], "type": "vex_rm_to_reg" },
2671        "Vcmpnltsd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "C2", "05" ], "type": "vex_rm_to_reg" },
2672        "Vcmpordsd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "C2", "07" ], "type": "optimizable_using_commutation" },
2673        "Vcmpunordsd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "C2", "03" ], "type": "optimizable_using_commutation" },
2674        "Vdivsd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "5E" ], "type": "vex_rm_to_reg" },
2675        "Vmulsd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "59" ], "type": "optimizable_using_commutation" },
2676        "Vsubsd": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "5C" ], "type": "vex_rm_to_reg" }
2677      },
2678      "args": [
2679        { "class": "FpReg64", "usage": "def" },
2680        { "class": "FpReg64", "usage": "use" },
2681        { "class": "FpReg64/VecMem64", "usage": "use" }
2682      ]
2683    },
2684    {
2685      "encodings": {
2686        "Vaddss": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "58" ], "type": "optimizable_using_commutation" },
2687        "Vcmpeqss": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "C2", "00" ], "type": "optimizable_using_commutation" },
2688        "Vcmpless": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "C2", "02" ], "type": "vex_rm_to_reg" },
2689        "Vcmpltss": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "C2", "01" ], "type": "vex_rm_to_reg" },
2690        "Vcmpneqss": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "C2", "04" ], "type": "optimizable_using_commutation" },
2691        "Vcmpnless": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "C2", "06" ], "type": "vex_rm_to_reg" },
2692        "Vcmpnltss": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "C2", "05" ], "type": "vex_rm_to_reg" },
2693        "Vcmpordss": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "C2", "07" ], "type": "optimizable_using_commutation" },
2694        "Vcmpunordss": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "C2", "03" ], "type": "optimizable_using_commutation" },
2695        "Vdivss": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "5E" ], "type": "vex_rm_to_reg" },
2696        "Vmulss": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "59" ], "type": "optimizable_using_commutation" },
2697        "Vsubss": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "5C" ], "type": "vex_rm_to_reg" }
2698      },
2699      "args": [
2700        { "class": "FpReg32", "usage": "def" },
2701        { "class": "FpReg32", "usage": "use" },
2702        { "class": "FpReg32/VecMem32", "usage": "use" }
2703      ]
2704    },
2705    {
2706      "encodings": {
2707        "Vcvtsd2ss": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "5A" ], "type": "vex_rm_to_reg" }
2708      },
2709      "args": [
2710        { "class": "FpReg32", "usage": "def" },
2711        { "class": "XmmReg", "usage": "use" },
2712        { "class": "FpReg64/VecMem64", "usage": "use" }
2713      ]
2714    },
2715    {
2716      "encodings": {
2717        "Vcvtsi2sdl": { "feature": "AVX", "opcodes": [ "C4", "01", "03", "2A" ], "type": "vex_rm_to_reg" }
2718      },
2719      "args": [
2720        { "class": "FpReg64", "usage": "def" },
2721        { "class": "XmmReg", "usage": "use" },
2722        { "class": "GeneralReg32/Mem32", "usage": "use" }
2723      ]
2724    },
2725    {
2726      "encodings": {
2727        "Vcvtsi2ssl": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "2A" ], "type": "vex_rm_to_reg" }
2728      },
2729      "args": [
2730        { "class": "FpReg32", "usage": "def" },
2731        { "class": "XmmReg", "usage": "use" },
2732        { "class": "GeneralReg32/Mem32", "usage": "use" }
2733      ]
2734    },
2735    {
2736      "encodings": {
2737        "Vcvtss2sd": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "5A" ], "type": "vex_rm_to_reg" }
2738      },
2739      "args": [
2740        { "class": "FpReg64", "usage": "def" },
2741        { "class": "XmmReg", "usage": "use" },
2742        { "class": "FpReg32/VecMem32", "usage": "use" }
2743      ]
2744    },
2745    {
2746      "encodings": {
2747        "Vfmadd132pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "98" ], "type": "vex_rm_to_reg" },
2748        "Vfmadd132ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "98" ], "type": "vex_rm_to_reg" },
2749        "Vfmadd213pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "A8" ], "type": "vex_rm_to_reg" },
2750        "Vfmadd213ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "A8" ], "type": "vex_rm_to_reg" },
2751        "Vfmadd231pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "B8" ], "type": "vex_rm_to_reg" },
2752        "Vfmadd231ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "B8" ], "type": "vex_rm_to_reg" },
2753        "Vfmaddsub132pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "96" ], "type": "vex_rm_to_reg" },
2754        "Vfmaddsub132ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "96" ], "type": "vex_rm_to_reg" },
2755        "Vfmaddsub213pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "A6" ], "type": "vex_rm_to_reg" },
2756        "Vfmaddsub213ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "A6" ], "type": "vex_rm_to_reg" },
2757        "Vfmaddsub231pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "B6" ], "type": "vex_rm_to_reg" },
2758        "Vfmaddsub231ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "B6" ], "type": "vex_rm_to_reg" },
2759        "Vfmsub132pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "9A" ], "type": "vex_rm_to_reg" },
2760        "Vfmsub132ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "9A" ], "type": "vex_rm_to_reg" },
2761        "Vfmsub213pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "AA" ], "type": "vex_rm_to_reg" },
2762        "Vfmsub213ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "AA" ], "type": "vex_rm_to_reg" },
2763        "Vfmsub231pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "BA" ], "type": "vex_rm_to_reg" },
2764        "Vfmsub231ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "BA" ], "type": "vex_rm_to_reg" },
2765        "Vfmsubadd132pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "97" ], "type": "vex_rm_to_reg" },
2766        "Vfmsubadd132ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "97" ], "type": "vex_rm_to_reg" },
2767        "Vfmsubadd213pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "A7" ], "type": "vex_rm_to_reg" },
2768        "Vfmsubadd213ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "A7" ], "type": "vex_rm_to_reg" },
2769        "Vfmsubadd231pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "B7" ], "type": "vex_rm_to_reg" },
2770        "Vfmsubadd231ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "B7" ], "type": "vex_rm_to_reg" },
2771        "Vfnmadd132pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "9C" ], "type": "vex_rm_to_reg" },
2772        "Vfnmadd132ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "9C" ], "type": "vex_rm_to_reg" },
2773        "Vfnmadd213pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "AC" ], "type": "vex_rm_to_reg" },
2774        "Vfnmadd213ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "AC" ], "type": "vex_rm_to_reg" },
2775        "Vfnmadd231pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "BC" ], "type": "vex_rm_to_reg" },
2776        "Vfnmadd231ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "BC" ], "type": "vex_rm_to_reg" },
2777        "Vfnmsub132pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "9E" ], "type": "vex_rm_to_reg" },
2778        "Vfnmsub132ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "9E" ], "type": "vex_rm_to_reg" },
2779        "Vfnmsub213pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "AE" ], "type": "vex_rm_to_reg" },
2780        "Vfnmsub213ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "AE" ], "type": "vex_rm_to_reg" },
2781        "Vfnmsub231pd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "BE" ], "type": "vex_rm_to_reg" },
2782        "Vfnmsub231ps": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "BE" ], "type": "vex_rm_to_reg" }
2783      },
2784      "args": [
2785        { "class": "VecReg128", "usage": "use_def" },
2786        { "class": "VecReg128", "usage": "use" },
2787        { "class": "VecReg128/VecMem128", "usage": "use" }
2788      ]
2789    },
2790    {
2791      "encodings": {
2792        "Vfmadd132sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "99" ], "type": "vex_rm_to_reg" },
2793        "Vfmadd213sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "A9" ], "type": "vex_rm_to_reg" },
2794        "Vfmadd231sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "B9" ], "type": "vex_rm_to_reg" },
2795        "Vfmsub132sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "9B" ], "type": "vex_rm_to_reg" },
2796        "Vfmsub213sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "AB" ], "type": "vex_rm_to_reg" },
2797        "Vfmsub231sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "BB" ], "type": "vex_rm_to_reg" },
2798        "Vfnmadd132sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "9D" ], "type": "vex_rm_to_reg" },
2799        "Vfnmadd213sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "AD" ], "type": "vex_rm_to_reg" },
2800        "Vfnmadd231sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "BD" ], "type": "vex_rm_to_reg" },
2801        "Vfnmsub132sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "9F" ], "type": "vex_rm_to_reg" },
2802        "Vfnmsub213sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "AF" ], "type": "vex_rm_to_reg" },
2803        "Vfnmsub231sd": { "feature": "FMA", "opcodes": [ "C4", "02", "81", "BF" ], "type": "vex_rm_to_reg" }
2804      },
2805      "args": [
2806        { "class": "XmmReg", "usage": "use_def" },
2807        { "class": "XmmReg", "usage": "use" },
2808        { "class": "XmmReg/VecMem64", "usage": "use" }
2809      ]
2810    },
2811    {
2812      "encodings": {
2813        "Vfmadd132ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "99" ], "type": "vex_rm_to_reg" },
2814        "Vfmadd213ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "A9" ], "type": "vex_rm_to_reg" },
2815        "Vfmadd231ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "B9" ], "type": "vex_rm_to_reg" },
2816        "Vfmsub132ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "9B" ], "type": "vex_rm_to_reg" },
2817        "Vfmsub213ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "AB" ], "type": "vex_rm_to_reg" },
2818        "Vfmsub231ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "BB" ], "type": "vex_rm_to_reg" },
2819        "Vfnmadd132ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "9D" ], "type": "vex_rm_to_reg" },
2820        "Vfnmadd213ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "AD" ], "type": "vex_rm_to_reg" },
2821        "Vfnmadd231ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "BD" ], "type": "vex_rm_to_reg" },
2822        "Vfnmsub132ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "9F" ], "type": "vex_rm_to_reg" },
2823        "Vfnmsub213ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "AF" ], "type": "vex_rm_to_reg" },
2824        "Vfnmsub231ss": { "feature": "FMA", "opcodes": [ "C4", "02", "01", "BF" ], "type": "vex_rm_to_reg" }
2825      },
2826      "args": [
2827        { "class": "XmmReg", "usage": "use_def" },
2828        { "class": "XmmReg", "usage": "use" },
2829        { "class": "XmmReg/VecMem32", "usage": "use" }
2830      ]
2831    },
2832    {
2833      "encodings": {
2834        "Vfmaddpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "69" ], "type": "vex_rm_imm_to_reg" },
2835        "Vfmaddps": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "68" ], "type": "vex_rm_imm_to_reg" },
2836        "Vfmaddsubpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "5D" ], "type": "vex_rm_imm_to_reg" },
2837        "Vfmaddsubps": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "5C" ], "type": "vex_rm_imm_to_reg" },
2838        "Vfmsubaddpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "5F" ], "type": "vex_rm_imm_to_reg" },
2839        "Vfmsubaddps": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "5E" ], "type": "vex_rm_imm_to_reg" },
2840        "Vfmsubpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "6D" ], "type": "vex_rm_imm_to_reg" },
2841        "Vfmsubps": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "6C" ], "type": "vex_rm_imm_to_reg" },
2842        "Vfnmaddpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "79" ], "type": "vex_rm_imm_to_reg" },
2843        "Vfnmaddps": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "78" ], "type": "vex_rm_imm_to_reg" },
2844        "Vfnmsubpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "7D" ], "type": "vex_rm_imm_to_reg" },
2845        "Vfnmsubps": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "7C" ], "type": "vex_rm_imm_to_reg" }
2846      },
2847      "args": [
2848        { "class": "VecReg128", "usage": "def" },
2849        { "class": "VecReg128", "usage": "use" },
2850        { "class": "VecMem128", "usage": "use" },
2851        { "class": "VecReg128", "usage": "use" }
2852      ]
2853    },
2854    {
2855      "encodings": {
2856        "Vfmaddpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "69" ], "type": "vex_imm_rm_to_reg" },
2857        "Vfmaddps": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "68" ], "type": "vex_imm_rm_to_reg" },
2858        "Vfmaddsubpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "5D" ], "type": "vex_imm_rm_to_reg" },
2859        "Vfmaddsubps": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "5C" ], "type": "vex_imm_rm_to_reg" },
2860        "Vfmsubaddpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "5F" ], "type": "vex_imm_rm_to_reg" },
2861        "Vfmsubaddps": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "5E" ], "type": "vex_imm_rm_to_reg" },
2862        "Vfmsubpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "6D" ], "type": "vex_imm_rm_to_reg" },
2863        "Vfmsubps": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "6C" ], "type": "vex_imm_rm_to_reg" },
2864        "Vfnmaddpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "79" ], "type": "vex_imm_rm_to_reg" },
2865        "Vfnmaddps": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "78" ], "type": "vex_imm_rm_to_reg" },
2866        "Vfnmsubpd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "7D" ], "type": "vex_imm_rm_to_reg" },
2867        "Vfnmsubps": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "7C" ], "type": "vex_imm_rm_to_reg" }
2868      },
2869      "args": [
2870        { "class": "VecReg128", "usage": "def" },
2871        { "class": "VecReg128", "usage": "use" },
2872        { "class": "VecReg128", "usage": "use" },
2873        { "class": "VecReg128/VecMem128", "usage": "use" }
2874      ]
2875    },
2876    {
2877      "encodings": {
2878        "Vfmaddsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "6B" ], "type": "vex_rm_imm_to_reg" },
2879        "Vfmsubsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "6F" ], "type": "vex_rm_imm_to_reg" },
2880        "Vfnmaddsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "7B" ], "type": "vex_rm_imm_to_reg" },
2881        "Vfnmsubsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "7F" ], "type": "vex_rm_imm_to_reg" }
2882      },
2883      "args": [
2884        { "class": "XmmReg", "usage": "def" },
2885        { "class": "XmmReg", "usage": "use" },
2886        { "class": "VecMem64", "usage": "use" },
2887        { "class": "XmmReg", "usage": "use" }
2888      ]
2889    },
2890    {
2891      "encodings": {
2892        "Vfmaddsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "6B" ], "type": "vex_imm_rm_to_reg" },
2893        "Vfmsubsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "6F" ], "type": "vex_imm_rm_to_reg" },
2894        "Vfnmaddsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "7B" ], "type": "vex_imm_rm_to_reg" },
2895        "Vfnmsubsd": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "7F" ], "type": "vex_imm_rm_to_reg" }
2896      },
2897      "args": [
2898        { "class": "XmmReg", "usage": "def" },
2899        { "class": "XmmReg", "usage": "use" },
2900        { "class": "XmmReg", "usage": "use" },
2901        { "class": "XmmReg/VecMem64", "usage": "use" }
2902      ]
2903    },
2904    {
2905      "encodings": {
2906        "Vfmaddss": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "6A" ], "type": "vex_rm_imm_to_reg" },
2907        "Vfmsubss": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "6E" ], "type": "vex_rm_imm_to_reg" },
2908        "Vfnmaddss": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "7A" ], "type": "vex_rm_imm_to_reg" },
2909        "Vfnmsubss": { "feature": "FMA4", "opcodes": [ "C4", "03", "01", "7E" ], "type": "vex_rm_imm_to_reg" }
2910      },
2911      "args": [
2912        { "class": "XmmReg", "usage": "def" },
2913        { "class": "XmmReg", "usage": "use" },
2914        { "class": "VecMem32", "usage": "use" },
2915        { "class": "XmmReg", "usage": "use" }
2916      ]
2917    },
2918    {
2919      "encodings": {
2920        "Vfmaddss": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "6A" ], "type": "vex_imm_rm_to_reg" },
2921        "Vfmsubss": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "6E" ], "type": "vex_imm_rm_to_reg" },
2922        "Vfnmaddss": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "7A" ], "type": "vex_imm_rm_to_reg" },
2923        "Vfnmsubss": { "feature": "FMA4", "opcodes": [ "C4", "03", "81", "7E" ], "type": "vex_imm_rm_to_reg" }
2924      },
2925      "args": [
2926        { "class": "XmmReg", "usage": "def" },
2927        { "class": "XmmReg", "usage": "use" },
2928        { "class": "XmmReg", "usage": "use" },
2929        { "class": "XmmReg/VecMem32", "usage": "use" }
2930      ]
2931    },
2932    {
2933      "encodings": {
2934        "Vmovapd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "28" ] },
2935        "Vmovaps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "28" ] }
2936      },
2937      "args": [
2938        { "class": "XmmReg", "usage": "def" },
2939        { "class": "VecMem128", "usage": "use" }
2940      ]
2941    },
2942    {
2943      "encodings": {
2944        "Vmovdqa": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "6F" ] },
2945        "Vmovdqu": { "feature": "AVX", "opcodes": [ "C4", "01", "02", "6F" ] }
2946      },
2947      "args": [
2948        { "class": "XmmReg", "usage": "def" },
2949        { "class": "VecMem128", "usage": "use" }
2950      ]
2951    },
2952    {
2953      "encodings": {
2954        "Vmovhlps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "12" ], "type": "vex_rm_to_reg" },
2955        "Vmovlhps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "16" ], "type": "vex_rm_to_reg" }
2956      },
2957      "args": [
2958        { "class": "XmmReg", "usage": "def" },
2959        { "class": "XmmReg", "usage": "use" },
2960        { "class": "XmmReg", "usage": "use" }
2961      ]
2962    },
2963    {
2964      "encodings": {
2965        "Vmovhpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "16" ] },
2966        "Vmovhps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "16" ] },
2967        "Vmovlpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "12" ] },
2968        "Vmovlps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "12" ] }
2969      },
2970      "args": [
2971        { "class": "XmmReg", "usage": "def" },
2972        { "class": "XmmReg", "usage": "use" },
2973        { "class": "VecMem64", "usage": "use" }
2974      ]
2975    },
2976    {
2977      "encodings": {
2978        "Vpermil2pd": { "feature": "AVX", "opcodes": [ "C4", "03", "81", "49" ], "type": "vex_imm_rm_to_reg" },
2979        "Vpermil2ps": { "feature": "AVX", "opcodes": [ "C4", "03", "81", "48" ], "type": "vex_imm_rm_to_reg" }
2980      },
2981      "args": [
2982        { "class": "VecReg128", "usage": "def" },
2983        { "class": "VecReg128", "usage": "use" },
2984        { "class": "VecReg128", "usage": "use" },
2985        { "class": "VecMem128", "usage": "use" },
2986        { "class": "Imm2" }
2987      ]
2988    },
2989    {
2990      "encodings": {
2991        "Vpermil2pd": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "49" ], "type": "vex_rm_imm_to_reg" },
2992        "Vpermil2ps": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "48" ], "type": "vex_rm_imm_to_reg" }
2993      },
2994      "args": [
2995        { "class": "VecReg128", "usage": "def" },
2996        { "class": "VecReg128", "usage": "use" },
2997        { "class": "VecReg128/VecMem128", "usage": "use" },
2998        { "class": "VecReg128", "usage": "use" },
2999        { "class": "Imm2" }
3000      ]
3001    },
3002    {
3003      "encodings": {
3004        "Vpinsrb": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "20" ], "type": "vex_rm_to_reg" },
3005        "Vpinsrd": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "22" ], "type": "vex_rm_to_reg" },
3006        "Vpinsrw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C4" ], "type": "vex_rm_to_reg" }
3007      },
3008      "args": [
3009        { "class": "VecReg128", "usage": "use_def" },
3010        { "class": "VecReg128", "usage": "use" },
3011        { "class": "GeneralReg32", "usage": "use" },
3012        { "class": "Imm8" }
3013      ]
3014    },
3015    {
3016      "encodings": {
3017        "Vpslld": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "72", "6" ], "type": "rm_to_vex" },
3018        "Vpslldq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "73", "7" ], "type": "rm_to_vex" },
3019        "Vpsllq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "73", "6" ], "type": "rm_to_vex" },
3020        "Vpsllw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "71", "6" ], "type": "rm_to_vex" },
3021        "Vpsrad": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "72", "4" ], "type": "rm_to_vex" },
3022        "Vpsraw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "71", "4" ], "type": "rm_to_vex" },
3023        "Vpsrld": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "72", "2" ], "type": "rm_to_vex" },
3024        "Vpsrldq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "73", "3" ], "type": "rm_to_vex" },
3025        "Vpsrlq": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "73", "2" ], "type": "rm_to_vex" },
3026        "Vpsrlw": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "71", "2" ], "type": "rm_to_vex" }
3027      },
3028      "args": [
3029        { "class": "VecReg128", "usage": "def" },
3030        { "class": "VecReg128", "usage": "use" },
3031        { "class": "Imm8" }
3032      ]
3033    },
3034    {
3035      "encodings": {
3036        "Vpslld": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "F2" ], "type": "vex_rm_to_reg" },
3037        "Vpsllq": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "F3" ], "type": "vex_rm_to_reg" },
3038        "Vpsllw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "F1" ], "type": "vex_rm_to_reg" },
3039        "Vpsrad": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "E2" ], "type": "vex_rm_to_reg" },
3040        "Vpsraw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "E1" ], "type": "vex_rm_to_reg" },
3041        "Vpsrld": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "D2" ], "type": "vex_rm_to_reg" },
3042        "Vpsrlq": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "D3" ], "type": "vex_rm_to_reg" },
3043        "Vpsrlw": { "feature": "AVX2", "opcodes": [ "C4", "01", "05", "D1" ], "type": "vex_rm_to_reg" }
3044      },
3045      "args": [
3046        { "class": "VecReg256", "usage": "def" },
3047        { "class": "VecReg256", "usage": "use" },
3048        { "class": "VecReg128/VecMem128", "usage": "use" }
3049      ]
3050    },
3051    {
3052      "encodings": {
3053        "Vroundsd": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "0B" ], "type": "vex_rm_to_reg" }
3054      },
3055      "args": [
3056        { "class": "FpReg64", "usage": "def" },
3057        { "class": "XmmReg", "usage": "use" },
3058        { "class": "FpReg64/VecMem64", "usage": "use" },
3059        { "class": "Imm8" }
3060      ]
3061    },
3062    {
3063      "encodings": {
3064        "Vroundss": { "feature": "AVX", "opcodes": [ "C4", "03", "01", "0A" ], "type": "vex_rm_to_reg" }
3065      },
3066      "args": [
3067        { "class": "FpReg32", "usage": "def" },
3068        { "class": "XmmReg", "usage": "use" },
3069        { "class": "FpReg32/VecMem32", "usage": "use" },
3070        { "class": "Imm8" }
3071      ]
3072    },
3073    {
3074      "encodings": {
3075        "Vshufpd": { "feature": "AVX", "opcodes": [ "C4", "01", "01", "C6" ], "type": "vex_rm_to_reg" },
3076        "Vshufps": { "feature": "AVX", "opcodes": [ "C4", "01", "00", "C6" ], "type": "vex_rm_to_reg" }
3077      },
3078      "args": [
3079        { "class": "VecReg128", "usage": "def" },
3080        { "class": "VecReg128", "usage": "use" },
3081        { "class": "VecReg128/VecMem128", "usage": "use" },
3082        { "class": "Imm8" }
3083      ]
3084    },
3085    {
3086      "encodings": {
3087        "Xchgb": { "opcode": "86" }
3088      },
3089      "args": [
3090        { "class": "GeneralReg8", "usage": "use_def" },
3091        { "class": "Mem8", "usage": "use_def" }
3092      ]
3093    },
3094    {
3095      "stems": [ "Xchgl" ],
3096      "args": [
3097        { "class": "GeneralReg32", "usage": "use_def" },
3098        { "class": "GeneralReg32", "usage": "use_def" }
3099      ]
3100    },
3101    {
3102      "encodings": {
3103        "Xchgl": { "opcode": "87" }
3104      },
3105      "args": [
3106        { "class": "GeneralReg32", "usage": "use_def" },
3107        { "class": "Mem32", "usage": "use_def" }
3108      ]
3109    },
3110    {
3111      "encodings": {
3112        "Xchgw": { "opcodes": [ "66", "87" ] }
3113      },
3114      "args": [
3115        { "class": "GeneralReg16", "usage": "use_def" },
3116        { "class": "Mem16", "usage": "use_def" }
3117      ]
3118    }
3119  ]
3120}
3121