Searched defs:Divw (Results 1 – 4 of 4) sorted by relevance
| /aosp_15_r20/art/compiler/optimizing/ |
| H A D | code_generator_riscv64.cc | 1521 __ Divw(out, dividend, tmp); in GenerateDivRemWithAnyConstant() local
1560 __ Divw(out, dividend, divisor); in GenerateDivRemIntegral() local
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| /aosp_15_r20/art/compiler/utils/riscv64/ |
| H A D | assembler_riscv64_test.cc | 2930 TEST_F(AssemblerRISCV64Test, Divw) { in TEST_F() argument
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| H A D | assembler_riscv64.cc | 707 void Riscv64Assembler::Divw(XRegister rd, XRegister rs1, XRegister rs2) { in Divw() function in art::riscv64::Riscv64Assembler
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| /aosp_15_r20/frameworks/libs/binary_translation/assembler/instructions/ |
| D | insn_def_x86.json | 1029 "Divw": { "opcodes": [ "66", "F7", "6" ] }, object
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