1 /* SPDX-License-Identifier: BSD-3-Clause */
2
3 //-----------------------------------------------------------------------------
4 // Include files
5 //-----------------------------------------------------------------------------
6 #include "dramc_common.h"
7 #include "dramc_int_global.h"
8 #include "x_hal_io.h"
9 #if (FOR_DV_SIMULATION_USED == 0)
10 #include "dramc_top.h"
11 #endif
12
13 //-----------------------------------------------------------------------------
14 // Global variables
15 //-----------------------------------------------------------------------------
16
17 //U8 gu1MR23Done = FALSE;
18 U8 gu1MR23[CHANNEL_NUM][RANK_MAX];
19
20 U16 gu2DQSOSCTHRD_INC[CHANNEL_NUM][RANK_MAX];
21 U16 gu2DQSOSCTHRD_DEC[CHANNEL_NUM][RANK_MAX];
22 U16 gu2MR18[CHANNEL_NUM][RANK_MAX];
23 U16 gu2MR19[CHANNEL_NUM][RANK_MAX];
24 U16 gu2DQSOSC[CHANNEL_NUM][RANK_MAX];
25 U16 gu2DQSOscCnt[CHANNEL_NUM][RANK_MAX][2];
26
27
DramcDQSOSCInit(void)28 void DramcDQSOSCInit(void)
29 {
30 memset(gu1MR23, 0x3F, sizeof(gu1MR23));
31 memset(gu2DQSOSCTHRD_INC, 0x6, sizeof(gu2DQSOSCTHRD_INC));
32 memset(gu2DQSOSCTHRD_DEC, 0x4, sizeof(gu2DQSOSCTHRD_DEC));
33 }
34
35 #if DQSOSC_SCSM
DramcStartDQSOSC_SCSM(DRAMC_CTX_T * p)36 static DRAM_STATUS_T DramcStartDQSOSC_SCSM(DRAMC_CTX_T *p)
37 {
38 U32 u4Response;
39 U32 u4TimeCnt;
40 U32 u4MRSRKBak;
41
42 u4TimeCnt = TIME_OUT_CNT;
43 mcSHOW_DBG_MSG2(("[DQSOSC]\n"));
44
45 u4MRSRKBak = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), SWCMD_CTRL0_MRSRK);
46
47
48 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0, DQSOSCR_DQSOSC2RK);
49 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u1GetRank(p), SWCMD_CTRL0_MRSRK);
50 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_OPTION), 1, MPC_OPTION_MPCRKEN);
51
52
53 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_DQSOSCENEN);
54
55 do
56 {
57 u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_DQSOSCEN_RESPONSE);
58 u4TimeCnt --;
59 mcDELAY_US(1);
60 } while ((u4Response == 0) && (u4TimeCnt > 0));
61
62 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_DQSOSCENEN);
63
64 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), u4MRSRKBak, SWCMD_CTRL0_MRSRK);
65
66 if (u4TimeCnt == 0)
67 {
68 mcSHOW_ERR_MSG(("Start fail (time out)\n"));
69 return DRAM_FAIL;
70 }
71
72 return DRAM_OK;
73 }
74 #endif
75
76 #if DQSOSC_RTSWCMD
DramcStartDQSOSC_RTSWCMD(DRAMC_CTX_T * p)77 static DRAM_STATUS_T DramcStartDQSOSC_RTSWCMD(DRAMC_CTX_T *p)
78 {
79 U32 u4Response, u4TimeCnt;
80
81 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2),
82 P_Fld(0, SWCMD_CTRL2_RTSWCMD_AGE) |
83 P_Fld(u1GetRank(p), SWCMD_CTRL2_RTSWCMD_RK));
84 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL),
85 1, MPC_CTRL_RTSWCMD_HPRI_EN);
86 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT),
87 0x2a, RTSWCMD_CNT_RTSWCMD_CNT);
88 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
89 2, SWCMD_EN_RTSWCMD_SEL);
90 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
91 1, SWCMD_EN_RTSWCMDEN);
92
93 u4TimeCnt = TIME_OUT_CNT;
94
95 do {
96 u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3),
97 SPCMDRESP3_RTSWCMD_RESPONSE);
98 u4TimeCnt--;
99 mcDELAY_US(5);
100 } while ((u4Response == 0) && (u4TimeCnt > 0));
101
102 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
103 0, SWCMD_EN_RTSWCMDEN);
104 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL),
105 0, MPC_CTRL_RTSWCMD_HPRI_EN);
106
107 if (u4TimeCnt == 0)
108 {
109 mcSHOW_ERR_MSG(("[LP5 RT SW Cmd MRW ] Resp fail (time out)\n"));
110 return DRAM_FAIL;
111 }
112
113 return DRAM_OK;
114 }
115 #endif
116
117 #if DQSOSC_SWCMD
DramcStartDQSOSC_SWCMD(DRAMC_CTX_T * p)118 static DRAM_STATUS_T DramcStartDQSOSC_SWCMD(DRAMC_CTX_T *p)
119 {
120 U32 u4Response;
121 U32 u4TimeCnt = TIME_OUT_CNT;
122 U32 u4RegBackupAddress[] = {DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), DRAMC_REG_ADDR(DRAMC_REG_CKECTRL)};
123
124
125 DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
126
127 mcSHOW_DBG_MSG4(("[ZQCalibration]\n"));
128 //mcFPRINTF((fp_A60501, "[ZQCalibration]\n"));
129
130
131 DramCLKAlwaysOnOff(p, ON, TO_ONE_CHANNEL);
132 mcDELAY_US(1);
133
134
135 CKEFixOnOff(p, TO_ALL_RANK, CKE_FIXON, TO_ONE_CHANNEL);
136
137
138 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_WCK2DQI_START_SWTRIG);
139
140 do
141 {
142 u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3), SPCMDRESP3_WCK2DQI_START_SWTRIG_RESPONSE);
143 u4TimeCnt --;
144 mcDELAY_US(1);
145
146 mcSHOW_DBG_MSG4(("%d- ", u4TimeCnt));
147 //mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt));
148 }while((u4Response==0) &&(u4TimeCnt>0));
149
150 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_WCK2DQI_START_SWTRIG);
151
152 if(u4TimeCnt==0)//time out
153 {
154 mcSHOW_ERR_MSG(("ZQCAL Start fail (time out)\n"));
155 //mcFPRINTF((fp_A60501, "ZQCAL Start fail (time out)\n"));
156 return DRAM_FAIL;
157 }
158
159
160 DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
161
162 mcSHOW_DBG_MSG4(("\n[DramcZQCalibration] Done\n\n"));
163 //mcFPRINTF((fp_A60501, "\n[DramcZQCalibration] Done\n\n"));
164
165 return DRAM_OK;
166 }
167 #endif
168
DramcStartDQSOSC(DRAMC_CTX_T * p)169 static DRAM_STATUS_T DramcStartDQSOSC(DRAMC_CTX_T *p)
170 {
171 #if DQSOSC_SCSM
172 return DramcStartDQSOSC_SCSM(p);
173 #elif DQSOSC_RTSWCMD
174 return DramcStartDQSOSC_RTSWCMD(p);
175 #else
176 return DramcStartDQSOSC_SWCMD(p);
177 #endif
178 }
179
DramcDQSOSCAuto(DRAMC_CTX_T * p)180 DRAM_STATUS_T DramcDQSOSCAuto(DRAMC_CTX_T *p)
181 {
182 U8 u1MR23 = gu1MR23[p->channel][p->rank];
183 U16 u2MR18, u2MR19;
184 U16 u2DQSCnt;
185 U16 u2DQSOsc[2];
186 U32 u4RegBak[2];
187
188 #if MRW_CHECK_ONLY
189 mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
190 #endif
191
192 u4RegBak[0] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL));
193 u4RegBak[1] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL));
194
195
196 //vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRS), u1GetRank(p), MRS_MRSRK);
197 DramcModeRegWriteByRank(p, p->rank, 23, u1MR23);
198
199
200 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), 1, SHU_DQSOSC_SET0_DQSOSCENDIS);
201
202
203 DramCLKAlwaysOnOff(p, ON, TO_ONE_CHANNEL);
204
205 CKEFixOnOff(p, p->rank, CKE_FIXON, TO_ONE_CHANNEL);
206
207 DramcStartDQSOSC(p);
208 mcDELAY_US(1);
209
210 DramcModeRegReadByRank(p, p->rank, 18, &u2MR18);
211 DramcModeRegReadByRank(p, p->rank, 19, &u2MR19);
212
213 #if (SW_CHANGE_FOR_SIMULATION == 0)
214
215 u2DQSCnt = (u2MR18 & 0x00FF) | ((u2MR19 & 0x00FF) << 8);
216 if (u2DQSCnt != 0)
217 u2DQSOsc[0] = u1MR23 * 16 * 1000000 / (2 * u2DQSCnt * DDRPhyGetRealFreq(p));
218 else
219 u2DQSOsc[0] = 0;
220
221
222 u2DQSCnt = (u2MR18 >> 8) | ((u2MR19 & 0xFF00));
223 if (u2DQSCnt != 0)
224 u2DQSOsc[1] = u1MR23 * 16 * 1000000 / (2 * u2DQSCnt * DDRPhyGetRealFreq(p));
225 else
226 u2DQSOsc[1] = 0;
227 mcSHOW_DBG_MSG2(("[DQSOSCAuto] RK%d, (LSB)MR18= 0x%x, (MSB)MR19= 0x%x, tDQSOscB0 = %d ps tDQSOscB1 = %d ps\n", u1GetRank(p), u2MR18, u2MR19, u2DQSOsc[0], u2DQSOsc[1]));
228 #endif
229
230 gu2MR18[p->channel][p->rank] = u2MR18;
231 gu2MR19[p->channel][p->rank] = u2MR19;
232 gu2DQSOSC[p->channel][p->rank] = u2DQSOsc[0];
233
234 if (u2DQSOsc[1] != 0 && u2DQSOsc[1] < u2DQSOsc[0])
235 gu2DQSOSC[p->channel][p->rank] = u2DQSOsc[1];
236
237 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), u4RegBak[0]);
238 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4RegBak[1]);
239
240 return DRAM_OK;
241 }
242
243
244 #if ENABLE_TX_TRACKING
245
DramcDQSOSCMR23(DRAMC_CTX_T * p)246 DRAM_STATUS_T DramcDQSOSCMR23(DRAMC_CTX_T *p)
247 {
248 #if (SW_CHANGE_FOR_SIMULATION == 0)
249
250 U8 u1MR23 = gu1MR23[p->channel][p->rank];
251 U16 u2DQSOSC = gu2DQSOSC[p->channel][p->rank];
252 U32 u4tCK = 1000000 / DDRPhyGetRealFreq(p);
253
254 if (u2DQSOSC != 0)
255 {
256 gu2DQSOSCTHRD_INC[p->channel][p->rank] = (3 * u1MR23 * u4tCK * u4tCK) / (u2DQSOSC * u2DQSOSC * 20);
257 gu2DQSOSCTHRD_DEC[p->channel][p->rank] = (u1MR23 * u4tCK * u4tCK) / (u2DQSOSC * u2DQSOSC * 10);
258 }
259
260 mcSHOW_DBG_MSG2(("CH%d_RK%d: MR19=0x%X, MR18=0x%X, DQSOSC=%d, MR23=%u, INC=%u, DEC=%u\n", p->channel, p->rank,
261 gu2MR19[p->channel][p->rank], gu2MR18[p->channel][p->rank], gu2DQSOSC[p->channel][p->rank],
262 u1MR23, gu2DQSOSCTHRD_INC[p->channel][p->rank], gu2DQSOSCTHRD_DEC[p->channel][p->rank]));
263 #endif
264 return DRAM_OK;
265 }
266
267
268
DramcDQSOSCSetMR18MR19(DRAMC_CTX_T * p)269 DRAM_STATUS_T DramcDQSOSCSetMR18MR19(DRAMC_CTX_T *p)
270 {
271 U16 u2DQSOscCnt[2];
272
273 DramcDQSOSCAuto(p);
274
275
276 gu2DQSOscCnt[p->channel][p->rank][0] = u2DQSOscCnt[0] = (gu2MR18[p->channel][p->rank] & 0x00FF) | ((gu2MR19[p->channel][p->rank] & 0x00FF) << 8);
277
278 gu2DQSOscCnt[p->channel][p->rank][1] = u2DQSOscCnt[1] = (gu2MR18[p->channel][p->rank] >> 8) | ((gu2MR19[p->channel][p->rank] & 0xFF00));
279
280 if ((p->dram_cbt_mode[p->rank] == CBT_NORMAL_MODE) && (gu2DQSOscCnt[p->channel][p->rank][1] == 0))
281 {
282 gu2DQSOscCnt[p->channel][p->rank][1] = u2DQSOscCnt[1] = u2DQSOscCnt[0];
283 }
284
285 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC), P_Fld(u2DQSOscCnt[0], SHURK_DQSOSC_DQSOSC_BASE_RK0) | P_Fld(u2DQSOscCnt[1], SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
286
287 mcSHOW_DBG_MSG2(("CH%d RK%d: MR19=%X, MR18=%X\n", p->channel, p->rank, gu2MR19[p->channel][p->rank], gu2MR18[p->channel][p->rank]));
288 //mcDUMP_REG_MSG(("CH%d RK%d: MR19=%X, MR18=%X\n", p->channel, p->rank, gu2MR19[p->channel][p->rank], gu2MR18[p->channel][p->rank]));
289 return DRAM_OK;
290 }
291
DramcDQSOSCShuSettings(DRAMC_CTX_T * p)292 DRAM_STATUS_T DramcDQSOSCShuSettings(DRAMC_CTX_T *p)
293 {
294 U16 u2PRDCNT = 0x3FF, u2PRDCNTtmp = 0x3FF;
295 U8 u1PRDCNT_DIV = 4;
296 U16 u2DQSOSCENCNT = 0xFFF;
297 U8 u1FILT_PITHRD = 0;
298 U8 u1W2R_SEL = 0;
299 U8 u1RankIdx, u1RankIdxBak;
300 U8 u1DQSOSCRCNT = 0, u1IsDiv4 = 0, u1RoundUp= 0;
301
302 u1RankIdxBak = u1GetRank(p);
303
304 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), 0x0, SHU_TX_SET0_DQS2DQ_FILT_PITHRD);
305 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0x0, DQSOSCR_R_DMDQS2DQ_FILT_OPT);
306 if (p->frequency <= 400)
307 {
308 u1FILT_PITHRD = 0x5;
309 if (vGet_Div_Mode(p) == DIV4_MODE)
310 u1W2R_SEL = 0x2;
311 else
312 u1W2R_SEL = 0x5;
313 }
314 else if (p->frequency <= 600)
315 {
316 u1FILT_PITHRD = 0x6;
317 if (vGet_Div_Mode(p) == DIV4_MODE)
318 u1W2R_SEL = 0x2;
319 else
320 u1W2R_SEL = 0x5;
321 }
322 else if (p->frequency <= 800)
323 {
324 u1FILT_PITHRD = 0x6;
325 if (vGet_Div_Mode(p) == DIV4_MODE)
326 u1W2R_SEL = 0x2;
327 else
328 u1W2R_SEL = 0x5;
329 }
330 else if (p->frequency <= 933)
331 {
332 u1FILT_PITHRD = 0x9;
333 u1W2R_SEL = 0x2;
334 }
335 else if (p->frequency <= 1200)
336 {
337 u1FILT_PITHRD = 0xb;
338 u1W2R_SEL = 0x2;
339 }
340 else if (p->frequency <= 1333)
341 {
342 u1FILT_PITHRD = 0xc;
343 u1W2R_SEL = 0x2;
344 }
345 else if (p->frequency <= 1600)
346 {
347 u1FILT_PITHRD = 0xE;
348 u1W2R_SEL = 0x2;
349 }
350 else if (p->frequency <= 1866)
351 {
352 u1FILT_PITHRD = 0x12;
353 u1W2R_SEL = 0x2;
354 }
355 else
356 {
357 u1FILT_PITHRD = 0x17;
358 u1W2R_SEL = 0x2;
359 }
360
361 if (vGet_Div_Mode(p) == DIV4_MODE)
362 {
363 u1PRDCNT_DIV = 2;
364 u1IsDiv4 = 1;
365 }
366
367 u1DQSOSCRCNT = ((p->frequency<< u1IsDiv4))/100;
368 if ((p->frequency%100) != 0)
369 u1DQSOSCRCNT++;
370
371 if (gu1MR23[p->channel][RANK_1] > gu1MR23[p->channel][RANK_0])
372 u2PRDCNTtmp = ((gu1MR23[p->channel][RANK_1]*100)/u1PRDCNT_DIV);
373 else
374 u2PRDCNTtmp = ((gu1MR23[p->channel][RANK_0]*100)/u1PRDCNT_DIV);
375
376 u2PRDCNT = (u2PRDCNTtmp + ((u1DQSOSCRCNT*100)/16))/100;
377 u1RoundUp = (u2PRDCNTtmp + ((u1DQSOSCRCNT*100)/16))%100;
378 if (u1RoundUp != 0)
379 u2PRDCNT++;
380
381
382 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), u2PRDCNT, SHU_DQSOSC_SET0_DQSOSC_PRDCNT);
383
384
385 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSCR), u1DQSOSCRCNT, SHU_DQSOSCR_DQSOSCRCNT);
386 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), (u1FILT_PITHRD>>1), SHU_TX_SET0_DQS2DQ_FILT_PITHRD);
387 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_TX_SET0), P_Fld(u1W2R_SEL, SHU_TX_SET0_TXUPD_W2R_SEL) | P_Fld(0x0, SHU_TX_SET0_TXUPD_SEL));
388
389
390 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
391 {
392 vSetRank(p, u1RankIdx);
393 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC_THRD), gu2DQSOSCTHRD_INC[p->channel][u1RankIdx], SHURK_DQSOSC_THRD_DQSOSCTHRD_INC);
394 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC_THRD), gu2DQSOSCTHRD_DEC[p->channel][u1RankIdx], SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC);
395 }
396 vSetRank(p, u1RankIdxBak);
397
398
399 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DQSOSC_SET0), u2DQSOSCENCNT, SHU_DQSOSC_SET0_DQSOSCENCNT);
400
401 return DRAM_OK;
402 }
403
DramcHwDQSOSC(DRAMC_CTX_T * p)404 void DramcHwDQSOSC(DRAMC_CTX_T *p)
405 {
406 DRAM_RANK_T rank_bak = u1GetRank(p);
407 DRAM_CHANNEL_T ch_bak = p->channel;
408
409
410 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0), 1, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT);
411
412
413 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_TX_TRACKING_SET0), P_Fld(1, TX_TRACKING_SET0_SHU_PRELOAD_TX_HW)
414 | P_Fld(0, TX_TRACKING_SET0_SHU_PRELOAD_TX_START)
415 | P_Fld(0, TX_TRACKING_SET0_SW_UP_TX_NOW_CASE));
416
417
418 #if ENABLE_TMRRI_NEW_MODE
419 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 1, MPC_CTRL_MPC_BLOCKALE_OPT);
420 #else
421 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 0, MPC_CTRL_MPC_BLOCKALE_OPT);
422 #endif
423
424
425 #if ENABLE_SW_TX_TRACKING
426 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 1, MISC_CTRL1_R_DMARPIDQ_SW);
427 #else
428 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 0, MISC_CTRL1_R_DMARPIDQ_SW);
429 #if ENABLE_PA_IMPRO_FOR_TX_TRACKING
430 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DCM_SUB_CTRL), 1, DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING);
431 #endif
432 #endif
433 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_ARUIDQ_SW);
434
435
436 #if 0
437 vSetRank(p, RANK_0);
438 vSetPHY2ChannelMapping(p, CHANNEL_A);
439 DramcModeRegWrite(p, 23, u1MR23);
440 vSetPHY2ChannelMapping(p, CHANNEL_B);
441 DramcModeRegWrite(p, 23, u1MR23);
442
443 vSetRank(p, RANK_1);
444 vSetPHY2ChannelMapping(p, CHANNEL_A);
445 DramcModeRegWrite(p, 23, u1MR23);
446 vSetPHY2ChannelMapping(p, CHANNEL_B);
447 DramcModeRegWrite(p, 23, u1MR23);
448 #endif
449
450
451 #if ENABLE_SW_TX_TRACKING
452 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_DQSOSCRDIS);
453 #else
454 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0, DQSOSCR_DQSOSCRDIS);
455 #endif
456
457 vSetRank(p, RANK_0);
458 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC), 1, RK_DQSOSC_DQSOSCR_RK0EN);
459 if (p->support_rank_num == RANK_DUAL)
460 {
461 vSetRank(p, RANK_1);
462 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_DQSOSC), 1, RK_DQSOSC_DQSOSCR_RK0EN);
463 }
464
465
466 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 1, TX_SET0_DRSCLR_RK0_EN);
467
468 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_DQSOSC_CALEN);
469
470 vSetRank(p, rank_bak);
471 vSetPHY2ChannelMapping(p, ch_bak);
472 }
473
Enable_TX_Tracking(DRAMC_CTX_T * p)474 void Enable_TX_Tracking(DRAMC_CTX_T *p)
475 {
476
477 if (u1IsPhaseMode(p) == TRUE)
478 {
479 vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0, 1, SHU_DQSOSC_SET0_DQSOSCENDIS);
480 }
481 else
482 {
483 vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0, 0, SHU_DQSOSC_SET0_DQSOSCENDIS);
484 }
485 }
486 #endif
487
488 #if RDSEL_TRACKING_EN
Enable_RDSEL_Tracking(DRAMC_CTX_T * p,U16 u2Freq)489 void Enable_RDSEL_Tracking(DRAMC_CTX_T *p, U16 u2Freq)
490 {
491
492 if (u2Freq >= RDSEL_TRACKING_TH)
493 {
494 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, 0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN);
495 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, P_Fld(0x1, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN)
496 | P_Fld(0x0, SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK));
497 }
498 else
499 {
500 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, 0x0, SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN);
501 }
502 }
503 #endif
504
505 #ifdef HW_GATING
Enable_Gating_Tracking(DRAMC_CTX_T * p)506 void Enable_Gating_Tracking(DRAMC_CTX_T *p)
507 {
508
509 if (u1IsPhaseMode(p) == TRUE)
510 {
511 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_STBCAL,
512 P_Fld(0x0, MISC_SHU_STBCAL_STBCALEN) |
513 P_Fld(0x0, MISC_SHU_STBCAL_STB_SELPHCALEN));
514 } else {
515 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_STBCAL,
516 P_Fld(0x1, MISC_SHU_STBCAL_STBCALEN) |
517 P_Fld(0x1, MISC_SHU_STBCAL_STB_SELPHCALEN));
518 }
519 }
520 #endif
521
522 #if ENABLE_PER_BANK_REFRESH
Enable_PerBank_Refresh(DRAMC_CTX_T * p)523 void Enable_PerBank_Refresh(DRAMC_CTX_T *p)
524 {
525 vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF0, 1, SHU_CONF0_PBREFEN);
526 }
527 #endif
528
Enable_ClkTxRxLatchEn(DRAMC_CTX_T * p)529 void Enable_ClkTxRxLatchEn(DRAMC_CTX_T *p)
530 {
531
532 BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
533 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ13, 1, SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0);
534 if (!isLP4_DSC)
535 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ13, 1, SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1);
536 else
537 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD13, 1, SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA);
538
539 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ10, 1, SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0);
540 if (!isLP4_DSC)
541 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ10, 1, SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1);
542 else
543 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD10, 1, SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA);
544
545
546 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ2, 1, SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0);
547 if (!isLP4_DSC)
548 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ2, 1, SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1);
549 else
550 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD2, 1, SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA);
551
552
553 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ11, 1, SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0);
554 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ11, 1, SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1);
555 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD11, 1, SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA);
556
557 if(!isLP4_DSC)
558 {
559 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD10, P_Fld(0, SHU_CA_CMD10_RG_RX_ARCLK_RANK_SEL_LAT_EN_CA)\
560 | P_Fld(0, SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_RANK_SEL_LAT_EN_CA));
561 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD11, 0, SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA);
562 }
563 else
564 {
565 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ10, P_Fld(0, SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1)\
566 | P_Fld(0, SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1));
567 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ11, 0, SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1);
568 }
569 }
570
571 #if ENABLE_TX_WDQS
Enable_TxWDQS(DRAMC_CTX_T * p)572 void Enable_TxWDQS(DRAMC_CTX_T *p)
573 {
574 BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
575
576 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B0_DQ13, P_Fld(1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0)
577 | P_Fld(1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0)
578 | P_Fld(1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0)
579 | P_Fld(1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0));
580 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_B1_DQ13, P_Fld(!isLP4_DSC, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1)
581 | P_Fld(!isLP4_DSC, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1)
582 | P_Fld(!isLP4_DSC, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1)
583 | P_Fld(!isLP4_DSC, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1));
584 vIO32WriteFldMulti_All(DDRPHY_REG_SHU_CA_CMD13, P_Fld(isLP4_DSC, SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_EN_CA)
585 | P_Fld(isLP4_DSC, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_EN_CA)
586 | P_Fld(isLP4_DSC, SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_DATA_TIE_EN_CA)
587 | P_Fld(isLP4_DSC, SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA));
588 }
589 #endif
590 #if 0
591 static void Enable_and_Trigger_TX_Retry(DRAMC_CTX_T *p)
592 {
593 #if TX_RETRY_CONTROL_BY_SPM
594 vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 1, TX_RETRY_SET0_XSR_TX_RETRY_SPM_MODE);
595 #else
596 vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 0, TX_RETRY_SET0_XSR_TX_RETRY_SPM_MODE);
597 #endif
598 vIO32WriteFldMulti_All(DRAMC_REG_TX_RETRY_SET0, P_Fld(1, TX_RETRY_SET0_TX_RETRY_SHU_RESP_OPT)
599 | P_Fld(0, TX_RETRY_SET0_TX_RETRY_UPDPI_CG_OPT)
600 | P_Fld(1, TX_RETRY_SET0_XSR_TX_RETRY_OPT)
601 | P_Fld(0, TX_RETRY_SET0_XSR_TX_RETRY_EN)
602 | P_Fld(0, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN));
603
604 if (u1IsPhaseMode(p) == TRUE)
605 {
606 vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0, 1, SHU_DQSOSC_SET0_DQSOSCENDIS);
607 }
608 else
609 {
610 vIO32WriteFldAlign_All(DRAMC_REG_SHU_DQSOSC_SET0, 0, SHU_DQSOSC_SET0_DQSOSCENDIS);
611 }
612 }
613 #endif
614 #if ENABLE_SW_TX_TRACKING & __ETT__
DramcSWTxTracking(DRAMC_CTX_T * p)615 void DramcSWTxTracking(DRAMC_CTX_T *p)
616 {
617 U8 u1MR4OnOff;
618 U8 rankIdx, rankBak;
619 U8 u1SRAMShuLevel = vGet_Current_SRAMIdx(p);
620 U8 u1CurrentShuLevel;
621 U16 u2MR1819_Base[RANK_MAX][2], u2MR1819_Runtime[RANK_MAX][2];
622 U16 u2DQSOSC_INC[RANK_MAX] = {6}, u2DQSOSC_DEC[RANK_MAX] = {4};
623 U8 u1AdjPI[RANK_MAX][2];
624 U8 u1OriginalPI_DQ[DRAM_DFS_SRAM_MAX][RANK_MAX][2];
625 U8 u1UpdatedPI_DQ[DRAM_DFS_SRAM_MAX][RANK_MAX][2];
626 U8 u1OriginalPI_DQM[DRAM_DFS_SRAM_MAX][RANK_MAX][2];
627 U8 u1UpdatedPI_DQM[DRAM_DFS_SRAM_MAX][RANK_MAX][2];
628 U8 u1FreqRatioTX[DRAM_DFS_SRAM_MAX];
629 U8 shuIdx, shuBak, byteIdx;
630
631 if (gAndroid_DVFS_en)
632 {
633 for (shuIdx = 0; shuIdx < DRAM_DFS_SRAM_MAX; shuIdx++)
634 {
635 DRAM_DFS_FREQUENCY_TABLE_T *pDstFreqTbl = get_FreqTbl_by_SRAMIndex(p, shuIdx);
636 if (pDstFreqTbl == NULL)
637 {
638 mcSHOW_ERR_MSG(("NULL pFreqTbl %d\n", shuIdx));
639 while (1);
640 }
641
642 if (pDstFreqTbl->freq_sel == LP4_DDR800)
643 {
644 u1FreqRatioTX[shuIdx] = 0;
645 }
646 else
647 {
648 u1FreqRatioTX[shuIdx] = ((GetFreqBySel(p, pDstFreqTbl->freq_sel)) * 8) / p->frequency;
649 mcSHOW_DBG_MSG2(("[SWTxTracking] ShuLevel=%d, Ratio[%d]=%d (%d, %d)\n", u1SRAMShuLevel, shuIdx, u1FreqRatioTX[shuIdx], GetFreqBySel(p, pDstFreqTbl->freq_sel), p->frequency));
650 }
651 }
652 }
653 else
654 {
655 u1FreqRatioTX[0] = 8;
656 }
657
658 mcSHOW_DBG_MSG2(("[SWTxTracking] channel=%d\n", p->channel));
659 rankBak = u1GetRank(p);
660 shuBak = p->ShuRGAccessIdx;
661
662 u1CurrentShuLevel = u4IO32ReadFldAlign(DDRPHY_REG_DVFS_STATUS, DVFS_STATUS_OTHER_SHU_GP);
663
664 for (shuIdx = 0; shuIdx < DRAM_DFS_SRAM_MAX; shuIdx++)
665 {
666 if (shuIdx == u1SRAMShuLevel || !gAndroid_DVFS_en) {
667 p->ShuRGAccessIdx = u1CurrentShuLevel;
668 } else {
669 LoadShuffleSRAMtoDramc(p, shuIdx, !u1CurrentShuLevel);
670 p->ShuRGAccessIdx = !u1CurrentShuLevel;
671 }
672
673 for (rankIdx = RANK_0;rankIdx < p->support_rank_num;rankIdx++)
674 {
675 vSetRank(p, rankIdx);
676
677 u1OriginalPI_DQ[shuIdx][p->rank][0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), SHURK_PI_RK0_ARPI_DQ_B0);
678 u1OriginalPI_DQ[shuIdx][p->rank][1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), SHURK_PI_RK0_ARPI_DQ_B1);
679
680 u1OriginalPI_DQM[shuIdx][p->rank][0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), SHURK_PI_RK0_ARPI_DQM_B0);
681 u1OriginalPI_DQM[shuIdx][p->rank][1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_PI), SHURK_PI_RK0_ARPI_DQM_B1);
682 }
683
684 if (!gAndroid_DVFS_en)
685 break;
686 }
687
688 u1MR4OnOff = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), HMR4_REFRDIS);
689 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), 1, HMR4_REFRDIS);
690
691 p->ShuRGAccessIdx = u1CurrentShuLevel;
692
693 for (rankIdx = RANK_0;rankIdx < p->support_rank_num;rankIdx++)
694 {
695 vSetRank(p, rankIdx);
696
697 u2DQSOSC_INC[p->rank] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC_THRD), SHURK_DQSOSC_THRD_DQSOSCTHRD_INC);
698 u2DQSOSC_DEC[p->rank] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC_THRD), SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC);
699
700 u2MR1819_Base[p->rank][0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC), SHURK_DQSOSC_DQSOSC_BASE_RK0);
701 u2MR1819_Base[p->rank][1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC), SHURK_DQSOSC_DQSOSC_BASE_RK0_B1);
702
703 DramcDQSOSCAuto(p);
704
705 u2MR1819_Runtime[p->rank][0] = (gu2MR18[p->channel][p->rank] & 0x00FF) | ((gu2MR19[p->channel][p->rank] & 0x00FF) << 8);
706 if (p->dram_cbt_mode[p->rank] == CBT_BYTE_MODE1)
707 {
708 u2MR1819_Runtime[p->rank][1] = (gu2MR18[p->channel][p->rank] >> 8) | ((gu2MR19[p->channel][p->rank] & 0xFF00));
709 }
710 else
711 {
712 u2MR1819_Runtime[p->rank][1] = u2MR1819_Runtime[p->rank][0];
713 }
714
715
716 for (byteIdx = 0; byteIdx < 2; byteIdx++)
717 {
718 U16 deltaMR1819 = 0;
719
720 if (u2MR1819_Runtime[p->rank][byteIdx] >= u2MR1819_Base[p->rank][byteIdx])
721 {
722 deltaMR1819 = u2MR1819_Runtime[p->rank][byteIdx] - u2MR1819_Base[p->rank][byteIdx];
723 u1AdjPI[rankIdx][byteIdx] = deltaMR1819 / u2DQSOSC_INC[rankIdx];
724 for (shuIdx = 0; shuIdx < DRAM_DFS_SRAM_MAX; shuIdx++)
725 {
726 u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx] - (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]);
727 u1UpdatedPI_DQM[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQM[shuIdx][rankIdx][byteIdx] - (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]);
728 mcSHOW_DBG_MSG2(("SHU%u CH%d RK%d B%d, Base=%X Runtime=%X delta=%d INC=%d PI=0x%B Adj=%d newPI=0x%B\n", shuIdx, p->channel, u1GetRank(p), byteIdx
729 , u2MR1819_Base[p->rank][byteIdx], u2MR1819_Runtime[p->rank][byteIdx], deltaMR1819, u2DQSOSC_INC[rankIdx]
730 , u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx], (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]), u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx]));
731
732 if (!gAndroid_DVFS_en)
733 break;
734 }
735 }
736 else
737 {
738 deltaMR1819 = u2MR1819_Base[p->rank][byteIdx] - u2MR1819_Runtime[p->rank][byteIdx];
739 u1AdjPI[rankIdx][byteIdx] = deltaMR1819 / u2DQSOSC_DEC[rankIdx];
740 for (shuIdx = 0; shuIdx < DRAM_DFS_SRAM_MAX; shuIdx++)
741 {
742 u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx] + (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]);
743 u1UpdatedPI_DQM[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQM[shuIdx][rankIdx][byteIdx] + (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]);
744 mcSHOW_DBG_MSG2(("SHU%u CH%d RK%d B%d, Base=%X Runtime=%X delta=%d DEC=%d PI=0x%B Adj=%d newPI=0x%B\n", shuIdx, p->channel, u1GetRank(p), byteIdx
745 , u2MR1819_Base[p->rank][byteIdx], u2MR1819_Runtime[p->rank][byteIdx], deltaMR1819, u2DQSOSC_DEC[rankIdx]
746 , u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx], (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]), u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx]));
747
748 if (!gAndroid_DVFS_en)
749 break;
750 }
751 }
752 }
753 }
754
755 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_TXUPDMODE);
756
757 if (gAndroid_DVFS_en)
758 {
759 p->ShuRGAccessIdx = !u1CurrentShuLevel;
760 for (shuIdx = 0; shuIdx < DRAM_DFS_SRAM_MAX; shuIdx++)
761 {
762 LoadShuffleSRAMtoDramc(p, shuIdx, !u1CurrentShuLevel);
763
764 for (rankIdx = RANK_0;rankIdx < p->support_rank_num;rankIdx++)
765 {
766 vSetRank(p, rankIdx);
767
768 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0),
769 P_Fld(u1UpdatedPI_DQ[shuIdx][p->rank][0], SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
770 P_Fld(u1UpdatedPI_DQM[shuIdx][p->rank][0], SHU_R0_B0_DQ0_SW_ARPI_DQM_B0));
771 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0),
772 P_Fld(u1UpdatedPI_DQ[shuIdx][p->rank][1], SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
773 P_Fld(u1UpdatedPI_DQM[shuIdx][p->rank][1], SHU_R0_B1_DQ0_SW_ARPI_DQM_B1));
774 }
775
776 DramcSaveToShuffleSRAM(p, !u1CurrentShuLevel, shuIdx);
777 }
778 }
779
780 p->ShuRGAccessIdx = u1CurrentShuLevel;
781 shuIdx = (gAndroid_DVFS_en) ? u1SRAMShuLevel : 0;
782 for (rankIdx = RANK_0;rankIdx < p->support_rank_num;rankIdx++)
783 {
784 vSetRank(p, rankIdx);
785
786 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_DQ0),
787 P_Fld(u1UpdatedPI_DQ[shuIdx][p->rank][0], SHU_R0_B0_DQ0_SW_ARPI_DQ_B0) |
788 P_Fld(u1UpdatedPI_DQM[shuIdx][p->rank][0], SHU_R0_B0_DQ0_SW_ARPI_DQM_B0));
789 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_DQ0),
790 P_Fld(u1UpdatedPI_DQ[shuIdx][p->rank][1], SHU_R0_B1_DQ0_SW_ARPI_DQ_B1) |
791 P_Fld(u1UpdatedPI_DQM[shuIdx][p->rank][1], SHU_R0_B1_DQ0_SW_ARPI_DQM_B1));
792 }
793
794 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 1, DQSOSCR_MANUTXUPD);
795
796 while ((u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TCMDO1LAT), TCMDO1LAT_MANUTXUPD_B0_DONE) != 1) && (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TCMDO1LAT), TCMDO1LAT_MANUTXUPD_B1_DONE) != 1))
797 {
798 mcDELAY_US(1);
799 }
800
801 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0, DQSOSCR_TXUPDMODE);
802 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DQSOSCR), 0, DQSOSCR_MANUTXUPD);
803
804 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HMR4), u1MR4OnOff, HMR4_REFRDIS);
805
806 vSetRank(p, rankBak);
807 p->ShuRGAccessIdx = shuBak;
808 }
809 #endif
810
811 #if SIMULATION_RX_DVS || ENABLE_RX_TRACKING
DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T * p)812 void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p)
813 {
814 BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
815 U8 u1DVS_Delay;
816 U8 u1DVS_En=1;
817 U32 u4WbrBackup = GetDramcBroadcast();
818 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
819
820
821 #if (fcFOR_CHIP_ID == fc8195)
822
823 if(p->frequency >= 3200)
824 {
825 u1DVS_Delay =1;
826 }
827 else if(p->frequency >= 2250)
828 {
829 u1DVS_Delay = 2;
830 }
831 else if(p->frequency >= 2133)
832 {
833 u1DVS_Delay = 3;
834 }
835 else if(p->frequency >= 1600)
836 {
837 u1DVS_Delay =5;
838 }
839 else if(p->frequency >= 1200)
840 {
841 u1DVS_Delay =7;
842 }
843 else if(p->frequency >= 800)
844 {
845 u1DVS_Delay =12;
846 u1DVS_En =0;
847 }
848 else
849 {
850 u1DVS_Delay =15;
851 u1DVS_En =0;
852 }
853 #endif
854
855 #if RX_DVS_NOT_SHU_WA
856 if (isLP4_DSC)
857 {
858
859 u1DVS_En =1;
860 }
861 #endif
862
863
864 vIO32WriteFldAlign((DDRPHY_REG_SHU_B0_DQ5), u1DVS_Delay, SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0);
865 if (!isLP4_DSC)
866 {
867 vIO32WriteFldAlign((DDRPHY_REG_SHU_B1_DQ5), u1DVS_Delay, SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1);
868 }
869 else
870 {
871 vIO32WriteFldAlign((DDRPHY_REG_SHU_CA_CMD5), u1DVS_Delay, SHU_CA_CMD5_RG_RX_ARCLK_DVS_DLY);
872 }
873
874
875 vIO32WriteFldMulti((DDRPHY_REG_SHU_B0_DQ7), P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0)
876 | P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0));
877 vIO32WriteFldMulti((DDRPHY_REG_SHU_B1_DQ7), P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1)
878 | P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1));
879
880 vIO32WriteFldAlign((DDRPHY_REG_SHU_B0_DQ11), u1DVS_En, SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0);
881 if (!isLP4_DSC)
882 {
883 vIO32WriteFldAlign((DDRPHY_REG_SHU_B1_DQ11), u1DVS_En, SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1);
884 }
885 else
886 {
887 vIO32WriteFldAlign((DDRPHY_REG_CA_CMD5), u1DVS_En, CA_CMD5_RG_RX_ARCLK_DVS_EN);
888 }
889
890 DramcBroadcastOnOff(u4WbrBackup);
891 }
892 #endif
893
894
895 #if __A60868_TO_BE_PORTING__
896 #if RX_DLY_TRACK_ONLY_FOR_DEBUG
DramcRxDlyTrackDebug(DRAMC_CTX_T * p)897 void DramcRxDlyTrackDebug(DRAMC_CTX_T *p)
898 {
899
900
901 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK0_DUMMY_RD_ADR), P_Fld(2, RK0_DUMMY_RD_ADR_DMY_RD_RK0_ROW_ADR)
902 | P_Fld(0, RK0_DUMMY_RD_ADR_DMY_RD_RK0_COL_ADR)
903 | P_Fld(0, RK0_DUMMY_RD_ADR_DMY_RD_RK0_LEN));
904 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DRAMC_REG_RK1_DUMMY_RD_ADR), P_Fld(2, RK1_DUMMY_RD_ADR_DMY_RD_RK1_ROW_ADR)
905 | P_Fld(0, RK1_DUMMY_RD_ADR_DMY_RD_RK1_COL_ADR)
906 | P_Fld(0, RK1_DUMMY_RD_ADR_DMY_RD_RK1_LEN));
907 vIO32WriteFldAlign_All(DRAMC_REG_RK0_DUMMY_RD_BK, 0, RK0_DUMMY_RD_BK_DMY_RD_RK0_BK);
908 vIO32WriteFldAlign_All(DRAMC_REG_RK1_DUMMY_RD_BK, 0, RK1_DUMMY_RD_BK_DMY_RD_RK1_BK);
909
910 vIO32Write4B_All(DRAMC_REG_RK0_DUMMY_RD_WDATA0, 0xAAAA5555);
911 vIO32Write4B_All(DRAMC_REG_RK0_DUMMY_RD_WDATA1, 0xAAAA5555);
912 vIO32Write4B_All(DRAMC_REG_RK0_DUMMY_RD_WDATA2, 0xAAAA5555);
913 vIO32Write4B_All(DRAMC_REG_RK0_DUMMY_RD_WDATA3, 0xAAAA5555);
914 vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA0, 0xAAAA5555);
915 vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA1, 0xAAAA5555);
916 vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA2, 0xAAAA5555);
917 vIO32Write4B_All(DRAMC_REG_RK1_DUMMY_RD_WDATA3, 0xAAAA5555);
918
919
920 vIO32WriteFldMulti_All((DDRPHY_MISC_RXDVS2), P_Fld(0, MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN)
921 | P_Fld(1, MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR)
922 | P_Fld(0, MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN));
923
924
925 vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x1, DUMMY_RD_DMY_WR_DBG);
926 vIO32WriteFldAlign_All(DRAMC_REG_DUMMY_RD, 0x0, DUMMY_RD_DMY_WR_DBG);
927
928
929 vIO32WriteFldMulti_All((DDRPHY_MISC_RXDVS2), P_Fld(1, MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN)
930 | P_Fld(0, MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR)
931 | P_Fld(1, MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN));
932 }
933
DramcPrintRxDlyTrackDebugStatus(DRAMC_CTX_T * p)934 void DramcPrintRxDlyTrackDebugStatus(DRAMC_CTX_T *p)
935 {
936 U32 backup_rank, u1ChannelBak, u4value;
937 U8 u1ChannelIdx, u1ChannelMax = p->support_channel_num;
938
939 u1ChannelBak = p->channel;
940 backup_rank = u1GetRank(p);
941
942 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
943 {
944 p->channel = u1ChannelIdx;
945
946 u4value = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_MISC_DQ_RXDLY_TRRO18));
947 //mcSHOW_DBG_MSG(("\nCH_%d DQ_RXDLY_TRRO18 = 0x\033[1;36m%x\033[m\n",u1ChannelIdx,u4value));
948 if (u4value & 1)
949 {
950 mcSHOW_DBG_MSG3(("=== CH_%d DQ_RXDLY_TRRO18 = 0x\033[1;36m%x\033[m, %s %s shu: %d\n", u1ChannelIdx, u4value,
951 u4value & 0x2? "RK0: fail":"",u4value&0x4?"RK1: fail":"", (u4value >> 4) & 0x3));
952 }
953 }
954 }
955 #endif
956
957 #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
958 #if (__ETT__ || CPU_RW_TEST_AFTER_K)
DramcPrintRXDQDQSStatus(DRAMC_CTX_T * p,U8 u1Channel)959 void DramcPrintRXDQDQSStatus(DRAMC_CTX_T *p, U8 u1Channel)
960 {
961 U8 u1RankIdx, u1RankMax, u1ChannelBak, u1ByteIdx, ii;
962 U32 u4ResultDQS_PI, u4ResultDQS_UI, u4ResultDQS_UI_P1;
963 U8 u1Dqs_pi[DQS_BIT_NUMBER], u1Dqs_ui[DQS_BIT_NUMBER], u1Dqs_ui_P1[DQS_BIT_NUMBER];
964 U16 u2TmpValue, u2TmpUI[DQS_BYTE_NUMBER], u2TmpPI[DQS_BYTE_NUMBER];
965 U32 MANUDLLFRZ_bak, STBSTATE_OPT_bak;
966 U32 backup_rank;
967 U8 u1DQX_B0, u1DQS0, u1DQX_B1, u1DQS1;
968
969 u1ChannelBak = p->channel;
970 vSetPHY2ChannelMapping(p, u1Channel);
971 backup_rank = u1GetRank(p);
972
973 if (p->support_rank_num == RANK_DUAL)
974 u1RankMax = RANK_MAX;
975 else
976 u1RankMax = RANK_1;
977
978 for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++)
979 {
980 vSetRank(p, u1RankIdx);
981 mcSHOW_DBG_MSG3(("[RXDQDQSStatus] CH%d, RK%d\n", p->channel, u1RankIdx));
982 if (u1RankIdx == 0)
983 u4ResultDQS_PI = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_MISC_DQ_RXDLY_TRRO22));
984 if (u1RankIdx == 1)
985 u4ResultDQS_PI = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_MISC_DQ_RXDLY_TRRO23));
986
987 u1DQX_B0 = u4ResultDQS_PI & 0xff;
988 u1DQS0 = (u4ResultDQS_PI >> 8) & 0xff;
989 u1DQX_B1 = (u4ResultDQS_PI >> 16) & 0xff;
990 u1DQS1 = (u4ResultDQS_PI >> 24) & 0xff;
991
992 mcSHOW_DBG_MSG3(("DQX_B0, DQS0, DQX_B1, DQS1 =(%d, %d, %d, %d)\n\n", u1DQX_B0, u1DQS0, u1DQX_B1, u1DQS1));
993
994 }
995 vSetRank(p, backup_rank);
996
997 p->channel = u1ChannelBak;
998 vSetPHY2ChannelMapping(p, u1ChannelBak);
999 }
1000 #endif
1001 #endif
1002
DummyReadForDqsGatingRetryShuffle(DRAMC_CTX_T * p,bool bEn)1003 void DummyReadForDqsGatingRetryShuffle(DRAMC_CTX_T *p, bool bEn)
1004 {
1005 if (bEn == 1)
1006 {
1007 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DQSG_RETRY1, P_Fld(0, MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM)
1008 | P_Fld(1, MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE)
1009 | P_Fld(0, MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN)
1010 | P_Fld(0, MISC_SHU_DQSG_RETRY1_RETRY_SW_EN)
1011 | P_Fld(1, MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE)
1012 | P_Fld(1, MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE)
1013 | P_Fld(1, MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS));
1014 }
1015 else
1016 {
1017 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DQSG_RETRY1, P_Fld(0, MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE)
1018 | P_Fld(0, MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN)
1019 | P_Fld(0, MISC_SHU_DQSG_RETRY1_RETRY_SW_EN));
1020 }
1021 return;
1022 }
1023
DummyReadForDqsGatingRetryNonShuffle(DRAMC_CTX_T * p,bool bEn)1024 void DummyReadForDqsGatingRetryNonShuffle(DRAMC_CTX_T *p, bool bEn)
1025 {
1026 U8 backup_rank = p->rank;
1027 U8 rankIdx;
1028
1029 if (bEn == 1)
1030 {
1031 vIO32WriteFldAlign_All(DRAMC_REG_TEST2_A4, 4, TEST2_A4_TESTAGENTRKSEL);
1032 vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(1, DUMMY_RD_DQSG_DMYRD_EN)
1033 | P_Fld(p->support_rank_num, DUMMY_RD_RANK_NUM)
1034 | P_Fld(1, DUMMY_RD_DUMMY_RD_SW));
1035 for (rankIdx = RANK_0; rankIdx < p->support_rank_num; rankIdx++)
1036 {
1037 vSetRank(p, rankIdx);
1038 vIO32WriteFldAlign_All(DRAMC_REG_RK_DUMMY_RD_ADR, 0, RK_DUMMY_RD_ADR_DMY_RD_LEN);
1039 }
1040 vSetRank(p, backup_rank);
1041 }
1042 else
1043 {
1044 }
1045 return;
1046 }
1047
1048 #endif // __A60868_TO_BE_PORTING__
1049
1050 #ifdef IMPEDANCE_HW_SAVING
DramcImpedanceHWSaving(DRAMC_CTX_T * p)1051 void DramcImpedanceHWSaving(DRAMC_CTX_T *p)
1052 {
1053 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_IMPCAL_HWSAVE_EN);
1054 }
1055 #endif
1056
1057 #ifdef IMPEDANCE_TRACKING_ENABLE
DramcImpedanceTrackingEnable(DRAMC_CTX_T * p)1058 void DramcImpedanceTrackingEnable(DRAMC_CTX_T *p)
1059 {
1060 U8 u1CHAB_en = DISABLE;
1061 #if 0
1062 vIO32WriteFldMulti_All(DRAMC_REG_IMPEDAMCE_CTRL1, P_Fld(2, IMPEDAMCE_CTRL1_DQS1_OFF) | P_Fld(2, IMPEDAMCE_CTRL1_DOS2_OFF));
1063 vIO32WriteFldMulti_All(DRAMC_REG_IMPEDAMCE_CTRL2, P_Fld(2, IMPEDAMCE_CTRL2_DQ1_OFF) | P_Fld(2, IMPEDAMCE_CTRL2_DQ2_OFF));
1064 #endif
1065
1066 #ifdef IMP_DEBUG_ENABLE
1067 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DBG_IRQ_CTRL9, P_Fld(1, MISC_DBG_IRQ_CTRL9_IMP_CLK_ERR_CLEAN)
1068 | P_Fld(1, MISC_DBG_IRQ_CTRL9_IMP_CMD_ERR_CLEAN)
1069 | P_Fld(1, MISC_DBG_IRQ_CTRL9_IMP_DQ1_ERR_CLEAN)
1070 | P_Fld(1, MISC_DBG_IRQ_CTRL9_IMP_DQ0_ERR_CLEAN)
1071 | P_Fld(1, MISC_DBG_IRQ_CTRL9_IMP_DQS_ERR_CLEAN)
1072 | P_Fld(1, MISC_DBG_IRQ_CTRL9_IMP_ODTN_ERR_CLEAN)
1073 | P_Fld(1, MISC_DBG_IRQ_CTRL9_IMP_DRVN_ERR_CLEAN)
1074 | P_Fld(1, MISC_DBG_IRQ_CTRL9_IMP_DRVP_ERR_CLEAN));
1075 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMP_CTRL1, 1, MISC_IMP_CTRL1_IMP_ABN_LAT_CLR);
1076 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_IMP_CTRL1, P_Fld(3, MISC_IMP_CTRL1_IMP_DIFF_THD) | P_Fld(0, MISC_IMP_CTRL1_IMP_ABN_LAT_CLR));
1077 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMP_CTRL1, 1, MISC_IMP_CTRL1_IMP_ABN_LAT_EN);
1078 #endif
1079
1080
1081 //u1CHAB_en = (p->support_channel_num == CHANNEL_DUAL) ? ENABLE : DISABLE;
1082 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CTRL0, u1CHAB_en, MISC_CTRL0_IMPCAL_CHAB_EN);
1083
1084
1085 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_IMPCAL, P_Fld(1, MISC_IMPCAL_IMPCAL_HW) | P_Fld(0, MISC_IMPCAL_IMPCAL_EN) |
1086 P_Fld(1, MISC_IMPCAL_IMPCAL_SWVALUE_EN) | P_Fld(1, MISC_IMPCAL_IMPCAL_NEW_OLD_SL) |
1087 P_Fld(1, MISC_IMPCAL_IMPCAL_DRVUPDOPT) | P_Fld(1, MISC_IMPCAL_IMPCAL_CHGDRV_ECO_OPT) |
1088 P_Fld(1, MISC_IMPCAL_IMPCAL_SM_ECO_OPT) | P_Fld(1, MISC_IMPCAL_IMPBINARY) |
1089 P_Fld(1, MISC_IMPCAL_DRV_ECO_OPT));
1090
1091
1092 vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) |
1093 P_Fld(0x0, MISC_CTRL0_IMPCAL_TRACK_DISABLE));
1094 vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0 + SHIFT_TO_CHB_ADDR, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) |
1095 P_Fld(0x1, MISC_CTRL0_IMPCAL_TRACK_DISABLE));
1096
1097
1098 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV);
1099
1100
1101 vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL, P_Fld(0, MISC_IMPCAL_DIS_SUS_CH0_DRV) |
1102 P_Fld(1, MISC_IMPCAL_DIS_SUS_CH1_DRV) |
1103 P_Fld(0, MISC_IMPCAL_IMPSRCEXT) |
1104 P_Fld(1, MISC_IMPCAL_IMPCAL_ECO_OPT));
1105 vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHB_ADDR, P_Fld(1, MISC_IMPCAL_DIS_SUS_CH0_DRV) |
1106 P_Fld(0, MISC_IMPCAL_DIS_SUS_CH1_DRV) |
1107 P_Fld(1, MISC_IMPCAL_IMPSRCEXT) |
1108 P_Fld(0, MISC_IMPCAL_IMPCAL_ECO_OPT));
1109 #if (CHANNEL_NUM > 2)
1110 if (channel_num_auxadc > 2) {
1111 vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHC_ADDR, P_Fld(0, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(1, MISC_IMPCAL_DIS_SUS_CH1_DRV));
1112 vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHD_ADDR, P_Fld(1, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(0, MISC_IMPCAL_DIS_SUS_CH1_DRV));
1113 vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0 + SHIFT_TO_CHC_ADDR, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) | P_Fld(0x0, MISC_CTRL0_IMPCAL_TRACK_DISABLE));
1114 vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0 + SHIFT_TO_CHD_ADDR, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) | P_Fld(0x1, MISC_CTRL0_IMPCAL_TRACK_DISABLE));
1115 vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHC_ADDR, P_Fld(0, MISC_IMPCAL_IMPSRCEXT) | P_Fld(1, MISC_IMPCAL_IMPCAL_ECO_OPT));
1116 vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHD_ADDR, P_Fld(1, MISC_IMPCAL_IMPSRCEXT) | P_Fld(0, MISC_IMPCAL_IMPCAL_ECO_OPT));
1117 }
1118 #endif
1119
1120
1121 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_DRVCGWREF);
1122 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_IMPCAL, 1, MISC_IMPCAL_DQDRVSWUPD);
1123 }
1124 #endif
1125
1126 #if __ETT__
DramcPrintIMPTrackingStatus(DRAMC_CTX_T * p,U8 u1Channel)1127 void DramcPrintIMPTrackingStatus(DRAMC_CTX_T *p, U8 u1Channel)
1128 {
1129 #ifdef IMPEDANCE_TRACKING_ENABLE
1130
1131 U8 u1RankIdx, u1RankMax, u1ChannelBak, u1ByteIdx, ii;
1132 U8 DQS_DRVN_2, DQS_DRVP_2, DQS_ODTN_2, DQS_DRVN, DQS_DRVP, DQS_ODTN;
1133 U8 DQ_DRVN_2, DQ_DRVP_2, DQ_ODTN_2, DQ_DRVN, DQ_DRVP, DQ_ODTN;
1134 U8 CMD_DRVN_2, CMD_DRVP_2, CMD_ODTN_2, CMD_DRVN, CMD_DRVP, CMD_ODTN;
1135
1136 u1ChannelBak = p->channel;
1137 vSetPHY2ChannelMapping(p, u1Channel);
1138
1139 mcSHOW_DBG_MSG3(("[IMPTrackingStatus] CH=%d\n", p->channel));
1140
1141 // if (u1Channel == CHANNEL_A)
1142 {
1143
1144
1145 DQS_DRVN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS2), MISC_IMPCAL_STATUS2_DRVNDQS_SAVE_2);
1146 DQS_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS2), MISC_IMPCAL_STATUS2_DRVPDQS_SAVE_2);
1147 DQS_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS2), MISC_IMPCAL_STATUS2_ODTNDQS_SAVE_2);
1148 DQS_DRVN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS1), MISC_IMPCAL_STATUS1_DRVNDQS_SAVE_1);
1149 DQS_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS1), MISC_IMPCAL_STATUS1_DRVPDQS_SAVE_1);
1150 DQS_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS1), MISC_IMPCAL_STATUS1_ODTNDQS_SAVE_1);
1151
1152
1153 DQ_DRVN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS4), MISC_IMPCAL_STATUS4_DRVNDQ_SAVE_2);
1154 DQ_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS4), MISC_IMPCAL_STATUS4_DRVPDQ_SAVE_2);
1155 DQ_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS4), MISC_IMPCAL_STATUS4_ODTNDQ_SAVE_2);
1156 DQ_DRVN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_DRVNDQ_SAVE_1);
1157 DQ_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_DRVPDQ_SAVE_1);
1158 DQ_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS3), MISC_IMPCAL_STATUS3_ODTNDQ_SAVE_1);
1159
1160
1161 CMD_DRVN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS8), MISC_IMPCAL_STATUS8_DRVNCMD_SAVE_2);
1162 CMD_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS8), MISC_IMPCAL_STATUS8_DRVPCMD_SAVE_2);
1163 CMD_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS8), MISC_IMPCAL_STATUS8_ODTNCMD_SAVE_2);
1164 CMD_DRVN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS7), MISC_IMPCAL_STATUS7_DRVNCMD_SAVE_1);
1165 CMD_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS7), MISC_IMPCAL_STATUS7_DRVPCMD_SAVE_1);
1166 CMD_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL_STATUS7), MISC_IMPCAL_STATUS7_ODTNCMD_SAVE_1);
1167 }
1168 #if 0
1169 else
1170 {
1171 U8 shu_level;
1172
1173
1174 shu_level = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHUSTATUS), SHUSTATUS_SHUFFLE_LEVEL);
1175 mcSHOW_DBG_MSG(("shu_level=%d\n", shu_level));
1176
1177
1178 DQ_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING1 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING1_DQDRV2_DRVP);
1179 DQ_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING2 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING2_DQDRV1_DRVP);
1180 DQ_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING3 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING3_DQODT2_ODTN);
1181 DQ_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING4 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING4_DQODT1_ODTN);
1182
1183
1184 DQS_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING1 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING1_DQSDRV2_DRVP);
1185 DQS_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING1 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING1_DQSDRV1_DRVP);
1186 DQS_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING3 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING3_DQSODT2_ODTN);
1187 DQS_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING3 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING3_DQSODT1_ODTN);
1188
1189
1190 CMD_DRVP_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING2 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING2_CMDDRV2_DRVP);
1191 CMD_DRVP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING2 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING2_CMDDRV1_DRVP);
1192 CMD_ODTN_2 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING4 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING4_CMDODT2_ODTN);
1193 CMD_ODTN = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_DRVING4 + shu_level * SHU_GRP_DRAMC_OFFSET), SHU_DRVING4_CMDODT1_ODTN);
1194 }
1195 #endif
1196
1197 mcSHOW_DBG_MSG3(("\tDRVN_2\tDRVP_2\tODTN_2\tDRVN\tDRVP\tODTN\n"
1198 "DQS\t%d\t%d\t%d\t%d\t%d\t%d\n"
1199 "DQ\t%d\t%d\t%d\t%d\t%d\t%d\n"
1200 "CMD\t%d\t%d\t%d\t%d\t%d\t%d\n",
1201 DQS_DRVN_2, DQS_DRVP_2, DQS_ODTN_2, DQS_DRVN, DQS_DRVP, DQS_ODTN,
1202 DQ_DRVN_2, DQ_DRVP_2, DQ_ODTN_2, DQ_DRVN, DQ_DRVP, DQ_ODTN,
1203 CMD_DRVN_2, CMD_DRVP_2, CMD_ODTN_2, CMD_DRVN, CMD_DRVP, CMD_ODTN));
1204
1205 p->channel = u1ChannelBak;
1206 vSetPHY2ChannelMapping(p, u1ChannelBak);
1207 #endif
1208 }
1209 #endif
1210
divRoundClosest(const int n,const int d)1211 int divRoundClosest(const int n, const int d)
1212 {
1213 return ((n < 0) ^ (d < 0))? ((n - d / 2) / d): ((n + d / 2) / d);
1214 }
1215
1216
1217 #if (ENABLE_TX_TRACKING || TDQSCK_PRECALCULATION_FOR_DVFS)
FreqJumpRatioCalculation(DRAMC_CTX_T * p)1218 void FreqJumpRatioCalculation(DRAMC_CTX_T *p)
1219 {
1220 U32 shuffle_src_freq, shuffle_dst_index, jump_ratio_index;
1221 U16 u2JumpRatio[12] = {0};
1222 U16 u2Freq = 0;
1223
1224
1225 jump_ratio_index = 0;
1226
1227 if (vGet_DDR_Loop_Mode(p) == CLOSE_LOOP_MODE)
1228 {
1229 shuffle_src_freq = p->frequency;
1230 for (shuffle_dst_index = SRAM_SHU0; shuffle_dst_index < DRAM_DFS_SRAM_MAX; shuffle_dst_index++)
1231 {
1232 DRAM_DFS_FREQUENCY_TABLE_T *pDstFreqTbl = get_FreqTbl_by_SRAMIndex(p, shuffle_dst_index);
1233 if (pDstFreqTbl == NULL)
1234 {
1235 mcSHOW_ERR_MSG(("NULL pFreqTbl\n"));
1236 #if __ETT__
1237 while (1);
1238 #endif
1239 }
1240 #if 0
1241 if (pDstFreqTbl->freq_sel == LP4_DDR800)
1242 {
1243 u2JumpRatio[jump_ratio_index] = 0;
1244 }
1245 else
1246 #endif
1247 {
1248 u2Freq = GetFreqBySel(p, pDstFreqTbl->freq_sel);
1249 u2JumpRatio[jump_ratio_index] = divRoundClosest(u2Freq * 32, shuffle_src_freq);
1250 //u2JumpRatio[jump_ratio_index] = (pDstFreqTbl->frequency/shuffle_src_freq)*32;
1251 //mcSHOW_DBG_MSG3(("shuffle_%d=DDR%d / shuffle_%d=DDR%d \n", shuffle_dst_index, pFreqTbl->frequency<<1,
1252 // shuffle_src_index, get_FreqTbl_by_SRAMIndex(p,shuffle_src_index)->frequency<<1));
1253 //mcSHOW_DBG_MSG3(("Jump_RATIO_%d : 0x%x\n", jump_ratio_index, u2JumpRatio[jump_ratio_index],
1254 // get_FreqTbl_by_SRAMIndex(p,shuffle_src_index)->frequency));
1255 }
1256 #if DUMP_ALLSUH_RG
1257 mcSHOW_DBG_MSG(("[DUMPLOG] %d Jump_RATIO[%d]=%d, Jump_DDR%d=%d, Jump_DDR%d=%d\n", p->frequency*2, jump_ratio_index, u2JumpRatio[jump_ratio_index], vGet_Current_SRAMIdx(p), shuffle_src_freq << 1, shuffle_dst_index, u2Freq << 1));
1258 #endif
1259 jump_ratio_index++;
1260 }
1261 }
1262
1263
1264 vIO32WriteFldMulti_All(DRAMC_REG_SHU_FREQ_RATIO_SET0, P_Fld(u2JumpRatio[0], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0)
1265 | P_Fld(u2JumpRatio[1], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1)
1266 | P_Fld(u2JumpRatio[2], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2)
1267 | P_Fld(u2JumpRatio[3], SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3));
1268 vIO32WriteFldMulti_All(DRAMC_REG_SHU_FREQ_RATIO_SET1, P_Fld(u2JumpRatio[4], SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4)
1269 | P_Fld(u2JumpRatio[5], SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5)
1270 | P_Fld(u2JumpRatio[6], SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6)
1271 | P_Fld(u2JumpRatio[7], SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO7));
1272 vIO32WriteFldMulti_All(DRAMC_REG_SHU_FREQ_RATIO_SET2, P_Fld(u2JumpRatio[8], SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO8)
1273 | P_Fld(u2JumpRatio[9], SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9));
1274 return;
1275 }
1276 #endif
1277
1278
1279 #if TDQSCK_PRECALCULATION_FOR_DVFS
DramcDQSPrecalculation_preset(DRAMC_CTX_T * p)1280 void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)
1281 {
1282 U8 mck, ui, pi;
1283 U8 mck_p1, ui_p1;
1284 U8 byte_idx, rank;
1285 U8 backup_rank;
1286 U8 mck2ui;
1287 U8 set_value;
1288
1289 backup_rank = u1GetRank(p);
1290
1291 #if 1//(fcFOR_CHIP_ID == fc8195)
1292 mck2ui = 4;
1293 #else
1294
1295 if (vGet_Div_Mode(p) == DIV16_MODE)
1296 mck2ui = 4;
1297 else if (vGet_Div_Mode(p) == DIV8_MODE)
1298 mck2ui = 3;
1299 else
1300 mck2ui = 2;
1301 #endif
1302
1303 mcSHOW_DBG_MSG2(("Pre-setting of DQS Precalculation\n"));
1304
1305 for (byte_idx = 0; byte_idx < DQS_BYTE_NUMBER; byte_idx++) {
1306 for (rank = RANK_0; rank < p->support_rank_num; rank++) {
1307 vSetRank(p, rank);
1308
1309 if (byte_idx == 0) {
1310 mck = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
1311 SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0);
1312 ui = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
1313 SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0);
1314
1315 mck_p1= u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
1316 SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0);
1317 ui_p1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY),
1318 SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0);
1319
1320 pi = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY),
1321 SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0);
1322
1323 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_INI_UIPI),
1324 P_Fld((mck << mck2ui) + ui, SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0) |
1325 P_Fld(pi, SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0));
1326 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI),
1327 P_Fld((mck << mck2ui) +ui, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0) |
1328 P_Fld((mck_p1 << mck2ui) + ui_p1, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0) |
1329 P_Fld(pi, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0));
1330 } else {
1331 mck = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
1332 SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1);
1333 ui = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
1334 SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1);
1335
1336 mck_p1= u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
1337 SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1);
1338 ui_p1 = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY),
1339 SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1);
1340
1341 pi = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY),
1342 SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1);
1343
1344 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_INI_UIPI),
1345 P_Fld((mck << mck2ui) + ui, SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1) |
1346 P_Fld(pi, SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1));
1347 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI),
1348 P_Fld((mck << mck2ui) +ui, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1) |
1349 P_Fld((mck_p1 << mck2ui) + ui_p1, SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1) |
1350 P_Fld(pi, SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0));
1351 }
1352 }
1353 }
1354
1355 vSetRank(p, backup_rank);
1356
1357
1358 if (vGet_DDR_Loop_Mode(p) != CLOSE_LOOP_MODE)
1359 {
1360 set_value = 1;
1361 }
1362 else
1363 {
1364 set_value = 0;
1365 }
1366
1367 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_PRE_TDQSCK),
1368 set_value, SHU_MISC_PRE_TDQSCK_PRECAL_DISABLE);
1369 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RX_CG_CTRL),
1370 set_value, MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN);
1371 #if DUMP_ALLSUH_RG
1372 mcSHOW_DBG_MSG(("[DUMPLOG] %d RX_DQS_PREK_DISABLE Channel%d %d\n", p->frequency * 2, p->channel, set_value));
1373 #endif
1374 }
1375
1376 #if 0
1377 void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)
1378 {
1379 U8 u1ByteIdx, u1RankNum, u1RankBackup = p->rank;
1380 U8 u1ShuLevel = vGet_Current_SRAMIdx(p);
1381 U8 u1UI_value, u1PI_value, u1MCK_value;
1382 U16 u2Byte_offset;
1383 U32 u1Delay_Addr[2] = {0}, u1Delay_Fld[2];
1384 REG_FLD_DQS_PRE_K TransferReg;
1385
1386 mcSHOW_DBG_MSG(("Pre-setting of DQS Precalculation\n"));
1387 mcDUMP_REG_MSG(("Pre-setting of DQS Precalculation\n"));
1388
1389 if ((u1ShuLevel >= SRAM_SHU4) && (u1ShuLevel <= SRAM_SHU7))
1390 {
1391 u1Delay_Addr[0] = ((u1ShuLevel / 6) * 0x4) + 0x30;
1392 u1Delay_Addr[1] = 0x38;
1393 u2Byte_offset = 0xc;
1394 }
1395 else if (u1ShuLevel >= SRAM_SHU8)
1396 {
1397 u1Delay_Addr[0] = 0x260;
1398 u1Delay_Addr[1] = 0x268;
1399 u2Byte_offset = 0x4;
1400 }
1401 else
1402 {
1403 u1Delay_Addr[0] = ((u1ShuLevel / 2) * 0x4);
1404 u1Delay_Addr[1] = 0x8;
1405 u2Byte_offset = 0xc;
1406 }
1407
1408 u1Delay_Fld[0] = u1ShuLevel % 2;
1409 u1Delay_Fld[1] = u1ShuLevel % 4;
1410
1411 switch (u1Delay_Fld[0])
1412 {
1413 case 0:
1414 TransferReg.u4UI_Fld = RK0_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R0;
1415 TransferReg.u4PI_Fld = RK0_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R0;
1416 break;
1417 case 1:
1418 TransferReg.u4UI_Fld = RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0;
1419 TransferReg.u4PI_Fld = RK0_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R0;
1420 break;
1421 default:
1422 break;
1423 }
1424
1425 if (u1ShuLevel == SRAM_SHU8)
1426 {
1427 TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ9_P1_B0R0;
1428 TransferReg.u4UI_Fld_P1[1] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ9_P1_B1R0;
1429 }
1430 else if (u1ShuLevel == SRAM_SHU9)
1431 {
1432 TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ10_P1_B0R0;
1433 TransferReg.u4UI_Fld_P1[1] = RK0_PRE_TDQSCK27_TDQSCK_UIFREQ10_P1_B1R0;
1434 }
1435 else
1436 {
1437 switch (u1Delay_Fld[1])
1438 {
1439 case 0:
1440 TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R0;
1441 break;
1442 case 1:
1443 TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0;
1444 break;
1445 case 2:
1446 TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0;
1447 break;
1448 case 3:
1449 TransferReg.u4UI_Fld_P1[0] = RK0_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R0;
1450 break;
1451 default:
1452 break;
1453 }
1454 }
1455
1456 for (u1ByteIdx = 0; u1ByteIdx < (p->data_width / DQS_BIT_NUMBER); u1ByteIdx++)
1457 {
1458 for (u1RankNum = 0; u1RankNum < p->support_rank_num; u1RankNum++)
1459 {
1460 vSetRank(p, u1RankNum);
1461
1462 if (u1ByteIdx == 0)
1463 {
1464 u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED);
1465 u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED);
1466 u1PI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_DQSIEN), SHURK0_DQSIEN_R0DQS0IEN);
1467 }
1468 else
1469 {
1470 u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED);
1471 u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED);
1472 u1PI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_DQSIEN), SHURK0_DQSIEN_R0DQS1IEN);
1473 }
1474
1475 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[0] + (u1ByteIdx * u2Byte_offset)), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld);
1476 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[0] + (u1ByteIdx * u2Byte_offset)), u1PI_value, TransferReg.u4PI_Fld);
1477
1478 if (u1ByteIdx == 0)
1479 {
1480 u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1);
1481 u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1);
1482 }
1483 else
1484 {
1485 u1MCK_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0), SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1);
1486 u1UI_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1), SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1);
1487 }
1488
1489 if ((u1ShuLevel == SRAM_SHU8) || (u1ShuLevel == SRAM_SHU9))
1490 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[1]), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld_P1[u1ByteIdx]);
1491 else
1492 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1 + u1Delay_Addr[1] + (u1ByteIdx * u2Byte_offset)), (u1MCK_value << 3) | u1UI_value, TransferReg.u4UI_Fld_P1[0]);
1493 }
1494 }
1495 vSetRank(p, u1RankBackup);
1496
1497 return;
1498 }
1499 #endif
1500
DramcDQSPrecalculation_enable(DRAMC_CTX_T * p)1501 void DramcDQSPrecalculation_enable(DRAMC_CTX_T *p)
1502 {
1503
1504 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_PRE_TDQSCK1, 0x1, MISC_PRE_TDQSCK1_TDQSCK_PRECAL_HW);
1505
1506 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_PRE_TDQSCK1, 0x1, MISC_PRE_TDQSCK1_TDQSCK_REG_DVFS);
1507
1508 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_PRE_TDQSCK1, 0x1, MISC_PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL);
1509 }
1510 #endif
1511
1512 #if 0
1513 void DramcHWGatingInit(DRAMC_CTX_T *p)
1514 {
1515 #ifdef HW_GATING
1516 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
1517 0, MISC_SHU_STBCAL_STBCALEN);
1518 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL),
1519 P_Fld(0, MISC_STBCAL_STBCAL2R) |
1520 //P_Fld(0,STBCAL_STB_SELPHYCALEN) |
1521 P_Fld(0, MISC_STBCAL_STBSTATE_OPT) |
1522 P_Fld(0, MISC_STBCAL_RKCHGMASKDIS) |
1523 P_Fld(0, MISC_STBCAL_REFUICHG) |
1524 P_Fld(1, MISC_STBCAL_PICGEN));
1525
1526 vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), P_Fld(1, MISC_STBCAL_DQSIENCG_CHG_EN));
1527 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 0, MISC_STBCAL_CG_RKEN);
1528 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 1, MISC_STBCAL_DQSIENCG_NORMAL_EN);
1529 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1), 1, MISC_CTRL1_R_DMDQSIENCG_EN);
1530
1531 DramcHWDQSGatingTracking_ModeSetting(p);
1532 #endif
1533 }
1534 #endif
1535
DramcHWGatingOnOff(DRAMC_CTX_T * p,U8 u1OnOff)1536 void DramcHWGatingOnOff(DRAMC_CTX_T *p, U8 u1OnOff)
1537 {
1538 #ifdef HW_GATING
1539 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2),
1540 u1OnOff, MISC_STBCAL2_STB_GERRSTOP);
1541 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
1542 u1OnOff, MISC_SHU_STBCAL_STBCALEN);
1543 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
1544 u1OnOff, MISC_SHU_STBCAL_STB_SELPHCALEN);
1545 #else
1546 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), 0,
1547 MISC_STBCAL2_STB_GERRSTOP);
1548 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
1549 0, MISC_SHU_STBCAL_STBCALEN);
1550 vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
1551 0, MISC_SHU_STBCAL_STB_SELPHCALEN);
1552 #endif
1553 }
1554
1555
DramcHWGatingDebugOnOff(DRAMC_CTX_T * p,U8 u1OnOff)1556 void DramcHWGatingDebugOnOff(DRAMC_CTX_T *p, U8 u1OnOff)
1557 {
1558 #ifdef HW_GATING
1559
1560 U8 u1EnB0B1 = (u1OnOff == ENABLE)? 0x3: 0x0;
1561
1562 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_STBCAL2,
1563 P_Fld(u1EnB0B1, MISC_STBCAL2_STB_DBG_EN) |
1564 P_Fld(u1OnOff, MISC_STBCAL2_STB_PIDLYCG_IG) |
1565 P_Fld(u1OnOff, MISC_STBCAL2_STB_UIDLYCG_IG) |
1566 P_Fld(u1OnOff, MISC_STBCAL2_STB_GERRSTOP) |
1567 P_Fld(0, MISC_STBCAL2_STB_DBG_CG_AO) |
1568 P_Fld(0, MISC_STBCAL2_STB_DBG_UIPI_UPD_OPT));
1569 #endif
1570
1571 #if ENABLE_RX_FIFO_MISMATCH_DEBUG
1572 vIO32WriteFldAlign_All(DDRPHY_REG_B0_DQ9, 1, B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0);
1573 vIO32WriteFldAlign_All(DDRPHY_REG_B1_DQ9, 1, B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1);
1574 #endif
1575 }
1576
1577 #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
1578 #if (__ETT__ || CPU_RW_TEST_AFTER_K)
1579 #if 0
1580 U16 u2MaxGatingPos[CHANNEL_NUM][RANK_MAX][DQS_NUMBER] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
1581 U16 u2MinGatingPos[CHANNEL_NUM][RANK_MAX][DQS_NUMBER] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
1582 #endif
DramcPrintHWGatingStatus(DRAMC_CTX_T * p,U8 u1Channel)1583 void DramcPrintHWGatingStatus(DRAMC_CTX_T *p, U8 u1Channel)
1584 {
1585 #ifdef HW_GATING
1586 U8 u1RankIdx, u1RankMax, u1ChannelBak;
1587 U8 u1Dqs_pi[DQS_BIT_NUMBER]={0}, u1Dqs_ui[DQS_BIT_NUMBER]={0}, u1Dqs_ui_P1[DQS_BIT_NUMBER]={0};
1588 U32 MANUDLLFRZ_bak, STBSTATE_OPT_bak;
1589 U32 backup_rank;
1590
1591 u1ChannelBak = p->channel;
1592 vSetPHY2ChannelMapping(p, u1Channel);
1593 backup_rank = u1GetRank(p);
1594
1595 if (p->support_rank_num == RANK_DUAL)
1596 u1RankMax = RANK_MAX;
1597 else
1598 u1RankMax = RANK_1;
1599
1600 MANUDLLFRZ_bak = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DLLFRZ_CTRL), DLLFRZ_CTRL_MANUDLLFRZ);
1601 STBSTATE_OPT_bak = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), MISC_STBCAL_STBSTATE_OPT);
1602
1603 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DLLFRZ_CTRL), 1, DLLFRZ_CTRL_MANUDLLFRZ);
1604 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), 1, MISC_STBCAL_STBSTATE_OPT);
1605
1606 for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++)
1607 {
1608 vSetRank(p, u1RankIdx);
1609 mcSHOW_DBG_MSG3(("[DramcHWGatingStatus] Channel=%d, Rank=%d\n", p->channel, u1RankIdx));
1610
1611 u1Dqs_pi[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0),
1612 GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_PI_DLY_RK0);
1613 u1Dqs_ui[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0),
1614 GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_UI_P0_DLY_RK0);
1615 u1Dqs_ui_P1[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0),
1616 GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_UI_P1_DLY_RK0);;
1617
1618 u1Dqs_pi[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK0),
1619 GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_PI_DLY_RK0);
1620 u1Dqs_ui[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK0),
1621 GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_UI_P0_DLY_RK0);
1622 u1Dqs_ui_P1[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK0),
1623 GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_UI_P1_DLY_RK0);;
1624
1625 mcSHOW_DBG_MSG3(("Byte0(ui, pi) =(%x, %x) Byte1(ui, pi) =(%x, %x)\n",
1626 u1Dqs_ui[0], u1Dqs_pi[0], u1Dqs_ui[1], u1Dqs_pi[1]));
1627 mcSHOW_DBG_MSG3(("UI_Phase1 (DQS0~1) =(%x, %x)\n\n",
1628 u1Dqs_ui_P1[0], u1Dqs_ui_P1[1]));
1629 }
1630
1631 vSetRank(p, backup_rank);
1632 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL), STBSTATE_OPT_bak, MISC_STBCAL_STBSTATE_OPT);
1633 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DLLFRZ_CTRL), MANUDLLFRZ_bak, DLLFRZ_CTRL_MANUDLLFRZ);
1634
1635 p->channel = u1ChannelBak;
1636 vSetPHY2ChannelMapping(p, u1ChannelBak);
1637 #endif
1638 }
1639 #if 0
1640 static void DramcHWGatingTrackingRecord(DRAMC_CTX_T *p, U8 u1Channel)
1641 {
1642 #ifdef HW_GATING
1643 #if __A60868_TO_BE_PORTING__
1644 U8 u1RankIdx, u1RankMax, u1Info_NUM, u1Info_Max_MUM = 16;
1645 U8 u1ChannelBak, u1RankBak;
1646
1647 U8 u1DBG_Dqs0_DFS, u1DBG_Dqs0_Lead, u1DBG_Dqs0_Lag, u1DBG_Dqs0_UI, u1DBG_Dqs0_PI;
1648 U8 u1DBG_Dqs1_DFS, u1DBG_Dqs1_Lead, u1DBG_Dqs1_Lag, u1DBG_Dqs1_UI, u1DBG_Dqs1_PI;
1649 U16 u4DBG_Dqs0_Info, u4DBG_Dqs1_Info;
1650 U32 u4DBG_Dqs01_Info;
1651
1652 U32 u4Dqs0_MAX_MIN_DLY, u4Dqs1_MAX_MIN_DLY;
1653 U16 u2Dqs0_UI_MAX_DLY, u2Dqs0_PI_MAX_DLY, u2Dqs0_UI_MIN_DLY, u2Dqs0_PI_MIN_DLY;
1654 U16 u2Dqs1_UI_MAX_DLY, u2Dqs1_PI_MAX_DLY, u2Dqs1_UI_MIN_DLY, u2Dqs1_PI_MIN_DLY;
1655 U8 u1ShuffleLevel;
1656
1657 u1ChannelBak = p->channel;
1658 vSetPHY2ChannelMapping(p, u1Channel);
1659 u1RankBak = u1GetRank(p);
1660
1661 if (p->support_rank_num == RANK_DUAL)
1662 u1RankMax = RANK_MAX;
1663 else
1664 u1RankMax = RANK_1;
1665
1666
1667 //for(u1RankIdx=0; u1RankIdx<u1RankMax; u1RankIdx++)
1668 for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++)
1669 {
1670 vSetRank(p, u1RankIdx);
1671
1672 u1ShuffleLevel = u4IO32ReadFldAlign(DRAMC_REG_SHUSTATUS, SHUSTATUS_SHUFFLE_LEVEL);
1673
1674 mcSHOW_DBG_MSG3(("\n[HWGatingTrackingRecord] Channel=%d, Rank=%d, SHU_LEVEL=%d\n", p->channel, u1RankIdx, u1ShuffleLevel));
1675
1676 mcSHOW_DBG_MSG3(("Run Time HW Gating Debug Information :\n"));
1677 mcSHOW_DBG_MSG3((" B0=(DFS,Lead,Lag,4T, UI, PI), B1=(DFS,Lead,Lag,4T, UI, PI)\n"));
1678
1679 for (u1Info_NUM = 0; u1Info_NUM < u1Info_Max_MUM; u1Info_NUM++)
1680 {
1681
1682 u4DBG_Dqs01_Info = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RK0_B01_STB_DBG_INFO_00 + 0x4 * u1Info_NUM));
1683 u4DBG_Dqs0_Info = (u4DBG_Dqs01_Info >> 0) & 0xffff;
1684 u4DBG_Dqs1_Info = (u4DBG_Dqs01_Info >> 16) & 0xffff;
1685
1686 u1DBG_Dqs0_DFS = (u4DBG_Dqs0_Info >> 14) & 0x03;
1687 u1DBG_Dqs0_Lead = (u4DBG_Dqs0_Info >> 13) & 0x01;
1688 u1DBG_Dqs0_Lag = (u4DBG_Dqs0_Info >> 12) & 0x01;
1689 u1DBG_Dqs0_UI = (u4DBG_Dqs0_Info >> 6) & 0x3f;
1690 u1DBG_Dqs0_PI = (u4DBG_Dqs0_Info >> 0) & 0x3f;
1691
1692 u1DBG_Dqs1_DFS = (u4DBG_Dqs1_Info >> 14) & 0x03;
1693 u1DBG_Dqs1_Lead = (u4DBG_Dqs1_Info >> 13) & 0x01;
1694 u1DBG_Dqs1_Lag = (u4DBG_Dqs1_Info >> 12) & 0x01;
1695 u1DBG_Dqs1_UI = (u4DBG_Dqs1_Info >> 6) & 0x3f;
1696 u1DBG_Dqs1_PI = (u4DBG_Dqs1_Info >> 0) & 0x3f;
1697
1698 if (u1Info_NUM < 10)
1699 {
1700 mcSHOW_DBG_MSG3(("Info= %d ", u1Info_NUM));
1701 }
1702 else
1703 {
1704 mcSHOW_DBG_MSG3(("Info=%d ", u1Info_NUM));
1705 }
1706
1707 mcSHOW_DBG_MSG3(("B0=( %d, %d, %d, %d, %d, %d), B1=( %d, %d, %d, %d, %d, %d)\n",
1708 u1DBG_Dqs0_DFS, u1DBG_Dqs0_Lead, u1DBG_Dqs0_Lag, u1DBG_Dqs0_UI / 8, u1DBG_Dqs0_UI % 8, u1DBG_Dqs0_PI,
1709 u1DBG_Dqs1_DFS, u1DBG_Dqs1_Lead, u1DBG_Dqs1_Lag, u1DBG_Dqs1_UI / 8, u1DBG_Dqs1_UI % 8, u1DBG_Dqs1_PI));
1710 }
1711
1712
1713 u4Dqs0_MAX_MIN_DLY = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RK0_B0_STB_MAX_MIN_DLY));
1714 u2Dqs0_UI_MAX_DLY = (u4Dqs0_MAX_MIN_DLY >> 22) & 0x3f;
1715 u2Dqs0_PI_MAX_DLY = (u4Dqs0_MAX_MIN_DLY >> 16) & 0x3f;
1716 u2Dqs0_UI_MIN_DLY = (u4Dqs0_MAX_MIN_DLY >> 6) & 0x3f;
1717 u2Dqs0_PI_MIN_DLY = (u4Dqs0_MAX_MIN_DLY >> 0) & 0x3f;
1718
1719 u4Dqs1_MAX_MIN_DLY = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RK0_B1_STB_MAX_MIN_DLY));
1720 u2Dqs1_UI_MAX_DLY = (u4Dqs1_MAX_MIN_DLY >> 22) & 0x3f;
1721 u2Dqs1_PI_MAX_DLY = (u4Dqs1_MAX_MIN_DLY >> 16) & 0x3f;
1722 u2Dqs1_UI_MIN_DLY = (u4Dqs1_MAX_MIN_DLY >> 6) & 0x3f;
1723 u2Dqs1_PI_MIN_DLY = (u4Dqs1_MAX_MIN_DLY >> 0) & 0x3f;
1724
1725 mcSHOW_DBG_MSG3(("B0 = MAX(4T, UI, PI) MIN(4T, UI, PI), B1 = MAX(4T, UI, PI) MIN(4T, UI, PI)\n"));
1726 mcSHOW_DBG_MSG3(("B0 = MAX( %d, %d, %d) MIN( %d, %d, %d), B1 = MAX( %d, %d, %d) MIN( %d, %d, %d)\n",
1727 u2Dqs0_UI_MAX_DLY / 8, u2Dqs0_UI_MAX_DLY % 8, u2Dqs0_PI_MAX_DLY,
1728 u2Dqs0_UI_MIN_DLY / 8, u2Dqs0_UI_MIN_DLY % 8, u2Dqs0_PI_MIN_DLY,
1729 u2Dqs1_UI_MAX_DLY / 8, u2Dqs1_UI_MAX_DLY % 8, u2Dqs1_PI_MAX_DLY,
1730 u2Dqs1_UI_MIN_DLY / 8, u2Dqs1_UI_MIN_DLY % 8, u2Dqs1_PI_MIN_DLY));
1731 }
1732 vSetRank(p, u1RankBak);
1733 p->channel = u1ChannelBak;
1734 vSetPHY2ChannelMapping(p, u1ChannelBak);
1735 #endif
1736 #endif
1737 }
1738 #endif
1739 ///TODO: wait for porting +++
1740 #if __A60868_TO_BE_PORTING__
1741
DramcPrintRXFIFODebugStatus(DRAMC_CTX_T * p)1742 void DramcPrintRXFIFODebugStatus(DRAMC_CTX_T *p)
1743 {
1744 #if RX_PICG_NEW_MODE
1745
1746 U32 u1ChannelBak, u4value;
1747 U8 u1ChannelIdx;
1748
1749 u1ChannelBak = p->channel;
1750
1751 for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
1752 {
1753 p->channel = u1ChannelIdx;
1754
1755 u4value = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBERR_RK0_R)) & (0xf << 24);
1756 if (u4value)
1757 {
1758 mcSHOW_DBG_MSG2(("\n[RXFIFODebugStatus] CH_%d MISC_STBERR_RK0_R_RX_ARDQ = 0x\033[1;36m%x\033[m for Gating error information\n", u1ChannelIdx, u4value));
1759 }
1760 }
1761 p->channel = u1ChannelBak;
1762 vSetPHY2ChannelMapping(p, u1ChannelBak);
1763 #endif
1764 }
1765 #endif //#if __ETT__
1766 #endif
1767
1768 #endif /// __A60868_TO_BE_PORTING__
1769 ///TODO: wait for porting +++
1770