1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_CAVIUM_CN81XX_ADDRESSMAP_H__ 4 #define __SOC_CAVIUM_CN81XX_ADDRESSMAP_H__ 5 6 #define MAX_DRAM_ADDRESS 0x2000000000ULL /* 128GB */ 7 8 /* Physical addressed with bit 47 set indicate I/O memory space. */ 9 10 /* ARM code entry vector */ 11 #define BOOTROM_OFFSET 0x100000 12 13 /* Start of IO space */ 14 #define IO_SPACE_START 0x800000000000ULL 15 #define IO_SPACE_SIZE 0x100000000000ULL 16 17 /* L2C */ 18 #define L2C_PF_BAR0 0x87E080800000ULL 19 #define L2C_TAD0_PF_BAR0 (0x87E050000000ULL + 0x10000) 20 #define L2C_TAD0_INT_W1C (0x87E050000000ULL + 0x40000) 21 #define L2C_CBC0_PF_BAR0 0x87E058000000ULL 22 #define L2C_MCI0_PF_BAR0 0x87E05C000000ULL 23 24 /* LMC */ 25 #define LMC0_PF_BAR0 0x87E088000000ULL 26 #define LMC0_DDR_PLL_CTL0 0x258 27 28 /* OCLA */ 29 30 /* IOB */ 31 #define IOBN0_PF_BAR0 0x87E0F0000000ULL 32 #define MRML_PF_BAR0 0x87E0FC000000ULL 33 34 /* SMMU */ 35 #define SMMU_PF_BAR0 0x830000000000ULL 36 37 /* GTI */ 38 #define GTI_PF_BAR0 0x844000000000ULL 39 40 /* PCC */ 41 #define ECAM_PF_BAR2 0x848000000000ULL 42 #define ECAM0_DEVX_NSDIS 0x87e048070000ULL 43 #define ECAM0_DEVX_SDIS 0x87e048060000ULL 44 #define ECAM0_RSLX_NSDIS 0x87e048050000ULL 45 #define ECAM0_RSLX_SDIS 0x87e048040000ULL 46 47 /* CPT */ 48 /* SLI */ 49 50 /* RST */ 51 #define RST_PF_BAR0 (0x87E006000000ULL + 0x1600) 52 #define RST_PP_AVAILABLE (RST_PF_BAR0 + 0x138ULL) 53 #define RST_PP_RESET (RST_PF_BAR0 + 0x140ULL) 54 #define RST_PP_PENDING (RST_PF_BAR0 + 0x148ULL) 55 56 #define FUSF_PF_BAR0 0x87E004000000ULL 57 #define MIO_FUS_PF_BAR0 0x87E003000000ULL 58 #define MIO_BOOT_PF_BAR0 0x87E000000000ULL 59 #define MIO_BOOT_AP_JUMP (MIO_BOOT_PF_BAR0 + 0xD0ULL) 60 61 /* PTP */ 62 #define MIO_PTP_PF_BAR0 0x807000000000ULL 63 64 /* GIC */ 65 /* NIC */ 66 /* LBK */ 67 68 #define GTI_PF_BAR0 0x844000000000ULL 69 70 /* DAP */ 71 /* BCH */ 72 /* KEY */ 73 /* RNG */ 74 75 #define GSER0_PF_BAR0 (0x87E090000000ULL + (0 << 24)) 76 #define GSER1_PF_BAR0 (0x87E090000000ULL + (1 << 24)) 77 #define GSER2_PF_BAR0 (0x87E090000000ULL + (2 << 24)) 78 #define GSER3_PF_BAR0 (0x87E090000000ULL + (3 << 24)) 79 #define GSERx_PF_BAR0(x) \ 80 ((((x) == 0) || ((x) == 1) || ((x) == 2) || ((x) == 3)) ? \ 81 (0x87E090000000ULL + ((x) << 24)) : 0) 82 83 /* PEM */ 84 #define PEM_PEMX_PF_BAR0(x) (0x87e0c0000000ULL + 0x1000000ULL * (x)) 85 86 /* SATA */ 87 /* USB */ 88 89 /* UAA */ 90 #define UAA0_PF_BAR0 (0x87E028000000ULL + (0 << 24)) 91 #define UAA1_PF_BAR0 (0x87E028000000ULL + (1 << 24)) 92 #define UAA2_PF_BAR0 (0x87E028000000ULL + (2 << 24)) 93 #define UAA3_PF_BAR0 (0x87E028000000ULL + (3 << 24)) 94 #define UAAx_PF_BAR0(x) \ 95 ((((x) == 0) || ((x) == 1) || ((x) == 2) || ((x) == 3)) ? \ 96 (0x87E028000000ULL + ((x) << 24)) : 0) 97 98 #define CAVM_GICD_SETSPI_NSR 0x801000000040ULL 99 #define CAVM_GICD_CLRSPI_NSR 0x801000000048ULL 100 101 /* TWSI */ 102 #define MIO_TWS0_PF_BAR0 (0x87E0D0000000ULL + (0 << 24)) 103 #define MIO_TWS1_PF_BAR0 (0x87E0D0000000ULL + (1 << 24)) 104 #define MIO_TWSx_PF_BAR0(x) \ 105 ((((x) == 0) || ((x) == 1)) ? (0x87E0D0000000ULL + ((x) << 24)) : 0) 106 107 /* GPIO */ 108 #define GPIO_PF_BAR0 0x803000000000ULL 109 110 /* SGPIO */ 111 #define SGP_PF_BAR0 0x803000000000ULL 112 113 /* SMI */ 114 115 /* SPI */ 116 #define MPI_PF_BAR0 (0x804000000000ULL + 0x1000) 117 118 /* PCM */ 119 /* PBUS */ 120 /* NDF */ 121 /* EMM */ 122 123 /* VRM */ 124 /* VRM BARs are spaced apart by 0x1000000 */ 125 #define VRM0_PF_BAR0 0x87E021000000ULL 126 127 #endif /* __SOC_CAVIUM_CN81XX_ADDRESSMAP_H__ */ 128