1 /* -*- mesa-c++ -*- 2 * Copyright 2018-2019 Collabora LTD 3 * Author: Gert Wollny <[email protected]> 4 * SPDX-License-Identifier: MIT 5 */ 6 7 #ifndef sfn_defines_h 8 #define sfn_defines_h 9 10 #include "../r600_isa.h" 11 #include "amd_family.h" 12 namespace r600 { 13 14 enum EGWSOpCode { 15 cf_sema_v = 0, 16 cf_sema_p = 1, 17 cf_gws_barrier = 2, 18 cf_gws_init = 3, 19 }; 20 21 /* CF ALU instructions [29:26], highest bit always set. */ 22 enum ECFAluOpCode { 23 cf_alu_undefined = 0, 24 cf_alu = CF_OP_ALU, 25 cf_alu_push_before = CF_OP_ALU_PUSH_BEFORE, 26 cf_alu_pop_after = CF_OP_ALU_POP_AFTER, 27 cf_alu_pop2_after = CF_OP_ALU_POP2_AFTER, 28 cf_alu_extended = CF_OP_ALU_EXT, 29 cf_alu_continue = CF_OP_ALU_CONTINUE, 30 cf_alu_break = CF_OP_ALU_BREAK, 31 cf_alu_else_after = CF_OP_ALU_ELSE_AFTER, 32 }; 33 34 enum ECFAluOpCodeEG { 35 eg_cf_alu_undefined = 0, 36 eg_cf_alu = 8, 37 eg_cf_alu_push_before = 9, 38 eg_cf_alu_pop_after = 10, 39 eg_cf_alu_pop2_after = 11, 40 eg_cf_alu_extended = 12, 41 eg_cf_alu_continue = 13, 42 eg_cf_alu_break = 14, 43 eg_cf_alu_else_after = 15, 44 }; 45 46 enum ECFOpCode { 47 cf_nop = CF_OP_NOP, 48 cf_tc = CF_OP_TEX, 49 cf_vc = CF_OP_VTX, 50 cf_gds = CF_OP_GDS, 51 cf_loop_start = CF_OP_LOOP_START, 52 cf_loop_end = CF_OP_LOOP_END, 53 cf_loop_start_dx10 = CF_OP_LOOP_START_DX10, 54 cf_loop_start_no_al = CF_OP_LOOP_START_NO_AL, 55 cf_loop_continue = CF_OP_LOOP_CONTINUE, 56 cf_loop_break = CF_OP_LOOP_BREAK, 57 cf_jump = CF_OP_JUMP, 58 cf_push = CF_OP_PUSH, 59 cf_else = CF_OP_ELSE, 60 cf_pop = CF_OP_POP, 61 /* 15 - 17 reserved */ 62 cf_call = CF_OP_CALL, 63 cf_call_fs = CF_OP_CALL_FS, 64 cf_return = CF_OP_RET, 65 cf_emit_vertex = CF_OP_EMIT_VERTEX, 66 cf_emit_cut_vertex = CF_OP_EMIT_CUT_VERTEX, 67 cf_cut_vertex = CF_OP_CUT_VERTEX, 68 cf_kill = CF_OP_KILL, 69 /* 25 reserved */ 70 cf_wait_ack = CF_OP_WAIT_ACK, 71 cf_tc_ack = CF_OP_TEX_ACK, 72 cf_vc_ack = CF_OP_VTX_ACK, 73 cf_jump_table = CF_OP_JUMPTABLE, 74 cf_global_wave_sync = CF_OP_WAVE_SYNC, 75 cf_halt = CF_OP_HALT, 76 /* gap 32-63*/ 77 cf_mem_stream0_buf0 = CF_OP_MEM_STREAM0_BUF0, 78 cf_mem_stream0_buf1 = CF_OP_MEM_STREAM0_BUF1, 79 cf_mem_stream0_buf2 = CF_OP_MEM_STREAM0_BUF2, 80 cf_mem_stream0_buf3 = CF_OP_MEM_STREAM0_BUF3, 81 82 cf_mem_stream1_buf0 = CF_OP_MEM_STREAM1_BUF0, 83 cf_mem_stream1_buf1 = CF_OP_MEM_STREAM1_BUF1, 84 cf_mem_stream1_buf2 = CF_OP_MEM_STREAM1_BUF2, 85 cf_mem_stream1_buf3 = CF_OP_MEM_STREAM1_BUF3, 86 87 cf_mem_stream2_buf0 = CF_OP_MEM_STREAM2_BUF0, 88 cf_mem_stream2_buf1 = CF_OP_MEM_STREAM2_BUF1, 89 cf_mem_stream2_buf2 = CF_OP_MEM_STREAM2_BUF2, 90 cf_mem_stream2_buf3 = CF_OP_MEM_STREAM2_BUF3, 91 92 cf_mem_stream3_buf0 = CF_OP_MEM_STREAM3_BUF0, 93 cf_mem_stream3_buf1 = CF_OP_MEM_STREAM3_BUF1, 94 cf_mem_stream3_buf2 = CF_OP_MEM_STREAM3_BUF2, 95 cf_mem_stream3_buf3 = CF_OP_MEM_STREAM3_BUF3, 96 97 cf_mem_write_scratch = CF_OP_MEM_SCRATCH, 98 /* reserved 81 */ 99 cf_mem_ring = CF_OP_MEM_RING, 100 cf_export = CF_OP_EXPORT, 101 cf_export_done = CF_OP_EXPORT_DONE, 102 cf_mem_export = CF_OP_MEM_EXPORT, 103 cf_mem_rat = CF_OP_MEM_RAT, 104 cf_mem_rat_cacheless = CF_OP_MEM_RAT_NOCACHE, 105 106 cf_mem_ring1 = CF_OP_MEM_RING1, 107 cf_mem_ring2 = CF_OP_MEM_RING2, 108 cf_mem_ring3 = CF_OP_MEM_RING3, 109 cf_mem_export_combined = CF_OP_MEM_MEM_COMBINED, 110 cf_mem_rat_combined_cacheless = CF_OP_MEM_RAT_COMBINED_NOCACHE 111 }; 112 113 enum ECFOpCodeEG { 114 eg_cf_nop = 0, 115 eg_cf_tc = 1, 116 eg_cf_vc = 2, 117 eg_cf_gds = 3, 118 eg_cf_loop_start = 4, 119 eg_cf_loop_end = 5, 120 eg_cf_loop_start_dx10 = 6, 121 eg_cf_loop_start_no_al = 7, 122 eg_cf_loop_continue = 8, 123 eg_cf_loop_break = 9, 124 eg_cf_jump = 10, 125 eg_cf_push = 11, 126 eg_cf_else = 13, 127 eg_cf_pop = 14, 128 /* 15 - 17 reserved */ 129 eg_cf_call = 18, 130 eg_cf_call_fs, 131 eg_cf_return, 132 eg_cf_emit_vertex, 133 eg_cf_emit_cut_vertex, 134 eg_cf_cut_vertex, 135 eg_cf_kill, 136 /* 25 reserved */ 137 eg_cf_wait_ack = 26, 138 eg_cf_tc_ack, 139 eg_cf_vc_ack, 140 eg_cf_jump_table, 141 eg_cf_global_wave_sync, 142 eg_cf_halt, 143 /* gap 32-63*/ 144 eg_cf_mem_stream0_buf0 = 64, 145 eg_cf_mem_stream0_buf1, 146 eg_cf_mem_stream0_buf2, 147 eg_cf_mem_stream0_buf3, 148 149 eg_cf_mem_stream1_buf0, 150 eg_cf_mem_stream1_buf1, 151 eg_cf_mem_stream1_buf2, 152 eg_cf_mem_stream1_buf3, 153 154 eg_cf_mem_stream2_buf0, 155 eg_cf_mem_stream2_buf1, 156 eg_cf_mem_stream2_buf2, 157 eg_cf_mem_stream2_buf3, 158 159 eg_cf_mem_stream3_buf0, 160 eg_cf_mem_stream3_buf1, 161 eg_cf_mem_stream3_buf2, 162 eg_cf_mem_stream3_buf3, 163 164 eg_cf_mem_write_scratch, 165 /* reserved 81 */ 166 eg_cf_mem_ring = 82, 167 eg_cf_export, 168 eg_cf_export_done, 169 eg_cf_mem_export, 170 eg_cf_mem_rat, 171 eg_cf_mem_rat_cacheless, 172 173 eg_cf_mem_ring1, 174 eg_cf_mem_ring2, 175 eg_cf_mem_ring3, 176 eg_cf_mem_export_combined, 177 eg_cf_mem_rat_combined_cacheless 178 }; 179 180 enum EVFetchInstr { 181 vc_fetch = FETCH_OP_VFETCH, 182 vc_semantic = FETCH_OP_SEMFETCH, 183 vc_get_buf_resinfo = FETCH_OP_GET_BUFFER_RESINFO, 184 vc_read_scratch = FETCH_OP_READ_SCRATCH, 185 vc_unknown 186 }; 187 188 enum EVFetchType { 189 vertex_data = 0, 190 instance_data = 1, 191 no_index_offset = 2 192 }; 193 194 enum EVTXDataFormat { 195 fmt_invalid = 0, 196 fmt_8 = 1, 197 fmt_4_4 = 2, 198 fmt_3_3_2 = 3, 199 fmt_reserved_4 = 4, 200 fmt_16 = 5, 201 fmt_16_float = 6, 202 fmt_8_8 = 7, 203 fmt_5_6_5 = 8, 204 fmt_6_5_5 = 9, 205 fmt_1_5_5_5 = 10, 206 fmt_4_4_4_4 = 11, 207 fmt_5_5_5_1 = 12, 208 fmt_32 = 13, 209 fmt_32_float = 14, 210 fmt_16_16 = 15, 211 fmt_16_16_float = 16, 212 fmt_8_24 = 17, 213 fmt_8_24_float = 18, 214 fmt_24_8 = 19, 215 fmt_24_8_float = 20, 216 fmt_10_11_11 = 21, 217 fmt_10_11_11_float = 22, 218 fmt_11_11_10 = 23, 219 fmt_11_11_10_float = 24, 220 fmt_2_10_10_10 = 25, 221 fmt_8_8_8_8 = 26, 222 fmt_10_10_10_2 = 27, 223 fmt_x24_8_32_float = 28, 224 fmt_32_32 = 29, 225 fmt_32_32_float = 30, 226 fmt_16_16_16_16 = 31, 227 fmt_16_16_16_16_float = 32, 228 fmt_reserved_33 = 33, 229 fmt_32_32_32_32 = 34, 230 fmt_32_32_32_32_float = 35, 231 fmt_reserved_36 = 36, 232 fmt_1 = 37, 233 fmt_1_reversed = 38, 234 fmt_gb_gr = 39, 235 fmt_bg_rg = 40, 236 fmt_32_as_8 = 41, 237 fmt_32_as_8_8 = 42, 238 fmt_5_9_9_9_sharedexp = 43, 239 fmt_8_8_8 = 44, 240 fmt_16_16_16 = 45, 241 fmt_16_16_16_float = 46, 242 fmt_32_32_32 = 47, 243 fmt_32_32_32_float = 48, 244 fmt_bc1 = 49, 245 fmt_bc2 = 50, 246 fmt_bc3 = 51, 247 fmt_bc4 = 52, 248 fmt_bc5 = 53, 249 fmt_apc0 = 54, 250 fmt_apc1 = 55, 251 fmt_apc2 = 56, 252 fmt_apc3 = 57, 253 fmt_apc4 = 58, 254 fmt_apc5 = 59, 255 fmt_apc6 = 60, 256 fmt_apc7 = 61, 257 fmt_ctx1 = 62, 258 fmt_reserved_63 = 63 259 }; 260 261 enum EVFetchNumFormat { 262 vtx_nf_norm = 0, 263 vtx_nf_int = 1, 264 vtx_nf_scaled = 2 265 }; 266 267 enum EVFetchEndianSwap { 268 vtx_es_none = 0, 269 vtx_es_8in16 = 1, 270 vtx_es_8in32 = 2 271 }; 272 273 enum EVFetchFlagShift { 274 vtx_fetch_whole_quad, 275 vtx_use_const_field, 276 vtx_format_comp_signed, 277 vtx_srf_mode, 278 vtx_buf_no_stride, 279 vtx_alt_const, 280 vtx_use_tc, 281 vtx_vpm, 282 vtx_is_mega_fetch, 283 vtx_uncached, 284 vtx_indexed, 285 vtx_unknown 286 }; 287 288 enum EBufferIndexMode { 289 bim_none, 290 bim_zero, 291 bim_one, 292 bim_invalid 293 }; 294 295 } // namespace r600 296 297 #endif // DEFINES_H 298