1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _SOC_QUALCOMM_SC7280_ADDRESS_MAP_H_ 4 #define _SOC_QUALCOMM_SC7280_ADDRESS_MAP_H_ 5 6 #include <stdint.h> 7 8 #define AOSS_CC_BASE 0x0C2A0000 9 #define DISP_CC_BASE 0x0AF00000 10 #define GCC_BASE 0x00100000 11 #define L3_PLL_BASE 0x18284000 12 #define QSPI_BASE 0x088DC000 13 #define SHRM_SPROC_BASE 0x09051000 14 #define SILVER_PLL_BASE 0x18280000 15 #define TLMM_TILE_BASE 0x0F100000 16 17 /* SC7280 QSPI GPIO PINS */ 18 #define QSPI_CS GPIO(15) 19 #define QSPI_DATA_0 GPIO(12) 20 #define QSPI_DATA_1 GPIO(13) 21 #define QSPI_CLK GPIO(14) 22 23 #define GPIO_FUNC_QSPI_DATA_0 GPIO12_FUNC_QSPI_DATA_0 24 #define GPIO_FUNC_QSPI_DATA_1 GPIO13_FUNC_QSPI_DATA_1 25 #define GPIO_FUNC_QSPI_CLK GPIO14_FUNC_QSPI_CLK 26 27 /* SDHC TLMM Registers */ 28 #define SDC1_TLMM_CFG_ADDR 0x0F1B3000 29 #define SDC2_TLMM_CFG_ADDR 0x0F1B4000 30 31 /* 32 * QUP SERIAL ENGINE BASE ADDRESSES 33 */ 34 /* QUPV3_0 */ 35 #define QUP_SERIAL0_BASE 0x00980000 36 #define QUP_SERIAL1_BASE 0x00984000 37 #define QUP_SERIAL2_BASE 0x00988000 38 #define QUP_SERIAL3_BASE 0x0098C000 39 #define QUP_SERIAL4_BASE 0x00990000 40 #define QUP_SERIAL5_BASE 0x00994000 41 #define QUP_SERIAL6_BASE 0x00998000 42 #define QUP_SERIAL7_BASE 0x0099C000 43 #define QUP_WRAP0_BASE 0x009C0000 44 #define QUP_0_GSI_BASE 0x00904000 45 46 /* QUPV3_1 */ 47 #define QUP_SERIAL8_BASE 0x00A80000 48 #define QUP_SERIAL9_BASE 0x00A84000 49 #define QUP_SERIAL10_BASE 0x00A88000 50 #define QUP_SERIAL11_BASE 0x00A8C000 51 #define QUP_SERIAL12_BASE 0x00A90000 52 #define QUP_SERIAL13_BASE 0x00A94000 53 #define QUP_SERIAL14_BASE 0x00A98000 54 #define QUP_SERIAL15_BASE 0x00A9C000 55 #define QUP_WRAP1_BASE 0x00AC0000 56 #define QUP_1_GSI_BASE 0x00A04000 57 58 #define EPSSTOP_EPSS_TOP 0x18598000 59 #define EPSSFAST_BASE_ADDR 0x18580000 60 61 /* 62 * USB BASE ADDRESSES 63 */ 64 #define HS_USB_PRIM_PHY_BASE 0x088e3000 65 #define QMP_PHY_QSERDES_COM_REG_BASE 0x088e9000 66 #define QMP_PHY_QSERDES_TX_REG_BASE 0x088e9200 67 #define QMP_PHY_QSERDES_RX_REG_BASE 0x088e9400 68 #define QMP_PHY_PCS_REG_BASE 0x088e9c00 69 #define USB_HOST_DWC3_BASE 0x0a60c100 70 71 /* PCIE_1 */ 72 #define PCIE1_PCIE_PARF 0x01C08000 73 #define PCIE1_GEN3X2_PCIE_DBI 0x40000000 74 #define PCIE1_GEN3X2_PCIE_ELBI 0x40000F20 75 #define PCIE1_GEN3X2_DWC_PCIE_DM_IATU 0x40001000 76 #define PCIE1_SPACE_END_ADDR 0x60000000 77 #define PCIE1_BCR 0x18D000 78 79 /* QMP PCIE_1 PHY */ 80 #define PCIE_1_QMP_PHY 0x01C0E000 81 82 /* QMP PHY, Serdes,Tx, Rx and PCS register definitions */ 83 #define PCIE1_QMP_PHY_PCS_COM 0x01C0EA00 84 #define PCE1_QPHY_SERDES 0x01C0E000 85 #define PCE1_QPHY_TX0 0x01C0E200 86 #define PCE1_QPHY_RX0 0x01C0E400 87 #define PCE1_QPHY_TX1 0x01C0E600 88 #define PCE1_QPHY_RX1 0x01C0E800 89 #define PCE1_QPHY_PCS_MISC 0x01C0EE00 90 91 /* PHY BCR */ 92 #define GCC_PCIE_1_PHY_BCR 0x18E01C 93 94 /* eMMC base address */ 95 #define SDC1_HC_BASE 0x007C4000 96 97 #endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ 98