1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 /** 4 * Defines the SDRAM parameter structure. 5 * 6 * Note that PLLM is used by EMC. The field names are in camel case to ease 7 * directly converting BCT config files (*.cfg) into C structure. 8 */ 9 10 #ifndef __SOC_NVIDIA_TEGRA124_SDRAM_PARAM_H__ 11 #define __SOC_NVIDIA_TEGRA124_SDRAM_PARAM_H__ 12 13 #include <stddef.h> 14 #include <stdint.h> 15 16 enum { 17 /* Specifies the memory type to be undefined */ 18 NvBootMemoryType_None = 0, 19 20 /* Specifies the memory type to be DDR SDRAM */ 21 NvBootMemoryType_Ddr = 0, 22 23 /* Specifies the memory type to be LPDDR SDRAM */ 24 NvBootMemoryType_LpDdr = 0, 25 26 /* Specifies the memory type to be DDR2 SDRAM */ 27 NvBootMemoryType_Ddr2 = 0, 28 29 /* Specifies the memory type to be LPDDR2 SDRAM */ 30 NvBootMemoryType_LpDdr2, 31 32 /* Specifies the memory type to be DDR3 SDRAM */ 33 NvBootMemoryType_Ddr3, 34 35 NvBootMemoryType_Num, 36 37 /* Specifies an entry in the ram_code table that's not in use */ 38 NvBootMemoryType_Unused = 0x7FFFFFF, 39 }; 40 41 enum { 42 BOOT_ROM_PATCH_CONTROL_ENABLE_MASK = 0x1 << 31, 43 BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT = 0, 44 BOOT_ROM_PATCH_CONTROL_OFFSET_MASK = 0x7FFFFFFF << 0, 45 BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS = 0x70000000, 46 47 EMC_ZCAL_WARM_COLD_BOOT_ENABLES_COLDBOOT_MASK = 1 << 0, 48 }; 49 50 /** 51 * Defines the SDRAM parameter structure 52 */ 53 struct sdram_params { 54 /* Specifies the type of memory device */ 55 uint32_t MemoryType; 56 57 /* MC/EMC clock source configuration */ 58 59 /* Specifies the M value for PllM */ 60 uint32_t PllMInputDivider; 61 /* Specifies the N value for PllM */ 62 uint32_t PllMFeedbackDivider; 63 /* Specifies the time to wait for PLLM to lock (in microseconds) */ 64 uint32_t PllMStableTime; 65 /* Specifies misc. control bits */ 66 uint32_t PllMSetupControl; 67 /* Enables the Div by 2 */ 68 uint32_t PllMSelectDiv2; 69 /* Powers down VCO output Level shifter */ 70 uint32_t PllMPDLshiftPh45; 71 /* Powers down VCO output Level shifter */ 72 uint32_t PllMPDLshiftPh90; 73 /* Powers down VCO output Level shifter */ 74 uint32_t PllMPDLshiftPh135; 75 /* Specifies value for Charge Pump Gain Control */ 76 uint32_t PllMKCP; 77 /* Specifies VCO gain */ 78 uint32_t PllMKVCO; 79 /* Spare BCT param */ 80 uint32_t EmcBctSpare0; 81 /* Spare BCT param */ 82 uint32_t EmcBctSpare1; 83 /* Spare BCT param */ 84 uint32_t EmcBctSpare2; 85 /* Spare BCT param */ 86 uint32_t EmcBctSpare3; 87 /* Spare BCT param */ 88 uint32_t EmcBctSpare4; 89 /* Spare BCT param */ 90 uint32_t EmcBctSpare5; 91 /* Spare BCT param */ 92 uint32_t EmcBctSpare6; 93 /* Spare BCT param */ 94 uint32_t EmcBctSpare7; 95 /* Spare BCT param */ 96 uint32_t EmcBctSpare8; 97 /* Spare BCT param */ 98 uint32_t EmcBctSpare9; 99 /* Spare BCT param */ 100 uint32_t EmcBctSpare10; 101 /* Spare BCT param */ 102 uint32_t EmcBctSpare11; 103 /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ 104 uint32_t EmcClockSource; 105 106 /* Auto-calibration of EMC pads */ 107 108 /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ 109 uint32_t EmcAutoCalInterval; 110 /* 111 * Specifies the value for EMC_AUTO_CAL_CONFIG 112 * Note: Trigger bits are set by the SDRAM code. 113 */ 114 uint32_t EmcAutoCalConfig; 115 116 /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ 117 uint32_t EmcAutoCalConfig2; 118 119 /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ 120 uint32_t EmcAutoCalConfig3; 121 122 /* 123 * Specifies the time for the calibration 124 * to stabilize (in microseconds) 125 */ 126 uint32_t EmcAutoCalWait; 127 128 /* 129 * DRAM size information 130 * Specifies the value for EMC_ADR_CFG 131 */ 132 uint32_t EmcAdrCfg; 133 134 /* 135 * Specifies the time to wait after asserting pin 136 * CKE (in microseconds) 137 */ 138 uint32_t EmcPinProgramWait; 139 /* Specifies the extra delay before/after pin RESET/CKE command */ 140 uint32_t EmcPinExtraWait; 141 /* 142 * Specifies the extra delay after the first writing 143 * of EMC_TIMING_CONTROL 144 */ 145 uint32_t EmcTimingControlWait; 146 147 /* Timing parameters required for the SDRAM */ 148 149 /* Specifies the value for EMC_RC */ 150 uint32_t EmcRc; 151 /* Specifies the value for EMC_RFC */ 152 uint32_t EmcRfc; 153 /* Specifies the value for EMC_RFC_SLR */ 154 uint32_t EmcRfcSlr; 155 /* Specifies the value for EMC_RAS */ 156 uint32_t EmcRas; 157 /* Specifies the value for EMC_RP */ 158 uint32_t EmcRp; 159 /* Specifies the value for EMC_R2R */ 160 uint32_t EmcR2r; 161 /* Specifies the value for EMC_W2W */ 162 uint32_t EmcW2w; 163 /* Specifies the value for EMC_R2W */ 164 uint32_t EmcR2w; 165 /* Specifies the value for EMC_W2R */ 166 uint32_t EmcW2r; 167 /* Specifies the value for EMC_R2P */ 168 uint32_t EmcR2p; 169 /* Specifies the value for EMC_W2P */ 170 uint32_t EmcW2p; 171 /* Specifies the value for EMC_RD_RCD */ 172 uint32_t EmcRdRcd; 173 /* Specifies the value for EMC_WR_RCD */ 174 uint32_t EmcWrRcd; 175 /* Specifies the value for EMC_RRD */ 176 uint32_t EmcRrd; 177 /* Specifies the value for EMC_REXT */ 178 uint32_t EmcRext; 179 /* Specifies the value for EMC_WEXT */ 180 uint32_t EmcWext; 181 /* Specifies the value for EMC_WDV */ 182 uint32_t EmcWdv; 183 /* Specifies the value for EMC_WDV_MASK */ 184 uint32_t EmcWdvMask; 185 /* Specifies the value for EMC_QUSE */ 186 uint32_t EmcQUse; 187 /* Specifies the value for EMC_QUSE_WIDTH */ 188 uint32_t EmcQuseWidth; 189 /* Specifies the value for EMC_IBDLY */ 190 uint32_t EmcIbdly; 191 /* Specifies the value for EMC_EINPUT */ 192 uint32_t EmcEInput; 193 /* Specifies the value for EMC_EINPUT_DURATION */ 194 uint32_t EmcEInputDuration; 195 /* Specifies the value for EMC_PUTERM_EXTRA */ 196 uint32_t EmcPutermExtra; 197 /* Specifies the value for EMC_PUTERM_WIDTH */ 198 uint32_t EmcPutermWidth; 199 /* Specifies the value for EMC_PUTERM_ADJ */ 200 uint32_t EmcPutermAdj; 201 /* Specifies the value for EMC_CDB_CNTL_1 */ 202 uint32_t EmcCdbCntl1; 203 /* Specifies the value for EMC_CDB_CNTL_2 */ 204 uint32_t EmcCdbCntl2; 205 /* Specifies the value for EMC_CDB_CNTL_3 */ 206 uint32_t EmcCdbCntl3; 207 /* Specifies the value for EMC_QRST */ 208 uint32_t EmcQRst; 209 /* Specifies the value for EMC_QSAFE */ 210 uint32_t EmcQSafe; 211 /* Specifies the value for EMC_RDV */ 212 uint32_t EmcRdv; 213 /* Specifies the value for EMC_RDV_MASK */ 214 uint32_t EmcRdvMask; 215 /* Specifies the value for EMC_QPOP */ 216 uint32_t EmcQpop; 217 /* Specifies the value for EMC_CTT */ 218 uint32_t EmcCtt; 219 /* Specifies the value for EMC_CTT_DURATION */ 220 uint32_t EmcCttDuration; 221 /* Specifies the value for EMC_REFRESH */ 222 uint32_t EmcRefresh; 223 /* Specifies the value for EMC_BURST_REFRESH_NUM */ 224 uint32_t EmcBurstRefreshNum; 225 /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ 226 uint32_t EmcPreRefreshReqCnt; 227 /* Specifies the value for EMC_PDEX2WR */ 228 uint32_t EmcPdEx2Wr; 229 /* Specifies the value for EMC_PDEX2RD */ 230 uint32_t EmcPdEx2Rd; 231 /* Specifies the value for EMC_PCHG2PDEN */ 232 uint32_t EmcPChg2Pden; 233 /* Specifies the value for EMC_ACT2PDEN */ 234 uint32_t EmcAct2Pden; 235 /* Specifies the value for EMC_AR2PDEN */ 236 uint32_t EmcAr2Pden; 237 /* Specifies the value for EMC_RW2PDEN */ 238 uint32_t EmcRw2Pden; 239 /* Specifies the value for EMC_TXSR */ 240 uint32_t EmcTxsr; 241 /* Specifies the value for EMC_TXSRDLL */ 242 uint32_t EmcTxsrDll; 243 /* Specifies the value for EMC_TCKE */ 244 uint32_t EmcTcke; 245 /* Specifies the value for EMC_TCKESR */ 246 uint32_t EmcTckesr; 247 /* Specifies the value for EMC_TPD */ 248 uint32_t EmcTpd; 249 /* Specifies the value for EMC_TFAW */ 250 uint32_t EmcTfaw; 251 /* Specifies the value for EMC_TRPAB */ 252 uint32_t EmcTrpab; 253 /* Specifies the value for EMC_TCLKSTABLE */ 254 uint32_t EmcTClkStable; 255 /* Specifies the value for EMC_TCLKSTOP */ 256 uint32_t EmcTClkStop; 257 /* Specifies the value for EMC_TREFBW */ 258 uint32_t EmcTRefBw; 259 260 /* FBIO configuration values */ 261 262 /* Specifies the value for EMC_FBIO_CFG5 */ 263 uint32_t EmcFbioCfg5; 264 /* Specifies the value for EMC_FBIO_CFG6 */ 265 uint32_t EmcFbioCfg6; 266 /* Specifies the value for EMC_FBIO_SPARE */ 267 uint32_t EmcFbioSpare; 268 269 /* Specifies the value for EMC_CFG_RSV */ 270 uint32_t EmcCfgRsv; 271 272 /* MRS command values */ 273 274 /* Specifies the value for EMC_MRS */ 275 uint32_t EmcMrs; 276 /* Specifies the MP0 command to initialize mode registers */ 277 uint32_t EmcEmrs; 278 /* Specifies the MP2 command to initialize mode registers */ 279 uint32_t EmcEmrs2; 280 /* Specifies the MP3 command to initialize mode registers */ 281 uint32_t EmcEmrs3; 282 /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ 283 uint32_t EmcMrw1; 284 /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ 285 uint32_t EmcMrw2; 286 /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ 287 uint32_t EmcMrw3; 288 /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ 289 uint32_t EmcMrw4; 290 /* 291 * Specifies the programming to extra LPDDR2 Mode Register 292 * at cold boot 293 */ 294 uint32_t EmcMrwExtra; 295 /* 296 * Specifies the programming to extra LPDDR2 Mode Register 297 * at warm boot 298 */ 299 uint32_t EmcWarmBootMrwExtra; 300 /* 301 * Specify the enable of extra Mode Register programming at 302 * warm boot 303 */ 304 uint32_t EmcWarmBootExtraModeRegWriteEnable; 305 /* 306 * Specify the enable of extra Mode Register programming at 307 * cold boot 308 */ 309 uint32_t EmcExtraModeRegWriteEnable; 310 311 /* Specifies the EMC_MRW reset command value */ 312 uint32_t EmcMrwResetCommand; 313 /* Specifies the EMC Reset wait time (in microseconds) */ 314 uint32_t EmcMrwResetNInitWait; 315 /* Specifies the value for EMC_MRS_WAIT_CNT */ 316 uint32_t EmcMrsWaitCnt; 317 /* Specifies the value for EMC_MRS_WAIT_CNT2 */ 318 uint32_t EmcMrsWaitCnt2; 319 320 /* EMC miscellaneous configurations */ 321 322 /* Specifies the value for EMC_CFG */ 323 uint32_t EmcCfg; 324 /* Specifies the value for EMC_CFG_2 */ 325 uint32_t EmcCfg2; 326 /* Specifies the pipe bypass controls */ 327 uint32_t EmcCfgPipe; 328 /* Specifies the value for EMC_DBG */ 329 uint32_t EmcDbg; 330 /* Specifies the value for EMC_CMDQ */ 331 uint32_t EmcCmdQ; 332 /* Specifies the value for EMC_MC2EMCQ */ 333 uint32_t EmcMc2EmcQ; 334 /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ 335 uint32_t EmcDynSelfRefControl; 336 337 /* Specifies the value for MEM_INIT_DONE */ 338 uint32_t AhbArbitrationXbarCtrlMemInitDone; 339 340 /* Specifies the value for EMC_CFG_DIG_DLL */ 341 uint32_t EmcCfgDigDll; 342 /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ 343 uint32_t EmcCfgDigDllPeriod; 344 /* Specifies the value of *DEV_SELECTN of various EMC registers */ 345 uint32_t EmcDevSelect; 346 347 /* Specifies the value for EMC_SEL_DPD_CTRL */ 348 uint32_t EmcSelDpdCtrl; 349 350 /* Pads trimmer delays */ 351 352 /* Specifies the value for EMC_DLL_XFORM_DQS0 */ 353 uint32_t EmcDllXformDqs0; 354 /* Specifies the value for EMC_DLL_XFORM_DQS1 */ 355 uint32_t EmcDllXformDqs1; 356 /* Specifies the value for EMC_DLL_XFORM_DQS2 */ 357 uint32_t EmcDllXformDqs2; 358 /* Specifies the value for EMC_DLL_XFORM_DQS3 */ 359 uint32_t EmcDllXformDqs3; 360 /* Specifies the value for EMC_DLL_XFORM_DQS4 */ 361 uint32_t EmcDllXformDqs4; 362 /* Specifies the value for EMC_DLL_XFORM_DQS5 */ 363 uint32_t EmcDllXformDqs5; 364 /* Specifies the value for EMC_DLL_XFORM_DQS6 */ 365 uint32_t EmcDllXformDqs6; 366 /* Specifies the value for EMC_DLL_XFORM_DQS7 */ 367 uint32_t EmcDllXformDqs7; 368 /* Specifies the value for EMC_DLL_XFORM_DQS8 */ 369 uint32_t EmcDllXformDqs8; 370 /* Specifies the value for EMC_DLL_XFORM_DQS9 */ 371 uint32_t EmcDllXformDqs9; 372 /* Specifies the value for EMC_DLL_XFORM_DQS10 */ 373 uint32_t EmcDllXformDqs10; 374 /* Specifies the value for EMC_DLL_XFORM_DQS11 */ 375 uint32_t EmcDllXformDqs11; 376 /* Specifies the value for EMC_DLL_XFORM_DQS12 */ 377 uint32_t EmcDllXformDqs12; 378 /* Specifies the value for EMC_DLL_XFORM_DQS13 */ 379 uint32_t EmcDllXformDqs13; 380 /* Specifies the value for EMC_DLL_XFORM_DQS14 */ 381 uint32_t EmcDllXformDqs14; 382 /* Specifies the value for EMC_DLL_XFORM_DQS15 */ 383 uint32_t EmcDllXformDqs15; 384 /* Specifies the value for EMC_DLL_XFORM_QUSE0 */ 385 uint32_t EmcDllXformQUse0; 386 /* Specifies the value for EMC_DLL_XFORM_QUSE1 */ 387 uint32_t EmcDllXformQUse1; 388 /* Specifies the value for EMC_DLL_XFORM_QUSE2 */ 389 uint32_t EmcDllXformQUse2; 390 /* Specifies the value for EMC_DLL_XFORM_QUSE3 */ 391 uint32_t EmcDllXformQUse3; 392 /* Specifies the value for EMC_DLL_XFORM_QUSE4 */ 393 uint32_t EmcDllXformQUse4; 394 /* Specifies the value for EMC_DLL_XFORM_QUSE5 */ 395 uint32_t EmcDllXformQUse5; 396 /* Specifies the value for EMC_DLL_XFORM_QUSE6 */ 397 uint32_t EmcDllXformQUse6; 398 /* Specifies the value for EMC_DLL_XFORM_QUSE7 */ 399 uint32_t EmcDllXformQUse7; 400 /* Specifies the value for EMC_DLL_XFORM_ADDR0 */ 401 uint32_t EmcDllXformAddr0; 402 /* Specifies the value for EMC_DLL_XFORM_ADDR1 */ 403 uint32_t EmcDllXformAddr1; 404 /* Specifies the value for EMC_DLL_XFORM_ADDR2 */ 405 uint32_t EmcDllXformAddr2; 406 /* Specifies the value for EMC_DLL_XFORM_ADDR3 */ 407 uint32_t EmcDllXformAddr3; 408 /* Specifies the value for EMC_DLL_XFORM_ADDR4 */ 409 uint32_t EmcDllXformAddr4; 410 /* Specifies the value for EMC_DLL_XFORM_ADDR5 */ 411 uint32_t EmcDllXformAddr5; 412 /* Specifies the value for EMC_DLL_XFORM_QUSE8 */ 413 uint32_t EmcDllXformQUse8; 414 /* Specifies the value for EMC_DLL_XFORM_QUSE9 */ 415 uint32_t EmcDllXformQUse9; 416 /* Specifies the value for EMC_DLL_XFORM_QUSE10 */ 417 uint32_t EmcDllXformQUse10; 418 /* Specifies the value for EMC_DLL_XFORM_QUSE11 */ 419 uint32_t EmcDllXformQUse11; 420 /* Specifies the value for EMC_DLL_XFORM_QUSE12 */ 421 uint32_t EmcDllXformQUse12; 422 /* Specifies the value for EMC_DLL_XFORM_QUSE13 */ 423 uint32_t EmcDllXformQUse13; 424 /* Specifies the value for EMC_DLL_XFORM_QUSE14 */ 425 uint32_t EmcDllXformQUse14; 426 /* Specifies the value for EMC_DLL_XFORM_QUSE15 */ 427 uint32_t EmcDllXformQUse15; 428 /* Specifies the value for EMC_DLI_TRIM_TXDQS0 */ 429 uint32_t EmcDliTrimTxDqs0; 430 /* Specifies the value for EMC_DLI_TRIM_TXDQS1 */ 431 uint32_t EmcDliTrimTxDqs1; 432 /* Specifies the value for EMC_DLI_TRIM_TXDQS2 */ 433 uint32_t EmcDliTrimTxDqs2; 434 /* Specifies the value for EMC_DLI_TRIM_TXDQS3 */ 435 uint32_t EmcDliTrimTxDqs3; 436 /* Specifies the value for EMC_DLI_TRIM_TXDQS4 */ 437 uint32_t EmcDliTrimTxDqs4; 438 /* Specifies the value for EMC_DLI_TRIM_TXDQS5 */ 439 uint32_t EmcDliTrimTxDqs5; 440 /* Specifies the value for EMC_DLI_TRIM_TXDQS6 */ 441 uint32_t EmcDliTrimTxDqs6; 442 /* Specifies the value for EMC_DLI_TRIM_TXDQS7 */ 443 uint32_t EmcDliTrimTxDqs7; 444 /* Specifies the value for EMC_DLI_TRIM_TXDQS8 */ 445 uint32_t EmcDliTrimTxDqs8; 446 /* Specifies the value for EMC_DLI_TRIM_TXDQS9 */ 447 uint32_t EmcDliTrimTxDqs9; 448 /* Specifies the value for EMC_DLI_TRIM_TXDQS10 */ 449 uint32_t EmcDliTrimTxDqs10; 450 /* Specifies the value for EMC_DLI_TRIM_TXDQS11 */ 451 uint32_t EmcDliTrimTxDqs11; 452 /* Specifies the value for EMC_DLI_TRIM_TXDQS12 */ 453 uint32_t EmcDliTrimTxDqs12; 454 /* Specifies the value for EMC_DLI_TRIM_TXDQS13 */ 455 uint32_t EmcDliTrimTxDqs13; 456 /* Specifies the value for EMC_DLI_TRIM_TXDQS14 */ 457 uint32_t EmcDliTrimTxDqs14; 458 /* Specifies the value for EMC_DLI_TRIM_TXDQS15 */ 459 uint32_t EmcDliTrimTxDqs15; 460 /* Specifies the value for EMC_DLL_XFORM_DQ0 */ 461 uint32_t EmcDllXformDq0; 462 /* Specifies the value for EMC_DLL_XFORM_DQ1 */ 463 uint32_t EmcDllXformDq1; 464 /* Specifies the value for EMC_DLL_XFORM_DQ2 */ 465 uint32_t EmcDllXformDq2; 466 /* Specifies the value for EMC_DLL_XFORM_DQ3 */ 467 uint32_t EmcDllXformDq3; 468 /* Specifies the value for EMC_DLL_XFORM_DQ4 */ 469 uint32_t EmcDllXformDq4; 470 /* Specifies the value for EMC_DLL_XFORM_DQ5 */ 471 uint32_t EmcDllXformDq5; 472 /* Specifies the value for EMC_DLL_XFORM_DQ6 */ 473 uint32_t EmcDllXformDq6; 474 /* Specifies the value for EMC_DLL_XFORM_DQ7 */ 475 uint32_t EmcDllXformDq7; 476 477 /* 478 * Specifies the delay after asserting CKE pin during a WarmBoot0 479 * sequence (in microseconds) 480 */ 481 uint32_t WarmBootWait; 482 483 /* Specifies the value for EMC_CTT_TERM_CTRL */ 484 uint32_t EmcCttTermCtrl; 485 486 /* Specifies the value for EMC_ODT_WRITE */ 487 uint32_t EmcOdtWrite; 488 /* Specifies the value for EMC_ODT_WRITE */ 489 uint32_t EmcOdtRead; 490 491 /* Periodic ZQ calibration */ 492 493 /* 494 * Specifies the value for EMC_ZCAL_INTERVAL 495 * Value 0 disables ZQ calibration 496 */ 497 uint32_t EmcZcalInterval; 498 /* Specifies the value for EMC_ZCAL_WAIT_CNT */ 499 uint32_t EmcZcalWaitCnt; 500 /* Specifies the value for EMC_ZCAL_MRW_CMD */ 501 uint32_t EmcZcalMrwCmd; 502 503 /* DRAM initialization sequence flow control */ 504 505 /* Specifies the MRS command value for resetting DLL */ 506 uint32_t EmcMrsResetDll; 507 /* Specifies the command for ZQ initialization of device 0 */ 508 uint32_t EmcZcalInitDev0; 509 /* Specifies the command for ZQ initialization of device 1 */ 510 uint32_t EmcZcalInitDev1; 511 /* 512 * Specifies the wait time after programming a ZQ initialization 513 * command (in microseconds) 514 */ 515 uint32_t EmcZcalInitWait; 516 /* 517 * Specifies the enable for ZQ calibration at cold boot [bit 0] 518 * and warm boot [bit 1] 519 */ 520 uint32_t EmcZcalWarmColdBootEnables; 521 522 /* 523 * Specifies the MRW command to LPDDR2 for ZQ calibration 524 * on warmboot 525 */ 526 /* Is issued to both devices separately */ 527 uint32_t EmcMrwLpddr2ZcalWarmBoot; 528 /* 529 * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot 530 * Is issued to both devices separately 531 */ 532 uint32_t EmcZqCalDdr3WarmBoot; 533 /* 534 * Specifies the wait time for ZQ calibration on warmboot 535 * (in microseconds) 536 */ 537 uint32_t EmcZcalWarmBootWait; 538 /* 539 * Specifies the enable for DRAM Mode Register programming 540 * at warm boot 541 */ 542 uint32_t EmcMrsWarmBootEnable; 543 /* 544 * Specifies the wait time after sending an MRS DLL reset command 545 * in microseconds) 546 */ 547 uint32_t EmcMrsResetDllWait; 548 /* Specifies the extra MRS command to initialize mode registers */ 549 uint32_t EmcMrsExtra; 550 /* Specifies the extra MRS command at warm boot */ 551 uint32_t EmcWarmBootMrsExtra; 552 /* Specifies the EMRS command to enable the DDR2 DLL */ 553 uint32_t EmcEmrsDdr2DllEnable; 554 /* Specifies the MRS command to reset the DDR2 DLL */ 555 uint32_t EmcMrsDdr2DllReset; 556 /* Specifies the EMRS command to set OCD calibration */ 557 uint32_t EmcEmrsDdr2OcdCalib; 558 /* 559 * Specifies the wait between initializing DDR and setting OCD 560 * calibration (in microseconds) 561 */ 562 uint32_t EmcDdr2Wait; 563 /* Specifies the value for EMC_CLKEN_OVERRIDE */ 564 uint32_t EmcClkenOverride; 565 /* Specifies the value for MC_DIS_EXTRA_SNAP_LEVELS */ 566 uint32_t McDisExtraSnapLevels; 567 /* 568 * Specifies LOG2 of the extra refresh numbers after booting 569 * Program 0 to disable 570 */ 571 uint32_t EmcExtraRefreshNum; 572 /* Specifies the master override for all EMC clocks */ 573 uint32_t EmcClkenOverrideAllWarmBoot; 574 /* Specifies the master override for all MC clocks */ 575 uint32_t McClkenOverrideAllWarmBoot; 576 /* Specifies digital dll period, choosing between 4 to 64 ms */ 577 uint32_t EmcCfgDigDllPeriodWarmBoot; 578 579 /* Pad controls */ 580 581 /* Specifies the value for PMC_VDDP_SEL */ 582 uint32_t PmcVddpSel; 583 /* Specifies the wait time after programming PMC_VDDP_SEL */ 584 uint32_t PmcVddpSelWait; 585 /* Specifies the value for PMC_DDR_PWR */ 586 uint32_t PmcDdrPwr; 587 /* Specifies the value for PMC_DDR_CFG */ 588 uint32_t PmcDdrCfg; 589 /* Specifies the value for PMC_IO_DPD3_REQ */ 590 uint32_t PmcIoDpd3Req; 591 /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ 592 uint32_t PmcIoDpd3ReqWait; 593 /* Specifies the value for PMC_REG_SHORT */ 594 uint32_t PmcRegShort; 595 /* Specifies the value for PMC_NO_IOPOWER */ 596 uint32_t PmcNoIoPower; 597 /* Specifies the wait time after programming PMC_POR_DPD_CTRL */ 598 uint32_t PmcPorDpdCtrlWait; 599 /* Specifies the value for EMC_XM2CMDPADCTRL */ 600 uint32_t EmcXm2CmdPadCtrl; 601 /* Specifies the value for EMC_XM2CMDPADCTRL2 */ 602 uint32_t EmcXm2CmdPadCtrl2; 603 /* Specifies the value for EMC_XM2CMDPADCTRL3 */ 604 uint32_t EmcXm2CmdPadCtrl3; 605 /* Specifies the value for EMC_XM2CMDPADCTRL4 */ 606 uint32_t EmcXm2CmdPadCtrl4; 607 /* Specifies the value for EMC_XM2CMDPADCTRL5 */ 608 uint32_t EmcXm2CmdPadCtrl5; 609 /* Specifies the value for EMC_XM2DQSPADCTRL */ 610 uint32_t EmcXm2DqsPadCtrl; 611 /* Specifies the value for EMC_XM2DQSPADCTRL2 */ 612 uint32_t EmcXm2DqsPadCtrl2; 613 /* Specifies the value for EMC_XM2DQSPADCTRL3 */ 614 uint32_t EmcXm2DqsPadCtrl3; 615 /* Specifies the value for EMC_XM2DQSPADCTRL4 */ 616 uint32_t EmcXm2DqsPadCtrl4; 617 /* Specifies the value for EMC_XM2DQSPADCTRL5 */ 618 uint32_t EmcXm2DqsPadCtrl5; 619 /* Specifies the value for EMC_XM2DQSPADCTRL6 */ 620 uint32_t EmcXm2DqsPadCtrl6; 621 /* Specifies the value for EMC_XM2DQPADCTRL */ 622 uint32_t EmcXm2DqPadCtrl; 623 /* Specifies the value for EMC_XM2DQPADCTRL2 */ 624 uint32_t EmcXm2DqPadCtrl2; 625 /* Specifies the value for EMC_XM2DQPADCTRL3 */ 626 uint32_t EmcXm2DqPadCtrl3; 627 /* Specifies the value for EMC_XM2CLKPADCTRL */ 628 uint32_t EmcXm2ClkPadCtrl; 629 /* Specifies the value for EMC_XM2CLKPADCTRL2 */ 630 uint32_t EmcXm2ClkPadCtrl2; 631 /* Specifies the value for EMC_XM2COMPPADCTRL */ 632 uint32_t EmcXm2CompPadCtrl; 633 /* Specifies the value for EMC_XM2VTTGENPADCTRL */ 634 uint32_t EmcXm2VttGenPadCtrl; 635 /* Specifies the value for EMC_XM2VTTGENPADCTRL2 */ 636 uint32_t EmcXm2VttGenPadCtrl2; 637 /* Specifies the value for EMC_XM2VTTGENPADCTRL3 */ 638 uint32_t EmcXm2VttGenPadCtrl3; 639 /* Specifies the value for EMC_ACPD_CONTROL */ 640 uint32_t EmcAcpdControl; 641 642 /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */ 643 uint32_t EmcSwizzleRank0ByteCfg; 644 /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ 645 uint32_t EmcSwizzleRank0Byte0; 646 /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ 647 uint32_t EmcSwizzleRank0Byte1; 648 /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ 649 uint32_t EmcSwizzleRank0Byte2; 650 /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ 651 uint32_t EmcSwizzleRank0Byte3; 652 /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */ 653 uint32_t EmcSwizzleRank1ByteCfg; 654 /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ 655 uint32_t EmcSwizzleRank1Byte0; 656 /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ 657 uint32_t EmcSwizzleRank1Byte1; 658 /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ 659 uint32_t EmcSwizzleRank1Byte2; 660 /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ 661 uint32_t EmcSwizzleRank1Byte3; 662 663 /* Specifies the value for EMC_DSR_VTTGEN_DRV */ 664 uint32_t EmcDsrVttgenDrv; 665 666 /* Specifies the value for EMC_TXDSRVTTGEN */ 667 uint32_t EmcTxdsrvttgen; 668 /* Specifies the value for EMC_BGBIAS_CTL */ 669 uint32_t EmcBgbiasCtl0; 670 671 /* DRAM size information */ 672 673 /* Specifies the value for MC_EMEM_ADR_CFG */ 674 uint32_t McEmemAdrCfg; 675 /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ 676 uint32_t McEmemAdrCfgDev0; 677 /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ 678 uint32_t McEmemAdrCfgDev1; 679 /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */ 680 uint32_t McEmemAdrCfgBankMask0; 681 /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ 682 uint32_t McEmemAdrCfgBankMask1; 683 /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ 684 uint32_t McEmemAdrCfgBankMask2; 685 /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG3 */ 686 uint32_t McEmemAdrCfgBankSwizzle3; 687 688 /* 689 * Specifies the value for MC_EMEM_CFG which holds the external memory 690 * size (in KBytes) 691 */ 692 uint32_t McEmemCfg; 693 694 /* MC arbitration configuration */ 695 696 /* Specifies the value for MC_EMEM_ARB_CFG */ 697 uint32_t McEmemArbCfg; 698 /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ 699 uint32_t McEmemArbOutstandingReq; 700 /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ 701 uint32_t McEmemArbTimingRcd; 702 /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ 703 uint32_t McEmemArbTimingRp; 704 /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ 705 uint32_t McEmemArbTimingRc; 706 /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ 707 uint32_t McEmemArbTimingRas; 708 /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ 709 uint32_t McEmemArbTimingFaw; 710 /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ 711 uint32_t McEmemArbTimingRrd; 712 /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ 713 uint32_t McEmemArbTimingRap2Pre; 714 /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ 715 uint32_t McEmemArbTimingWap2Pre; 716 /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ 717 uint32_t McEmemArbTimingR2R; 718 /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ 719 uint32_t McEmemArbTimingW2W; 720 /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ 721 uint32_t McEmemArbTimingR2W; 722 /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ 723 uint32_t McEmemArbTimingW2R; 724 /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ 725 uint32_t McEmemArbDaTurns; 726 /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ 727 uint32_t McEmemArbDaCovers; 728 /* Specifies the value for MC_EMEM_ARB_MISC0 */ 729 uint32_t McEmemArbMisc0; 730 /* Specifies the value for MC_EMEM_ARB_MISC1 */ 731 uint32_t McEmemArbMisc1; 732 /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ 733 uint32_t McEmemArbRing1Throttle; 734 /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ 735 uint32_t McEmemArbOverride; 736 /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ 737 uint32_t McEmemArbOverride1; 738 /* Specifies the value for MC_EMEM_ARB_RSV */ 739 uint32_t McEmemArbRsv; 740 741 /* Specifies the value for MC_CLKEN_OVERRIDE */ 742 uint32_t McClkenOverride; 743 744 /* Specifies the value for MC_STAT_CONTROL */ 745 uint32_t McStatControl; 746 /* Specifies the value for MC_DISPLAY_SNAP_RING */ 747 uint32_t McDisplaySnapRing; 748 /* Specifies the value for MC_VIDEO_PROTECT_BOM */ 749 uint32_t McVideoProtectBom; 750 /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ 751 uint32_t McVideoProtectBomAdrHi; 752 /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ 753 uint32_t McVideoProtectSizeMb; 754 /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ 755 uint32_t McVideoProtectVprOverride; 756 /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ 757 uint32_t McVideoProtectVprOverride1; 758 /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ 759 uint32_t McVideoProtectGpuOverride0; 760 /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ 761 uint32_t McVideoProtectGpuOverride1; 762 /* Specifies the value for MC_SEC_CARVEOUT_BOM */ 763 uint32_t McSecCarveoutBom; 764 /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ 765 uint32_t McSecCarveoutAdrHi; 766 /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ 767 uint32_t McSecCarveoutSizeMb; 768 /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */ 769 uint32_t McVideoProtectWriteAccess; 770 /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */ 771 uint32_t McSecCarveoutProtectWriteAccess; 772 773 /* Specifies enable for CA training */ 774 uint32_t EmcCaTrainingEnable; 775 /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL1 */ 776 uint32_t EmcCaTrainingTimingCntl1; 777 /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL2 */ 778 uint32_t EmcCaTrainingTimingCntl2; 779 /* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */ 780 uint32_t SwizzleRankByteEncode; 781 /* Specifies enable and offset for patched boot ROM write */ 782 uint32_t BootRomPatchControl; 783 /* Specifies data for patched boot ROM write */ 784 uint32_t BootRomPatchData; 785 /* Specifies the value for MC_MTS_CARVEOUT_BOM */ 786 uint32_t McMtsCarveoutBom; 787 /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ 788 uint32_t McMtsCarveoutAdrHi; 789 /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ 790 uint32_t McMtsCarveoutSizeMb; 791 /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ 792 uint32_t McMtsCarveoutRegCtrl; 793 794 /* End of generated code by warmboot_code_gen */ 795 }; 796 797 check_member(sdram_params, McMtsCarveoutRegCtrl, 0x4d0); 798 799 #endif /* __SOC_NVIDIA_TEGRA124_SDRAM_PARAM_H__ */ 800