1 /* SPDX-License-Identifier: MIT */ 2 3 #ifndef _I915_REG_H_ 4 #define _I915_REG_H_ 5 6 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 7 #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) 8 9 #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) 10 11 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) 12 #define _MASKED_BIT_DISABLE(a) ((a) << 16) 13 14 /* 15 * The Bridge device's PCI config space has information about the 16 * fb aperture size and the amount of pre-reserved memory. 17 * This is all handled in the intel-gtt.ko module. i915.ko only 18 * cares about the vga bit for the vga arbiter. 19 */ 20 #define INTEL_GMCH_CTRL 0x52 21 #define INTEL_GMCH_VGA_DISABLE (1 << 1) 22 #define SNB_GMCH_CTRL 0x50 23 #define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */ 24 #define SNB_GMCH_GGMS_MASK 0x3 25 #define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */ 26 #define SNB_GMCH_GMS_MASK 0x1f 27 #define IVB_GMCH_GMS_SHIFT 4 28 #define IVB_GMCH_GMS_MASK 0xf 29 30 /* PCI config space */ 31 32 #define HPLLCC 0xc0 /* 855 only */ 33 #define GC_CLOCK_CONTROL_MASK (0xf << 0) 34 #define GC_CLOCK_133_200 (0 << 0) 35 #define GC_CLOCK_100_200 (1 << 0) 36 #define GC_CLOCK_100_133 (2 << 0) 37 #define GC_CLOCK_166_250 (3 << 0) 38 #define GCFGC2 0xda 39 #define GCFGC 0xf0 /* 915+ only */ 40 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 41 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 42 #define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) 43 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 44 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 45 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 46 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 47 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 48 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 49 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 50 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 51 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 52 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 53 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 54 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 55 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 56 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 57 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 58 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 59 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 60 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 61 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 62 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 63 #define LBB 0xf4 64 65 /* Graphics reset regs */ 66 #define I965_GDRST 0xc0 /* PCI config register */ 67 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ 68 #define GRDOM_FULL (0<<2) 69 #define GRDOM_RENDER (1<<2) 70 #define GRDOM_MEDIA (3<<2) 71 #define GRDOM_RESET_ENABLE (1<<0) 72 73 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ 74 #define GEN6_MBC_SNPCR_SHIFT 21 75 #define GEN6_MBC_SNPCR_MASK (3<<21) 76 #define GEN6_MBC_SNPCR_MAX (0<<21) 77 #define GEN6_MBC_SNPCR_MED (1<<21) 78 #define GEN6_MBC_SNPCR_LOW (2<<21) 79 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ 80 81 #define GEN6_MBCTL 0x0907c 82 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 83 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 84 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 85 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 86 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 87 88 #define GEN6_GDRST 0x941c 89 #define GEN6_GRDOM_FULL (1 << 0) 90 #define GEN6_GRDOM_RENDER (1 << 1) 91 #define GEN6_GRDOM_MEDIA (1 << 2) 92 #define GEN6_GRDOM_BLT (1 << 3) 93 94 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) 95 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) 96 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) 97 #define PP_DIR_DCLV_2G 0xffffffff 98 99 #define GAM_ECOCHK 0x4090 100 #define ECOCHK_SNB_BIT (1<<10) 101 #define ECOCHK_PPGTT_CACHE64B (0x3<<3) 102 #define ECOCHK_PPGTT_CACHE4B (0x0<<3) 103 104 #define GAC_ECO_BITS 0x14090 105 #define ECOBITS_PPGTT_CACHE64B (3<<8) 106 #define ECOBITS_PPGTT_CACHE4B (0<<8) 107 108 #define GAB_CTL 0x24000 109 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) 110 111 /* VGA stuff */ 112 113 #define VGA_ST01_MDA 0x3ba 114 #define VGA_ST01_CGA 0x3da 115 116 #define VGA_MSR_WRITE 0x3c2 117 #define VGA_MSR_READ 0x3cc 118 #define VGA_MSR_MEM_EN (1<<1) 119 #define VGA_MSR_CGA_MODE (1<<0) 120 121 #define VGA_SR_INDEX 0x3c4 122 #define VGA_SR_DATA 0x3c5 123 124 #define VGA_AR_INDEX 0x3c0 125 #define VGA_AR_VID_EN (1<<5) 126 #define VGA_AR_DATA_WRITE 0x3c0 127 #define VGA_AR_DATA_READ 0x3c1 128 129 #define VGA_GR_INDEX 0x3ce 130 #define VGA_GR_DATA 0x3cf 131 /* GR05 */ 132 #define VGA_GR_MEM_READ_MODE_SHIFT 3 133 #define VGA_GR_MEM_READ_MODE_PLANE 1 134 /* GR06 */ 135 #define VGA_GR_MEM_MODE_MASK 0xc 136 #define VGA_GR_MEM_MODE_SHIFT 2 137 #define VGA_GR_MEM_A0000_AFFFF 0 138 #define VGA_GR_MEM_A0000_BFFFF 1 139 #define VGA_GR_MEM_B0000_B7FFF 2 140 #define VGA_GR_MEM_B0000_BFFFF 3 141 142 #define VGA_DACMASK 0x3c6 143 #define VGA_DACRX 0x3c7 144 #define VGA_DACWX 0x3c8 145 #define VGA_DACDATA 0x3c9 146 147 #define VGA_CR_INDEX_MDA 0x3b4 148 #define VGA_CR_DATA_MDA 0x3b5 149 #define VGA_CR_INDEX_CGA 0x3d4 150 #define VGA_CR_DATA_CGA 0x3d5 151 152 /* 153 * Memory interface instructions used by the kernel 154 */ 155 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 156 157 #define MI_NOOP MI_INSTR(0, 0) 158 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 159 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 160 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 161 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 162 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 163 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 164 #define MI_FLUSH MI_INSTR(0x04, 0) 165 #define MI_READ_FLUSH (1 << 0) 166 #define MI_EXE_FLUSH (1 << 1) 167 #define MI_NO_WRITE_FLUSH (1 << 2) 168 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 169 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 170 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 171 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 172 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) 173 #define MI_SUSPEND_FLUSH_EN (1<<0) 174 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 175 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) 176 #define MI_OVERLAY_CONTINUE (0x0<<21) 177 #define MI_OVERLAY_ON (0x1<<21) 178 #define MI_OVERLAY_OFF (0x2<<21) 179 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 180 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 181 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 182 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 183 /* IVB has funny definitions for which plane to flip. */ 184 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) 185 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) 186 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) 187 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) 188 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) 189 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) 190 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) 191 #define MI_ARB_ENABLE (1<<0) 192 #define MI_ARB_DISABLE (0<<0) 193 194 #define MI_SET_CONTEXT MI_INSTR(0x18, 0) 195 #define MI_MM_SPACE_GTT (1<<8) 196 #define MI_MM_SPACE_PHYSICAL (0<<8) 197 #define MI_SAVE_EXT_STATE_EN (1<<3) 198 #define MI_RESTORE_EXT_STATE_EN (1<<2) 199 #define MI_FORCE_RESTORE (1<<1) 200 #define MI_RESTORE_INHIBIT (1<<0) 201 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 202 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 203 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 204 #define MI_STORE_DWORD_INDEX_SHIFT 2 205 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: 206 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw 207 * simply ignores the register load under certain conditions. 208 * - One can actually load arbitrary many arbitrary registers: Simply issue x 209 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 210 */ 211 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) 212 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ 213 #define MI_FLUSH_DW_STORE_INDEX (1<<21) 214 #define MI_INVALIDATE_TLB (1<<18) 215 #define MI_FLUSH_DW_OP_STOREDW (1<<14) 216 #define MI_INVALIDATE_BSD (1<<7) 217 #define MI_FLUSH_DW_USE_GTT (1<<2) 218 #define MI_FLUSH_DW_USE_PPGTT (0<<2) 219 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 220 #define MI_BATCH_NON_SECURE (1) 221 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ 222 #define MI_BATCH_NON_SECURE_I965 (1<<8) 223 #define MI_BATCH_PPGTT_HSW (1<<8) 224 #define MI_BATCH_NON_SECURE_HSW (1<<13) 225 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 226 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ 227 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ 228 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) 229 #define MI_SEMAPHORE_UPDATE (1<<21) 230 #define MI_SEMAPHORE_COMPARE (1<<20) 231 #define MI_SEMAPHORE_REGISTER (1<<18) 232 #define MI_SEMAPHORE_SYNC_RV (2<<16) 233 #define MI_SEMAPHORE_SYNC_RB (0<<16) 234 #define MI_SEMAPHORE_SYNC_VR (0<<16) 235 #define MI_SEMAPHORE_SYNC_VB (2<<16) 236 #define MI_SEMAPHORE_SYNC_BR (2<<16) 237 #define MI_SEMAPHORE_SYNC_BV (0<<16) 238 #define MI_SEMAPHORE_SYNC_INVALID (1<<0) 239 /* 240 * 3D instructions used by the kernel 241 */ 242 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 243 244 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 245 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 246 #define SC_UPDATE_SCISSOR (0x1<<1) 247 #define SC_ENABLE_MASK (0x1<<0) 248 #define SC_ENABLE (0x1<<0) 249 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 250 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 251 #define SCI_YMIN_MASK (0xffff<<16) 252 #define SCI_XMIN_MASK (0xffff<<0) 253 #define SCI_YMAX_MASK (0xffff<<16) 254 #define SCI_XMAX_MASK (0xffff<<0) 255 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 256 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 257 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 258 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 259 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 260 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 261 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 262 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 263 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 264 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 265 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 266 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 267 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 268 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 269 #define BLT_DEPTH_8 (0<<24) 270 #define BLT_DEPTH_16_565 (1<<24) 271 #define BLT_DEPTH_16_1555 (2<<24) 272 #define BLT_DEPTH_32 (3<<24) 273 #define BLT_ROP_GXCOPY (0xcc<<16) 274 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 275 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 276 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 277 #define ASYNC_FLIP (1<<22) 278 #define DISPLAY_PLANE_A (0<<20) 279 #define DISPLAY_PLANE_B (1<<20) 280 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) 281 #define PIPE_CONTROL_CS_STALL (1<<20) 282 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) 283 #define PIPE_CONTROL_QW_WRITE (1<<14) 284 #define PIPE_CONTROL_DEPTH_STALL (1<<13) 285 #define PIPE_CONTROL_WRITE_FLUSH (1<<12) 286 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ 287 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ 288 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ 289 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) 290 #define PIPE_CONTROL_NOTIFY (1<<8) 291 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) 292 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) 293 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) 294 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) 295 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) 296 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 297 298 /* 299 * Reset registers 300 */ 301 #define DEBUG_RESET_I830 0x6070 302 #define DEBUG_RESET_FULL (1<<7) 303 #define DEBUG_RESET_RENDER (1<<8) 304 #define DEBUG_RESET_DISPLAY (1<<9) 305 306 /* 307 * DPIO - a special bus for various display related registers to hide behind: 308 * 0x800c: m1, m2, n, p1, p2, k dividers 309 * 0x8014: REF and SFR select 310 * 0x8014: N divider, VCO select 311 * 0x801c/3c: core clock bits 312 * 0x8048/68: low pass filter coefficients 313 * 0x8100: fast clock controls 314 */ 315 #define DPIO_PKT 0x2100 316 #define DPIO_RID (0<<24) 317 #define DPIO_OP_WRITE (1<<16) 318 #define DPIO_OP_READ (0<<16) 319 #define DPIO_PORTID (0x12<<8) 320 #define DPIO_BYTE (0xf<<4) 321 #define DPIO_BUSY (1<<0) /* status only */ 322 #define DPIO_DATA 0x2104 323 #define DPIO_REG 0x2108 324 #define DPIO_CTL 0x2110 325 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ 326 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ 327 #define DPIO_SFR_BYPASS (1<<1) 328 #define DPIO_RESET (1<<0) 329 330 #define _DPIO_DIV_A 0x800c 331 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 332 #define DPIO_K_SHIFT (24) /* 4 bits */ 333 #define DPIO_P1_SHIFT (21) /* 3 bits */ 334 #define DPIO_P2_SHIFT (16) /* 5 bits */ 335 #define DPIO_N_SHIFT (12) /* 4 bits */ 336 #define DPIO_ENABLE_CALIBRATION (1<<11) 337 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 338 #define DPIO_M2DIV_MASK 0xff 339 #define _DPIO_DIV_B 0x802c 340 #define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B) 341 342 #define _DPIO_REFSFR_A 0x8014 343 #define DPIO_REFSEL_OVERRIDE 27 344 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 345 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 346 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 347 #define DPIO_PLL_REFCLK_SEL_MASK 3 348 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 349 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 350 #define _DPIO_REFSFR_B 0x8034 351 #define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B) 352 353 #define _DPIO_CORE_CLK_A 0x801c 354 #define _DPIO_CORE_CLK_B 0x803c 355 #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B) 356 357 #define _DPIO_LFP_COEFF_A 0x8048 358 #define _DPIO_LFP_COEFF_B 0x8068 359 #define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B) 360 361 #define DPIO_FASTCLK_DISABLE 0x8100 362 363 #define DPIO_DATA_CHANNEL1 0x8220 364 #define DPIO_DATA_CHANNEL2 0x8420 365 366 /* 367 * Fence registers 368 */ 369 #define FENCE_REG_830_0 0x2000 370 #define FENCE_REG_945_8 0x3000 371 #define I830_FENCE_START_MASK 0x07f80000 372 #define I830_FENCE_TILING_Y_SHIFT 12 373 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 374 #define I830_FENCE_PITCH_SHIFT 4 375 #define I830_FENCE_REG_VALID (1<<0) 376 #define I915_FENCE_MAX_PITCH_VAL 4 377 #define I830_FENCE_MAX_PITCH_VAL 6 378 #define I830_FENCE_MAX_SIZE_VAL (1<<8) 379 380 #define I915_FENCE_START_MASK 0x0ff00000 381 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 382 383 #define FENCE_REG_965_0 0x03000 384 #define I965_FENCE_PITCH_SHIFT 2 385 #define I965_FENCE_TILING_Y_SHIFT 1 386 #define I965_FENCE_REG_VALID (1<<0) 387 #define I965_FENCE_MAX_PITCH_VAL 0x0400 388 389 #define FENCE_REG_SANDYBRIDGE_0 0x100000 390 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 391 392 /* control register for cpu gtt access */ 393 #define TILECTL 0x101000 394 #define TILECTL_SWZCTL (1 << 0) 395 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 396 #define TILECTL_BACKSNOOP_DIS (1 << 3) 397 398 /* 399 * Instruction and interrupt control regs 400 */ 401 #define PGTBL_ER 0x02024 402 #define RENDER_RING_BASE 0x02000 403 #define BSD_RING_BASE 0x04000 404 #define GEN6_BSD_RING_BASE 0x12000 405 #define BLT_RING_BASE 0x22000 406 #define RING_TAIL(base) ((base)+0x30) 407 #define RING_HEAD(base) ((base)+0x34) 408 #define RING_START(base) ((base)+0x38) 409 #define RING_CTL(base) ((base)+0x3c) 410 #define RING_SYNC_0(base) ((base)+0x40) 411 #define RING_SYNC_1(base) ((base)+0x44) 412 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 413 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 414 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 415 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 416 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 417 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 418 #define RING_MAX_IDLE(base) ((base)+0x54) 419 #define RING_HWS_PGA(base) ((base)+0x80) 420 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) 421 #define ARB_MODE 0x04030 422 #define ARB_MODE_SWIZZLE_SNB (1<<4) 423 #define ARB_MODE_SWIZZLE_IVB (1<<5) 424 #define RENDER_HWS_PGA_GEN7 (0x04080) 425 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) 426 #define DONE_REG 0x40b0 427 #define BSD_HWS_PGA_GEN7 (0x04180) 428 #define BLT_HWS_PGA_GEN7 (0x04280) 429 #define RING_ACTHD(base) ((base)+0x74) 430 #define RING_NOPID(base) ((base)+0x94) 431 #define RING_IMR(base) ((base)+0xa8) 432 #define RING_TIMESTAMP(base) ((base)+0x358) 433 #define TAIL_ADDR 0x001FFFF8 434 #define HEAD_WRAP_COUNT 0xFFE00000 435 #define HEAD_WRAP_ONE 0x00200000 436 #define HEAD_ADDR 0x001FFFFC 437 #define RING_NR_PAGES 0x001FF000 438 #define RING_REPORT_MASK 0x00000006 439 #define RING_REPORT_64K 0x00000002 440 #define RING_REPORT_128K 0x00000004 441 #define RING_NO_REPORT 0x00000000 442 #define RING_VALID_MASK 0x00000001 443 #define RING_VALID 0x00000001 444 #define RING_INVALID 0x00000000 445 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ 446 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ 447 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ 448 #define IPEIR_I965 0x02064 449 #define IPEHR_I965 0x02068 450 #define INSTDONE_I965 0x0206c 451 #define GEN7_INSTDONE_1 0x0206c 452 #define GEN7_SC_INSTDONE 0x07100 453 #define GEN7_SAMPLER_INSTDONE 0x0e160 454 #define GEN7_ROW_INSTDONE 0x0e164 455 #define I915_NUM_INSTDONE_REG 4 456 #define RING_IPEIR(base) ((base)+0x64) 457 #define RING_IPEHR(base) ((base)+0x68) 458 #define RING_INSTDONE(base) ((base)+0x6c) 459 #define RING_INSTPS(base) ((base)+0x70) 460 #define RING_DMA_FADD(base) ((base)+0x78) 461 #define RING_INSTPM(base) ((base)+0xc0) 462 #define INSTPS 0x02070 /* 965+ only */ 463 #define INSTDONE1 0x0207c /* 965+ only */ 464 #define ACTHD_I965 0x02074 465 #define HWS_PGA 0x02080 466 #define HWS_ADDRESS_MASK 0xfffff000 467 #define HWS_START_ADDRESS_SHIFT 4 468 #define PWRCTXA 0x2088 /* 965GM+ only */ 469 #define PWRCTX_EN (1<<0) 470 #define IPEIR 0x02088 471 #define IPEHR 0x0208c 472 #define INSTDONE 0x02090 473 #define NOPID 0x02094 474 #define HWSTAM 0x02098 475 #define DMA_FADD_I8XX 0x020d0 476 477 #define ERROR_GEN6 0x040a0 478 #define GEN7_ERR_INT 0x44040 479 #define ERR_INT_MMIO_UNCLAIMED (1<<13) 480 481 #define DERRMR 0x44050 482 483 /* GM45+ chicken bits -- debug workaround bits that may be required 484 * for various sorts of correct behavior. The top 16 bits of each are 485 * the enables for writing to the corresponding low bit. 486 */ 487 #define _3D_CHICKEN 0x02084 488 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) 489 #define _3D_CHICKEN2 0x0208c 490 /* Disables pipelining of read flushes past the SF-WIZ interface. 491 * Required on all Ironlake steppings according to the B-Spec, but the 492 * particular danger of not doing so is not specified. 493 */ 494 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 495 #define _3D_CHICKEN3 0x02090 496 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) 497 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) 498 499 #define MI_MODE 0x0209c 500 # define VS_TIMER_DISPATCH (1 << 6) 501 # define MI_FLUSH_ENABLE (1 << 12) 502 # define ASYNC_FLIP_PERF_DISABLE (1 << 14) 503 504 #define GEN6_GT_MODE 0x20d0 505 #define GEN6_GT_MODE_HI (1 << 9) 506 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) 507 508 #define GFX_MODE 0x02520 509 #define GFX_MODE_GEN7 0x0229c 510 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) 511 #define GFX_RUN_LIST_ENABLE (1<<15) 512 #define GFX_TLB_INVALIDATE_ALWAYS (1<<13) 513 #define GFX_SURFACE_FAULT_ENABLE (1<<12) 514 #define GFX_REPLAY_MODE (1<<11) 515 #define GFX_PSMI_GRANULARITY (1<<10) 516 #define GFX_PPGTT_ENABLE (1<<9) 517 518 #define VLV_DISPLAY_BASE 0x180000 519 520 #define SCPD0 0x0209c /* 915+ only */ 521 #define IER 0x020a0 522 #define IIR 0x020a4 523 #define IMR 0x020a8 524 #define ISR 0x020ac 525 #define VLV_GUNIT_CLOCK_GATE 0x182060 526 #define GCFG_DIS (1<<8) 527 #define VLV_IIR_RW 0x182084 528 #define VLV_IER 0x1820a0 529 #define VLV_IIR 0x1820a4 530 #define VLV_IMR 0x1820a8 531 #define VLV_ISR 0x1820ac 532 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 533 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 534 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 535 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ 536 #define I915_HWB_OOM_INTERRUPT (1<<13) 537 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 538 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 539 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 540 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 541 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 542 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 543 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 544 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 545 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 546 #define I915_DEBUG_INTERRUPT (1<<2) 547 #define I915_USER_INTERRUPT (1<<1) 548 #define I915_ASLE_INTERRUPT (1<<0) 549 #define I915_BSD_USER_INTERRUPT (1<<25) 550 #define EIR 0x020b0 551 #define EMR 0x020b4 552 #define GM45_ERROR_PAGE_TABLE (1<<5) 553 #define GM45_ERROR_MEM_PRIV (1<<4) 554 #define I915_ERROR_PAGE_TABLE (1<<4) 555 #define GM45_ERROR_CP_PRIV (1<<3) 556 #define I915_ERROR_MEMORY_REFRESH (1<<1) 557 #define I915_ERROR_INSTRUCTION (1<<0) 558 #define INSTPM 0x020c0 559 #define INSTPM_SELF_EN (1<<12) /* 915GM only */ 560 #define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts 561 will not assert AGPBUSY# and will only 562 be delivered when out of C3. */ 563 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ 564 #define ACTHD 0x020c8 565 #define FW_BLC 0x020d8 566 #define FW_BLC2 0x020dc 567 #define FW_BLC_SELF 0x020e0 /* 915+ only */ 568 #define FW_BLC_SELF_EN_MASK (1UL<<31) 569 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ 570 #define FW_BLC_SELF_EN (1<<15) /* 945 only */ 571 #define MM_BURST_LENGTH 0x00700000 572 #define MM_FIFO_WATERMARK 0x0001F000 573 #define LM_BURST_LENGTH 0x00000700 574 #define LM_FIFO_WATERMARK 0x0000001F 575 #define MI_ARB_STATE 0x020e4 /* 915+ only */ 576 577 /* Make render/texture TLB fetches lower priority than associated data 578 * fetches. This is not turned on by default 579 */ 580 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 581 582 /* Isoch request wait on GTT enable (Display A/B/C streams). 583 * Make isoch requests stall on the TLB update. May cause 584 * display underruns (test mode only) 585 */ 586 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 587 588 /* Block grant count for isoch requests when block count is 589 * set to a finite value. 590 */ 591 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 592 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 593 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 594 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 595 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 596 597 /* Enable render writes to complete in C2/C3/C4 power states. 598 * If this isn't enabled, render writes are prevented in low 599 * power states. That seems bad to me. 600 */ 601 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 602 603 /* This acknowledges an async flip immediately instead 604 * of waiting for 2TLB fetches. 605 */ 606 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 607 608 /* Enables non-sequential data reads through arbiter 609 */ 610 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 611 612 /* Disable FSB snooping of cacheable write cycles from binner/render 613 * command stream 614 */ 615 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 616 617 /* Arbiter time slice for non-isoch streams */ 618 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 619 #define MI_ARB_TIME_SLICE_1 (0 << 5) 620 #define MI_ARB_TIME_SLICE_2 (1 << 5) 621 #define MI_ARB_TIME_SLICE_4 (2 << 5) 622 #define MI_ARB_TIME_SLICE_6 (3 << 5) 623 #define MI_ARB_TIME_SLICE_8 (4 << 5) 624 #define MI_ARB_TIME_SLICE_10 (5 << 5) 625 #define MI_ARB_TIME_SLICE_14 (6 << 5) 626 #define MI_ARB_TIME_SLICE_16 (7 << 5) 627 628 /* Low priority grace period page size */ 629 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 630 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 631 632 /* Disable display A/B trickle feed */ 633 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 634 635 /* Set display plane priority */ 636 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 637 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 638 639 #define CACHE_MODE_0 0x02120 /* 915+ only */ 640 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) 641 #define CM0_IZ_OPT_DISABLE (1<<6) 642 #define CM0_ZR_OPT_DISABLE (1<<5) 643 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) 644 #define CM0_DEPTH_EVICT_DISABLE (1<<4) 645 #define CM0_COLOR_EVICT_DISABLE (1<<3) 646 #define CM0_DEPTH_WRITE_DISABLE (1<<1) 647 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 648 #define BB_ADDR 0x02140 /* 8 bytes */ 649 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 650 #define GFX_FLSH_CNTL_GEN6 0x101008 651 #define GFX_FLSH_CNTL_EN (1<<0) 652 #define ECOSKPD 0x021d0 653 #define ECO_GATING_CX_ONLY (1<<3) 654 #define ECO_FLIP_DONE (1<<0) 655 656 #define CACHE_MODE_1 0x7004 /* IVB+ */ 657 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) 658 659 /* GEN6 interrupt control 660 * Note that the per-ring interrupt bits do alias with the global interrupt bits 661 * in GTIMR. */ 662 #define GEN6_RENDER_HWSTAM 0x2098 663 #define GEN6_RENDER_IMR 0x20a8 664 #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) 665 #define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) 666 #define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) 667 #define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) 668 #define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) 669 #define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) 670 #define GEN6_RENDER_SYNC_STATUS (1 << 2) 671 #define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) 672 #define GEN6_RENDER_USER_INTERRUPT (1 << 0) 673 674 #define GEN6_BLITTER_HWSTAM 0x22098 675 #define GEN6_BLITTER_IMR 0x220a8 676 #define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) 677 #define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) 678 #define GEN6_BLITTER_SYNC_STATUS (1 << 24) 679 #define GEN6_BLITTER_USER_INTERRUPT (1 << 22) 680 681 #define GEN6_BLITTER_ECOSKPD 0x221d0 682 #define GEN6_BLITTER_LOCK_SHIFT 16 683 #define GEN6_BLITTER_FBC_NOTIFY (1<<3) 684 685 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 686 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) 687 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) 688 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) 689 #define GEN6_BSD_GO_INDICATOR (1 << 4) 690 691 #define GEN6_BSD_HWSTAM 0x12098 692 #define GEN6_BSD_IMR 0x120a8 693 #define GEN6_BSD_USER_INTERRUPT (1 << 12) 694 695 #define GEN6_BSD_RNCID 0x12198 696 697 #define GEN7_FF_THREAD_MODE 0x20a0 698 #define GEN7_FF_SCHED_MASK 0x0077070 699 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) 700 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) 701 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) 702 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ 703 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) 704 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) 705 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ 706 #define GEN7_FF_VS_SCHED_HW (0x0<<12) 707 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) 708 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) 709 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ 710 #define GEN7_FF_DS_SCHED_HW (0x0<<4) 711 712 /* 713 * Framebuffer compression (915+ only) 714 */ 715 716 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 717 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 718 #define FBC_CONTROL 0x03208 719 #define FBC_CTL_EN (1UL<<31) 720 #define FBC_CTL_PERIODIC (1<<30) 721 #define FBC_CTL_INTERVAL_SHIFT (16) 722 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 723 #define FBC_CTL_C3_IDLE (1<<13) 724 #define FBC_CTL_STRIDE_SHIFT (5) 725 #define FBC_CTL_FENCENO (1<<0) 726 #define FBC_COMMAND 0x0320c 727 #define FBC_CMD_COMPRESS (1<<0) 728 #define FBC_STATUS 0x03210 729 #define FBC_STAT_COMPRESSING (1UL<<31) 730 #define FBC_STAT_COMPRESSED (1<<30) 731 #define FBC_STAT_MODIFIED (1<<29) 732 #define FBC_STAT_CURRENT_LINE (1<<0) 733 #define FBC_CONTROL2 0x03214 734 #define FBC_CTL_FENCE_DBL (0<<4) 735 #define FBC_CTL_IDLE_IMM (0<<2) 736 #define FBC_CTL_IDLE_FULL (1<<2) 737 #define FBC_CTL_IDLE_LINE (2<<2) 738 #define FBC_CTL_IDLE_DEBUG (3<<2) 739 #define FBC_CTL_CPU_FENCE (1<<1) 740 #define FBC_CTL_PLANEA (0<<0) 741 #define FBC_CTL_PLANEB (1<<0) 742 #define FBC_FENCE_OFF 0x0321b 743 #define FBC_TAG 0x03300 744 745 #define FBC_LL_SIZE (1536) 746 747 /* Framebuffer compression for GM45+ */ 748 #define DPFC_CB_BASE 0x3200 749 #define DPFC_CONTROL 0x3208 750 #define DPFC_CTL_EN (1UL<<31) 751 #define DPFC_CTL_PLANEA (0<<30) 752 #define DPFC_CTL_PLANEB (1<<30) 753 #define DPFC_CTL_FENCE_EN (1<<29) 754 #define DPFC_CTL_PERSISTENT_MODE (1<<25) 755 #define DPFC_SR_EN (1<<10) 756 #define DPFC_CTL_LIMIT_1X (0<<6) 757 #define DPFC_CTL_LIMIT_2X (1<<6) 758 #define DPFC_CTL_LIMIT_4X (2<<6) 759 #define DPFC_RECOMP_CTL 0x320c 760 #define DPFC_RECOMP_STALL_EN (1<<27) 761 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 762 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 763 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 764 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 765 #define DPFC_STATUS 0x3210 766 #define DPFC_INVAL_SEG_SHIFT (16) 767 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 768 #define DPFC_COMP_SEG_SHIFT (0) 769 #define DPFC_COMP_SEG_MASK (0x000003ff) 770 #define DPFC_STATUS2 0x3214 771 #define DPFC_FENCE_YOFF 0x3218 772 #define DPFC_CHICKEN 0x3224 773 #define DPFC_HT_MODIFY (1UL<<31) 774 775 /* Framebuffer compression for Ironlake */ 776 #define ILK_DPFC_CB_BASE 0x43200 777 #define ILK_DPFC_CONTROL 0x43208 778 /* The bit 28-8 is reserved */ 779 #define DPFC_RESERVED (0x1FFFFF00) 780 #define ILK_DPFC_RECOMP_CTL 0x4320c 781 #define ILK_DPFC_STATUS 0x43210 782 #define ILK_DPFC_FENCE_YOFF 0x43218 783 #define ILK_DPFC_CHICKEN 0x43224 784 #define ILK_FBC_RT_BASE 0x2128 785 #define ILK_FBC_RT_VALID (1<<0) 786 787 #define ILK_DISPLAY_CHICKEN1 0x42000 788 #define ILK_FBCQ_DIS (1<<22) 789 #define ILK_PABSTRETCH_DIS (1<<21) 790 791 /* 792 * Framebuffer compression for Sandybridge 793 * 794 * The following two registers are of type GTTMMADR 795 */ 796 #define SNB_DPFC_CTL_SA 0x100100 797 #define SNB_CPU_FENCE_ENABLE (1<<29) 798 #define DPFC_CPU_FENCE_OFFSET 0x100104 799 800 /* 801 * GPIO regs 802 */ 803 #define GPIOA 0x5010 804 #define GPIOB 0x5014 805 #define GPIOC 0x5018 806 #define GPIOD 0x501c 807 #define GPIOE 0x5020 808 #define GPIOF 0x5024 809 #define GPIOG 0x5028 810 #define GPIOH 0x502c 811 # define GPIO_CLOCK_DIR_MASK (1 << 0) 812 # define GPIO_CLOCK_DIR_IN (0 << 1) 813 # define GPIO_CLOCK_DIR_OUT (1 << 1) 814 # define GPIO_CLOCK_VAL_MASK (1 << 2) 815 # define GPIO_CLOCK_VAL_OUT (1 << 3) 816 # define GPIO_CLOCK_VAL_IN (1 << 4) 817 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 818 # define GPIO_DATA_DIR_MASK (1 << 8) 819 # define GPIO_DATA_DIR_IN (0 << 9) 820 # define GPIO_DATA_DIR_OUT (1 << 9) 821 # define GPIO_DATA_VAL_MASK (1 << 10) 822 # define GPIO_DATA_VAL_OUT (1 << 11) 823 # define GPIO_DATA_VAL_IN (1 << 12) 824 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 825 826 #define GMBUS0 0x5100 /* clock/port select */ 827 #define GMBUS_RATE_100KHZ (0<<8) 828 #define GMBUS_RATE_50KHZ (1<<8) 829 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ 830 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ 831 #define GMBUS_RATE_MASK (3<<8) 832 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ 833 #define GMBUS_PORT_DISABLED 0 834 #define GMBUS_PORT_SSC 1 835 #define GMBUS_PORT_VGADDC 2 836 #define GMBUS_PORT_PANEL 3 837 #define GMBUS_PORT_DPC 4 /* HDMIC */ 838 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ 839 #define GMBUS_PORT_DPD 6 /* HDMID */ 840 #define GMBUS_PORT_RESERVED 7 /* 7 reserved */ 841 #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) 842 #define GMBUS_PORT_MASK 7 843 #define GMBUS1 0x5104 /* command/status */ 844 #define GMBUS_SW_CLR_INT (1UL<<31) 845 #define GMBUS_SW_RDY (1<<30) 846 #define GMBUS_ENT (1<<29) /* enable timeout */ 847 #define GMBUS_CYCLE_NONE (0<<25) 848 #define GMBUS_CYCLE_WAIT (1<<25) 849 #define GMBUS_CYCLE_INDEX (2<<25) 850 #define GMBUS_CYCLE_STOP (4<<25) 851 #define GMBUS_BYTE_COUNT_SHIFT 16 852 #define GMBUS_SLAVE_INDEX_SHIFT 8 853 #define GMBUS_SLAVE_ADDR_SHIFT 1 854 #define GMBUS_SLAVE_READ (1<<0) 855 #define GMBUS_SLAVE_WRITE (0<<0) 856 #define GMBUS2 0x5108 /* status */ 857 #define GMBUS_INUSE (1<<15) 858 #define GMBUS_HW_WAIT_PHASE (1<<14) 859 #define GMBUS_STALL_TIMEOUT (1<<13) 860 #define GMBUS_INT (1<<12) 861 #define GMBUS_HW_RDY (1<<11) 862 #define GMBUS_SATOER (1<<10) 863 #define GMBUS_ACTIVE (1<<9) 864 #define GMBUS3 0x510c /* data buffer bytes 3-0 */ 865 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ 866 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 867 #define GMBUS_NAK_EN (1<<3) 868 #define GMBUS_IDLE_EN (1<<2) 869 #define GMBUS_HW_WAIT_EN (1<<1) 870 #define GMBUS_HW_RDY_EN (1<<0) 871 #define GMBUS5 0x5120 /* byte index */ 872 #define GMBUS_2BYTE_INDEX_EN (1UL<<31) 873 874 /* 875 * Clock control & power management 876 */ 877 878 #define VGA0 0x6000 879 #define VGA1 0x6004 880 #define VGA_PD 0x6010 881 #define VGA0_PD_P2_DIV_4 (1 << 7) 882 #define VGA0_PD_P1_DIV_2 (1 << 5) 883 #define VGA0_PD_P1_SHIFT 0 884 #define VGA0_PD_P1_MASK (0x1f << 0) 885 #define VGA1_PD_P2_DIV_4 (1 << 15) 886 #define VGA1_PD_P1_DIV_2 (1 << 13) 887 #define VGA1_PD_P1_SHIFT 8 888 #define VGA1_PD_P1_MASK (0x1f << 8) 889 #define _DPLL_A 0x06014 890 #define _DPLL_B 0x06018 891 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) 892 #define DPLL_VCO_ENABLE (1UL << 31) 893 #define DPLL_DVO_HIGH_SPEED (1 << 30) 894 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 895 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 896 #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) 897 #define DPLL_VGA_MODE_DIS (1 << 28) 898 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 899 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 900 #define DPLL_MODE_MASK (3 << 26) 901 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 902 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 903 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 904 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 905 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 906 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 907 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 908 #define DPLL_LOCK_VLV (1<<15) 909 #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) 910 911 #define SRX_INDEX 0x3c4 912 #define SRX_DATA 0x3c5 913 #define SR01 1 914 #define SR01_SCREEN_OFF (1<<5) 915 916 #define PPCR 0x61204 917 #define PPCR_ON (1<<0) 918 919 #define DVOB 0x61140 920 #define DVOB_ON (1UL<<31) 921 #define DVOC 0x61160 922 #define DVOC_ON (1UL<<31) 923 #define LVDS 0x61180 924 #define LVDS_ON (1UL<<31) 925 #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) 926 #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) 927 #define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) 928 #define LVDS_BORDER_ENABLE (1 << 15) 929 #define LVDS_DETECTED (1 << 1) 930 931 /* Scratch pad debug 0 reg: 932 */ 933 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 934 /* 935 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 936 * this field (only one bit may be set). 937 */ 938 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 939 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 940 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 941 /* i830, required in DVO non-gang */ 942 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 943 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 944 #define PLL_REF_INPUT_DREFCLK (0 << 13) 945 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 946 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 947 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 948 #define PLL_REF_INPUT_MASK (3 << 13) 949 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 950 /* Ironlake */ 951 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 952 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 953 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 954 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 955 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 956 957 /* 958 * Parallel to Serial Load Pulse phase selection. 959 * Selects the phase for the 10X DPLL clock for the PCIe 960 * digital display port. The range is 4 to 13; 10 or more 961 * is just a flip delay. The default is 6 962 */ 963 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 964 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 965 /* 966 * SDVO multiplier for 945G/GM. Not used on 965. 967 */ 968 #define SDVO_MULTIPLIER_MASK 0x000000ff 969 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 970 #define SDVO_MULTIPLIER_SHIFT_VGA 0 971 #define _DPLL_A_MD 0x0601c /* 965+ only */ 972 /* 973 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 974 * 975 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 976 */ 977 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 978 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 979 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 980 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 981 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 982 /* 983 * SDVO/UDI pixel multiplier. 984 * 985 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 986 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 987 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 988 * dummy bytes in the datastream at an increased clock rate, with both sides of 989 * the link knowing how many bytes are fill. 990 * 991 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 992 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 993 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 994 * through an SDVO command. 995 * 996 * This register field has values of multiplication factor minus 1, with 997 * a maximum multiplier of 5 for SDVO. 998 */ 999 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 1000 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 1001 /* 1002 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 1003 * This best be set to the default value (3) or the CRT won't work. No, 1004 * I don't entirely understand what this does... 1005 */ 1006 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 1007 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 1008 #define _DPLL_B_MD 0x06020 /* 965+ only */ 1009 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) 1010 1011 #define _FPA0 0x06040 1012 #define _FPA1 0x06044 1013 #define _FPB0 0x06048 1014 #define _FPB1 0x0604c 1015 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) 1016 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) 1017 #define FP_N_DIV_MASK 0x003f0000 1018 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 1019 #define FP_N_DIV_SHIFT 16 1020 #define FP_M1_DIV_MASK 0x00003f00 1021 #define FP_M1_DIV_SHIFT 8 1022 #define FP_M2_DIV_MASK 0x0000003f 1023 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 1024 #define FP_M2_DIV_SHIFT 0 1025 #define DPLL_TEST 0x606c 1026 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 1027 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 1028 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 1029 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 1030 #define DPLLB_TEST_N_BYPASS (1 << 19) 1031 #define DPLLB_TEST_M_BYPASS (1 << 18) 1032 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 1033 #define DPLLA_TEST_N_BYPASS (1 << 3) 1034 #define DPLLA_TEST_M_BYPASS (1 << 2) 1035 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 1036 #define D_STATE 0x6104 1037 #define DSTATE_GFX_RESET_I830 (1<<6) 1038 #define DSTATE_PLL_D3_OFF (1<<3) 1039 #define DSTATE_GFX_CLOCK_GATING (1<<1) 1040 #define DSTATE_DOT_CLOCK_GATING (1<<0) 1041 #define DSPCLK_GATE_D 0x6200 1042 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 1043 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 1044 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 1045 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 1046 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 1047 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 1048 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 1049 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 1050 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 1051 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 1052 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 1053 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 1054 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 1055 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 1056 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 1057 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 1058 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 1059 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 1060 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 1061 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 1062 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 1063 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 1064 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 1065 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 1066 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 1067 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 1068 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 1069 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 1070 /** 1071 * This bit must be set on the 830 to prevent hangs when turning off the 1072 * overlay scaler. 1073 */ 1074 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 1075 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 1076 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 1077 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 1078 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 1079 1080 #define RENCLK_GATE_D1 0x6204 1081 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 1082 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 1083 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 1084 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 1085 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 1086 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 1087 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 1088 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 1089 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 1090 /** This bit must be unset on 855,865 */ 1091 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 1092 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 1093 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 1094 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 1095 /** This bit must be set on 855,865. */ 1096 # define SV_CLOCK_GATE_DISABLE (1 << 0) 1097 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 1098 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 1099 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 1100 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 1101 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 1102 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 1103 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 1104 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 1105 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 1106 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 1107 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 1108 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 1109 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 1110 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 1111 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 1112 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 1113 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 1114 1115 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 1116 /** This bit must always be set on 965G/965GM */ 1117 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 1118 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 1119 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 1120 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 1121 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 1122 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 1123 /** This bit must always be set on 965G */ 1124 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 1125 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 1126 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 1127 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 1128 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 1129 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 1130 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 1131 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 1132 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 1133 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 1134 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 1135 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 1136 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 1137 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 1138 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 1139 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 1140 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 1141 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 1142 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 1143 1144 #define RENCLK_GATE_D2 0x6208 1145 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 1146 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 1147 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 1148 #define RAMCLK_GATE_D 0x6210 /* CRL only */ 1149 #define DEUC 0x6214 /* CRL only */ 1150 1151 #define FW_BLC_SELF_VLV 0x6500 1152 #define FW_CSPWRDWNEN (1<<15) 1153 1154 /* 1155 * Palette regs 1156 */ 1157 1158 #define _PALETTE_A 0x0a000 1159 #define _PALETTE_B 0x0a800 1160 #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B) 1161 1162 /* MCH MMIO space */ 1163 1164 /* 1165 * MCHBAR mirror. 1166 * 1167 * This mirrors the MCHBAR MMIO space whose location is determined by 1168 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 1169 * every way. It is not accessible from the CP register read instructions. 1170 * 1171 */ 1172 #define MCHBAR_MIRROR_BASE 0x10000 1173 1174 /* 1175 * Logical Context regs 1176 */ 1177 #define CCID 0x2180 1178 #define CCID_EN (1<<0) 1179 #define CXT_SIZE 0x21a0 1180 #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f) 1181 #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f) 1182 #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f) 1183 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f) 1184 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f) 1185 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_POWER_SIZE(cxt_reg) + \ 1186 GEN6_CXT_RING_SIZE(cxt_reg) + \ 1187 GEN6_CXT_RENDER_SIZE(cxt_reg) + \ 1188 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ 1189 GEN6_CXT_PIPELINE_SIZE(cxt_reg)) 1190 #define GEN7_CXT_SIZE 0x21a8 1191 #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f) 1192 #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7) 1193 #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f) 1194 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f) 1195 #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7) 1196 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f) 1197 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_POWER_SIZE(ctx_reg) + \ 1198 GEN7_CXT_RING_SIZE(ctx_reg) + \ 1199 GEN7_CXT_RENDER_SIZE(ctx_reg) + \ 1200 GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ 1201 GEN7_CXT_GT1_SIZE(ctx_reg) + \ 1202 GEN7_CXT_VFSTATE_SIZE(ctx_reg)) 1203 #define HSW_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 26) & 0x3f) 1204 #define HSW_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 23) & 0x7) 1205 #define HSW_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 15) & 0xff) 1206 #define HSW_CXT_TOTAL_SIZE(ctx_reg) (HSW_CXT_POWER_SIZE(ctx_reg) + \ 1207 HSW_CXT_RING_SIZE(ctx_reg) + \ 1208 HSW_CXT_RENDER_SIZE(ctx_reg) + \ 1209 GEN7_CXT_VFSTATE_SIZE(ctx_reg)) 1210 1211 /* 1212 * Overlay regs 1213 */ 1214 1215 #define OVADD 0x30000 1216 #define DOVSTA 0x30008 1217 #define OC_BUF (0x3<<20) 1218 #define OGAMC5 0x30010 1219 #define OGAMC4 0x30014 1220 #define OGAMC3 0x30018 1221 #define OGAMC2 0x3001c 1222 #define OGAMC1 0x30020 1223 #define OGAMC0 0x30024 1224 1225 /* 1226 * Display engine regs 1227 */ 1228 1229 /* Pipe A timing regs */ 1230 #define _HTOTAL_A 0x60000 1231 #define _HBLANK_A 0x60004 1232 #define _HSYNC_A 0x60008 1233 #define _VTOTAL_A 0x6000c 1234 #define _VBLANK_A 0x60010 1235 #define _VSYNC_A 0x60014 1236 #define _PIPEASRC 0x6001c 1237 #define _BCLRPAT_A 0x60020 1238 #define _VSYNCSHIFT_A 0x60028 1239 1240 /* Pipe B timing regs */ 1241 #define _HTOTAL_B 0x61000 1242 #define _HBLANK_B 0x61004 1243 #define _HSYNC_B 0x61008 1244 #define _VTOTAL_B 0x6100c 1245 #define _VBLANK_B 0x61010 1246 #define _VSYNC_B 0x61014 1247 #define _PIPEBSRC 0x6101c 1248 #define _BCLRPAT_B 0x61020 1249 #define _VSYNCSHIFT_B 0x61028 1250 1251 #define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B) 1252 #define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B) 1253 #define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B) 1254 #define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B) 1255 #define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B) 1256 #define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B) 1257 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) 1258 #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) 1259 1260 /* VGA port control */ 1261 #define ADPA 0x61100 1262 #define PCH_ADPA 0xe1100 1263 #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA) 1264 1265 #define ADPA_DAC_ENABLE (1UL<<31) 1266 #define ADPA_DAC_DISABLE 0 1267 #define ADPA_PIPE_SELECT_MASK (1<<30) 1268 #define ADPA_PIPE_A_SELECT 0 1269 #define ADPA_PIPE_B_SELECT (1<<30) 1270 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) 1271 /* CPT uses bits 29:30 for pch transcoder select */ 1272 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 1273 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 1274 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 1275 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 1276 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 1277 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 1278 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 1279 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 1280 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 1281 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 1282 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 1283 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 1284 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 1285 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 1286 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 1287 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 1288 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 1289 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 1290 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 1291 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 1292 #define ADPA_SETS_HVPOLARITY 0 1293 #define ADPA_VSYNC_CNTL_DISABLE (1<<11) 1294 #define ADPA_VSYNC_CNTL_ENABLE 0 1295 #define ADPA_HSYNC_CNTL_DISABLE (1<<10) 1296 #define ADPA_HSYNC_CNTL_ENABLE 0 1297 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 1298 #define ADPA_VSYNC_ACTIVE_LOW 0 1299 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 1300 #define ADPA_HSYNC_ACTIVE_LOW 0 1301 #define ADPA_DPMS_MASK (~(3<<10)) 1302 #define ADPA_DPMS_ON (0<<10) 1303 #define ADPA_DPMS_SUSPEND (1<<10) 1304 #define ADPA_DPMS_STANDBY (2<<10) 1305 #define ADPA_DPMS_OFF (3<<10) 1306 1307 /* Hotplug control (945+ only) */ 1308 #define PORT_HOTPLUG_EN 0x61110 1309 #define HDMIB_HOTPLUG_INT_EN (1 << 29) 1310 #define DPB_HOTPLUG_INT_EN (1 << 29) 1311 #define HDMIC_HOTPLUG_INT_EN (1 << 28) 1312 #define DPC_HOTPLUG_INT_EN (1 << 28) 1313 #define HDMID_HOTPLUG_INT_EN (1 << 27) 1314 #define DPD_HOTPLUG_INT_EN (1 << 27) 1315 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 1316 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 1317 #define TV_HOTPLUG_INT_EN (1 << 18) 1318 #define CRT_HOTPLUG_INT_EN (1 << 9) 1319 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 1320 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 1321 /* must use period 64 on GM45 according to docs */ 1322 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 1323 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 1324 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 1325 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 1326 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 1327 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 1328 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 1329 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 1330 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 1331 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 1332 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 1333 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 1334 1335 #define PORT_HOTPLUG_STAT 0x61114 1336 /* HDMI/DP bits are gen4+ */ 1337 #define DPB_HOTPLUG_LIVE_STATUS (1 << 29) 1338 #define DPC_HOTPLUG_LIVE_STATUS (1 << 28) 1339 #define DPD_HOTPLUG_LIVE_STATUS (1 << 27) 1340 #define DPD_HOTPLUG_INT_STATUS (3 << 21) 1341 #define DPC_HOTPLUG_INT_STATUS (3 << 19) 1342 #define DPB_HOTPLUG_INT_STATUS (3 << 17) 1343 /* HDMI bits are shared with the DP bits */ 1344 #define HDMIB_HOTPLUG_LIVE_STATUS (1 << 29) 1345 #define HDMIC_HOTPLUG_LIVE_STATUS (1 << 28) 1346 #define HDMID_HOTPLUG_LIVE_STATUS (1 << 27) 1347 #define HDMID_HOTPLUG_INT_STATUS (3 << 21) 1348 #define HDMIC_HOTPLUG_INT_STATUS (3 << 19) 1349 #define HDMIB_HOTPLUG_INT_STATUS (3 << 17) 1350 /* CRT/TV common between gen3+ */ 1351 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 1352 #define TV_HOTPLUG_INT_STATUS (1 << 10) 1353 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 1354 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 1355 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 1356 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 1357 /* SDVO is different across gen3/4 */ 1358 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 1359 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 1360 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 1361 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 1362 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 1363 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 1364 1365 /* SDVO port control */ 1366 #define SDVOB 0x61140 1367 #define SDVOC 0x61160 1368 #define SDVO_ENABLE (1UL << 31) 1369 #define SDVO_PIPE_B_SELECT (1 << 30) 1370 #define SDVO_STALL_SELECT (1 << 29) 1371 #define SDVO_INTERRUPT_ENABLE (1 << 26) 1372 /** 1373 * 915G/GM SDVO pixel multiplier. 1374 * 1375 * Programmed value is multiplier - 1, up to 5x. 1376 * 1377 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 1378 */ 1379 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 1380 #define SDVO_PORT_MULTIPLY_SHIFT 23 1381 #define SDVO_PHASE_SELECT_MASK (15 << 19) 1382 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 1383 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 1384 #define SDVOC_GANG_MODE (1 << 16) 1385 #define SDVO_ENCODING_SDVO (0x0 << 10) 1386 #define SDVO_ENCODING_HDMI (0x2 << 10) 1387 /** Required for HDMI operation */ 1388 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) 1389 #define SDVO_COLOR_RANGE_16_235 (1 << 8) 1390 #define SDVO_BORDER_ENABLE (1 << 7) 1391 #define SDVO_AUDIO_ENABLE (1 << 6) 1392 /** New with 965, default is to be set */ 1393 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 1394 /** New with 965, default is to be set */ 1395 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 1396 #define SDVOB_PCIE_CONCURRENCY (1 << 3) 1397 #define SDVO_DETECTED (1 << 2) 1398 /* Bits to be preserved when writing */ 1399 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) 1400 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) 1401 1402 /* DVO port control */ 1403 #define DVOA 0x61120 1404 #define DVOB 0x61140 1405 #define DVOC 0x61160 1406 #define DVO_ENABLE (1UL << 31) 1407 #define DVO_PIPE_B_SELECT (1 << 30) 1408 #define DVO_PIPE_STALL_UNUSED (0 << 28) 1409 #define DVO_PIPE_STALL (1 << 28) 1410 #define DVO_PIPE_STALL_TV (2 << 28) 1411 #define DVO_PIPE_STALL_MASK (3 << 28) 1412 #define DVO_USE_VGA_SYNC (1 << 15) 1413 #define DVO_DATA_ORDER_I740 (0 << 14) 1414 #define DVO_DATA_ORDER_FP (1 << 14) 1415 #define DVO_VSYNC_DISABLE (1 << 11) 1416 #define DVO_HSYNC_DISABLE (1 << 10) 1417 #define DVO_VSYNC_TRISTATE (1 << 9) 1418 #define DVO_HSYNC_TRISTATE (1 << 8) 1419 #define DVO_BORDER_ENABLE (1 << 7) 1420 #define DVO_DATA_ORDER_GBRG (1 << 6) 1421 #define DVO_DATA_ORDER_RGGB (0 << 6) 1422 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 1423 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 1424 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 1425 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 1426 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 1427 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 1428 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 1429 #define DVO_PRESERVE_MASK (0x7<<24) 1430 #define DVOA_SRCDIM 0x61124 1431 #define DVOB_SRCDIM 0x61144 1432 #define DVOC_SRCDIM 0x61164 1433 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 1434 #define DVO_SRCDIM_VERTICAL_SHIFT 0 1435 1436 /* LVDS port control */ 1437 #define LVDS 0x61180 1438 /* 1439 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 1440 * the DPLL semantics change when the LVDS is assigned to that pipe. 1441 */ 1442 #define LVDS_PORT_EN (1UL << 31) 1443 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 1444 #define LVDS_PIPEB_SELECT (1 << 30) 1445 #define LVDS_PIPE_MASK (1 << 30) 1446 #define LVDS_PIPE(pipe) ((pipe) << 30) 1447 /* LVDS dithering flag on 965/g4x platform */ 1448 #define LVDS_ENABLE_DITHER (1 << 25) 1449 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 1450 #define LVDS_VSYNC_POLARITY (1 << 21) 1451 #define LVDS_HSYNC_POLARITY (1 << 20) 1452 1453 /* Enable border for unscaled (or aspect-scaled) display */ 1454 #define LVDS_BORDER_ENABLE (1 << 15) 1455 /* 1456 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 1457 * pixel. 1458 */ 1459 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 1460 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 1461 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 1462 /* 1463 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 1464 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 1465 * on. 1466 */ 1467 #define LVDS_A3_POWER_MASK (3 << 6) 1468 #define LVDS_A3_POWER_DOWN (0 << 6) 1469 #define LVDS_A3_POWER_UP (3 << 6) 1470 /* 1471 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 1472 * is set. 1473 */ 1474 #define LVDS_CLKB_POWER_MASK (3 << 4) 1475 #define LVDS_CLKB_POWER_DOWN (0 << 4) 1476 #define LVDS_CLKB_POWER_UP (3 << 4) 1477 /* 1478 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 1479 * setting for whether we are in dual-channel mode. The B3 pair will 1480 * additionally only be powered up when LVDS_A3_POWER_UP is set. 1481 */ 1482 #define LVDS_B0B3_POWER_MASK (3 << 2) 1483 #define LVDS_B0B3_POWER_DOWN (0 << 2) 1484 #define LVDS_B0B3_POWER_UP (3 << 2) 1485 1486 /* Video Data Island Packet control */ 1487 #define VIDEO_DIP_DATA 0x61178 1488 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 1489 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 1490 * of the infoframe structure specified by CEA-861. */ 1491 #define VIDEO_DIP_DATA_SIZE 32 1492 #define VIDEO_DIP_CTL 0x61170 1493 /* Pre HSW: */ 1494 #define VIDEO_DIP_ENABLE (1UL << 31) 1495 #define VIDEO_DIP_PORT_B (1 << 29) 1496 #define VIDEO_DIP_PORT_C (2 << 29) 1497 #define VIDEO_DIP_PORT_D (3 << 29) 1498 #define VIDEO_DIP_PORT_MASK (3 << 29) 1499 #define VIDEO_DIP_ENABLE_GCP (1 << 25) 1500 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 1501 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 1502 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) 1503 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 1504 #define VIDEO_DIP_SELECT_AVI (0 << 19) 1505 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 1506 #define VIDEO_DIP_SELECT_SPD (3 << 19) 1507 #define VIDEO_DIP_SELECT_MASK (3 << 19) 1508 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 1509 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 1510 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 1511 #define VIDEO_DIP_FREQ_MASK (3 << 16) 1512 /* HSW and later: */ 1513 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 1514 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 1515 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 1516 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 1517 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 1518 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 1519 1520 /* Panel power sequencing */ 1521 #define PP_STATUS 0x61200 1522 #define PP_ON (1UL << 31) 1523 /* 1524 * Indicates that all dependencies of the panel are on: 1525 * 1526 * - PLL enabled 1527 * - pipe enabled 1528 * - LVDS/DVOB/DVOC on 1529 */ 1530 #define PP_READY (1 << 30) 1531 #define PP_SEQUENCE_NONE (0 << 28) 1532 #define PP_SEQUENCE_POWER_UP (1 << 28) 1533 #define PP_SEQUENCE_POWER_DOWN (2 << 28) 1534 #define PP_SEQUENCE_MASK (3 << 28) 1535 #define PP_SEQUENCE_SHIFT 28 1536 #define PP_CYCLE_DELAY_ACTIVE (1 << 27) 1537 #define PP_SEQUENCE_STATE_MASK 0x0000000f 1538 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) 1539 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) 1540 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) 1541 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) 1542 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) 1543 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) 1544 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) 1545 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) 1546 #define PP_SEQUENCE_STATE_RESET (0xf << 0) 1547 #define PP_CONTROL 0x61204 1548 #define POWER_TARGET_ON (1 << 0) 1549 #define PP_ON_DELAYS 0x61208 1550 #define PP_OFF_DELAYS 0x6120c 1551 #define PP_DIVISOR 0x61210 1552 1553 /* Panel fitting */ 1554 #define PFIT_CONTROL 0x61230 1555 #define PFIT_ENABLE (1UL << 31) 1556 #define PFIT_PIPE_MASK (3 << 29) 1557 #define PFIT_PIPE_SHIFT 29 1558 #define VERT_INTERP_DISABLE (0 << 10) 1559 #define VERT_INTERP_BILINEAR (1 << 10) 1560 #define VERT_INTERP_MASK (3 << 10) 1561 #define VERT_AUTO_SCALE (1 << 9) 1562 #define HORIZ_INTERP_DISABLE (0 << 6) 1563 #define HORIZ_INTERP_BILINEAR (1 << 6) 1564 #define HORIZ_INTERP_MASK (3 << 6) 1565 #define HORIZ_AUTO_SCALE (1 << 5) 1566 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 1567 #define PFIT_FILTER_FUZZY (0 << 24) 1568 #define PFIT_SCALING_AUTO (0 << 26) 1569 #define PFIT_SCALING_PROGRAMMED (1 << 26) 1570 #define PFIT_SCALING_PILLAR (2 << 26) 1571 #define PFIT_SCALING_LETTER (3 << 26) 1572 #define PFIT_PGM_RATIOS 0x61234 1573 #define PFIT_VERT_SCALE_MASK 0xfff00000 1574 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1575 /* Pre-965 */ 1576 #define PFIT_VERT_SCALE_SHIFT 20 1577 #define PFIT_VERT_SCALE_MASK 0xfff00000 1578 #define PFIT_HORIZ_SCALE_SHIFT 4 1579 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1580 /* 965+ */ 1581 #define PFIT_VERT_SCALE_SHIFT_965 16 1582 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 1583 #define PFIT_HORIZ_SCALE_SHIFT_965 0 1584 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 1585 1586 #define PFIT_AUTO_RATIOS 0x61238 1587 1588 /* Backlight control */ 1589 #define BLC_PWM_CTL2 0x61250 /* 965+ only */ 1590 #define BLM_PWM_ENABLE (1UL << 31) 1591 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ 1592 #define BLM_PIPE_SELECT (1 << 29) 1593 #define BLM_PIPE_SELECT_IVB (3 << 29) 1594 #define BLM_PIPE_A (0 << 29) 1595 #define BLM_PIPE_B (1 << 29) 1596 #define BLM_PIPE_C (2 << 29) /* ivb + */ 1597 #define BLM_PIPE(pipe) ((pipe) << 29) 1598 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ 1599 #define BLM_PHASE_IN_INTERRUPT_STATUS (1 << 26) 1600 #define BLM_PHASE_IN_ENABLE (1 << 25) 1601 #define BLM_PHASE_IN_INTERRUPT_ENABL (1 << 24) 1602 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) 1603 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) 1604 #define BLM_PHASE_IN_COUNT_SHIFT (8) 1605 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) 1606 #define BLM_PHASE_IN_INCR_SHIFT (0) 1607 #define BLM_PHASE_IN_INCR_MASK (0xff << 0) 1608 #define BLC_PWM_CTL 0x61254 1609 /* 1610 * This is the most significant 15 bits of the number of backlight cycles in a 1611 * complete cycle of the modulated backlight control. 1612 * 1613 * The actual value is this field multiplied by two. 1614 */ 1615 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 1616 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 1617 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ 1618 /* 1619 * This is the number of cycles out of the backlight modulation cycle for which 1620 * the backlight is on. 1621 * 1622 * This field must be no greater than the number of cycles in the complete 1623 * backlight modulation cycle. 1624 */ 1625 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 1626 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 1627 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) 1628 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ 1629 1630 #define BLC_HIST_CTL 0x61260 1631 1632 /* New registers for PCH-split platforms. Safe where new bits show up, the 1633 * register layout matches with gen4 BLC_PWM_CTL[12]. */ 1634 #define BLC_PWM_CPU_CTL2 0x48250 1635 #define BLC_PWM2_ENABLE (1UL<<31) 1636 #define BLC_PWM_CPU_CTL 0x48254 1637 1638 #define BLM_HIST_CTL 0x48260 1639 #define ENH_HIST_ENABLE (1UL<<31) 1640 #define ENH_MODIF_TBL_ENABLE (1<<30) 1641 #define ENH_PIPE_A_SELECT (0<<29) 1642 #define ENH_PIPE_B_SELECT (1<<29) 1643 #define ENH_PIPE(pipe) _PIPE(pipe, ENH_PIPE_A_SELECT, ENH_PIPE_B_SELECT) 1644 #define HIST_MODE_YUV (0<<24) 1645 #define HIST_MODE_HSV (1<<24) 1646 #define ENH_MODE_DIRECT (0<<13) 1647 #define ENH_MODE_ADDITIVE (1<<13) 1648 #define ENH_MODE_MULTIPLICATIVE (2<<13) 1649 #define BIN_REGISTER_SET (1<<11) 1650 #define ENH_NUM_BINS 32 1651 1652 #define BLM_HIST_ENH 0x48264 1653 1654 #define BLM_HIST_GUARD_BAND 0x48268 1655 #define BLM_HIST_INTR_ENABLE (1UL<<31) 1656 #define BLM_HIST_EVENT_STATUS (1<<30) 1657 #define BLM_HIST_INTR_DELAY_MASK (0xFF<<22) 1658 #define BLM_HIST_INTR_DELAY_SHIFT 22 1659 1660 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is 1661 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ 1662 #define BLC_PWM_PCH_CTL1 0xc8250 1663 #define BLM_PCH_PWM_ENABLE (1UL << 31) 1664 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) 1665 #define BLM_PCH_POLARITY (1 << 29) 1666 #define BLC_PWM_PCH_CTL2 0xc8254 1667 1668 #define UTIL_PIN_CTL 0x48400 1669 #define UTIL_PIN_ENABLE (1 << 31) 1670 1671 #define UTIL_PIN_PIPE(x) ((x) << 29) 1672 #define UTIL_PIN_PIPE_MASK (3 << 29) 1673 #define UTIL_PIN_MODE_PWM (1 << 24) 1674 #define UTIL_PIN_MODE_MASK (0xf << 24) 1675 #define UTIL_PIN_POLARITY (1 << 22) 1676 1677 /* BXT backlight register definition. */ 1678 #define _BXT_BLC_PWM_CTL1 0xC8250 1679 #define BXT_BLC_PWM_ENABLE (1 << 31) 1680 #define BXT_BLC_PWM_POLARITY (1 << 29) 1681 #define _BXT_BLC_PWM_FREQ1 0xC8254 1682 #define _BXT_BLC_PWM_DUTY1 0xC8258 1683 1684 #define _BXT_BLC_PWM_CTL2 0xC8350 1685 #define _BXT_BLC_PWM_FREQ2 0xC8354 1686 #define _BXT_BLC_PWM_DUTY2 0xC8358 1687 1688 #define BXT_BLC_PWM_CTL(controller) _PIPE(controller, \ 1689 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) 1690 #define BXT_BLC_PWM_FREQ(controller) _PIPE(controller, \ 1691 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) 1692 #define BXT_BLC_PWM_DUTY(controller) _PIPE(controller, \ 1693 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) 1694 1695 /* TV port control */ 1696 #define TV_CTL 0x68000 1697 /** Enables the TV encoder */ 1698 # define TV_ENC_ENABLE (1UL << 31) 1699 /** Sources the TV encoder input from pipe B instead of A. */ 1700 # define TV_ENC_PIPEB_SELECT (1 << 30) 1701 /** Outputs composite video (DAC A only) */ 1702 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 1703 /** Outputs SVideo video (DAC B/C) */ 1704 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 1705 /** Outputs Component video (DAC A/B/C) */ 1706 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 1707 /** Outputs Composite and SVideo (DAC A/B/C) */ 1708 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 1709 # define TV_TRILEVEL_SYNC (1 << 21) 1710 /** Enables slow sync generation (945GM only) */ 1711 # define TV_SLOW_SYNC (1 << 20) 1712 /** Selects 4x oversampling for 480i and 576p */ 1713 # define TV_OVERSAMPLE_4X (0 << 18) 1714 /** Selects 2x oversampling for 720p and 1080i */ 1715 # define TV_OVERSAMPLE_2X (1 << 18) 1716 /** Selects no oversampling for 1080p */ 1717 # define TV_OVERSAMPLE_NONE (2 << 18) 1718 /** Selects 8x oversampling */ 1719 # define TV_OVERSAMPLE_8X (3 << 18) 1720 /** Selects progressive mode rather than interlaced */ 1721 # define TV_PROGRESSIVE (1 << 17) 1722 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 1723 # define TV_PAL_BURST (1 << 16) 1724 /** Field for setting delay of Y compared to C */ 1725 # define TV_YC_SKEW_MASK (7 << 12) 1726 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */ 1727 # define TV_ENC_SDP_FIX (1 << 11) 1728 /** 1729 * Enables a fix for the 915GM only. 1730 * 1731 * Not sure what it does. 1732 */ 1733 # define TV_ENC_C0_FIX (1 << 10) 1734 /** Bits that must be preserved by software */ 1735 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 1736 # define TV_FUSE_STATE_MASK (3 << 4) 1737 /** Read-only state that reports all features enabled */ 1738 # define TV_FUSE_STATE_ENABLED (0 << 4) 1739 /** Read-only state that reports that Macrovision is disabled in hardware*/ 1740 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 1741 /** Read-only state that reports that TV-out is disabled in hardware. */ 1742 # define TV_FUSE_STATE_DISABLED (2 << 4) 1743 /** Normal operation */ 1744 # define TV_TEST_MODE_NORMAL (0 << 0) 1745 /** Encoder test pattern 1 - combo pattern */ 1746 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 1747 /** Encoder test pattern 2 - full screen vertical 75% color bars */ 1748 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 1749 /** Encoder test pattern 3 - full screen horizontal 75% color bars */ 1750 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 1751 /** Encoder test pattern 4 - random noise */ 1752 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 1753 /** Encoder test pattern 5 - linear color ramps */ 1754 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 1755 /** 1756 * This test mode forces the DACs to 50% of full output. 1757 * 1758 * This is used for load detection in combination with TVDAC_SENSE_MASK 1759 */ 1760 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 1761 # define TV_TEST_MODE_MASK (7 << 0) 1762 1763 #define TV_DAC 0x68004 1764 # define TV_DAC_SAVE 0x00ffff00 1765 /** 1766 * Reports that DAC state change logic has reported change (RO). 1767 * 1768 * This gets cleared when TV_DAC_STATE_EN is cleared 1769 */ 1770 # define TVDAC_STATE_CHG (1UL << 31) 1771 # define TVDAC_SENSE_MASK (7 << 28) 1772 /** Reports that DAC A voltage is above the detect threshold */ 1773 # define TVDAC_A_SENSE (1 << 30) 1774 /** Reports that DAC B voltage is above the detect threshold */ 1775 # define TVDAC_B_SENSE (1 << 29) 1776 /** Reports that DAC C voltage is above the detect threshold */ 1777 # define TVDAC_C_SENSE (1 << 28) 1778 /** 1779 * Enables DAC state detection logic, for load-based TV detection. 1780 * 1781 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 1782 * to off, for load detection to work. 1783 */ 1784 # define TVDAC_STATE_CHG_EN (1 << 27) 1785 /** Sets the DAC A sense value to high */ 1786 # define TVDAC_A_SENSE_CTL (1 << 26) 1787 /** Sets the DAC B sense value to high */ 1788 # define TVDAC_B_SENSE_CTL (1 << 25) 1789 /** Sets the DAC C sense value to high */ 1790 # define TVDAC_C_SENSE_CTL (1 << 24) 1791 /** Overrides the ENC_ENABLE and DAC voltage levels */ 1792 # define DAC_CTL_OVERRIDE (1 << 7) 1793 /** Sets the slew rate. Must be preserved in software */ 1794 # define ENC_TVDAC_SLEW_FAST (1 << 6) 1795 # define DAC_A_1_3_V (0 << 4) 1796 # define DAC_A_1_1_V (1 << 4) 1797 # define DAC_A_0_7_V (2 << 4) 1798 # define DAC_A_MASK (3 << 4) 1799 # define DAC_B_1_3_V (0 << 2) 1800 # define DAC_B_1_1_V (1 << 2) 1801 # define DAC_B_0_7_V (2 << 2) 1802 # define DAC_B_MASK (3 << 2) 1803 # define DAC_C_1_3_V (0 << 0) 1804 # define DAC_C_1_1_V (1 << 0) 1805 # define DAC_C_0_7_V (2 << 0) 1806 # define DAC_C_MASK (3 << 0) 1807 1808 /** 1809 * CSC coefficients are stored in a floating point format with 9 bits of 1810 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 1811 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 1812 * -1 (0x3) being the only legal negative value. 1813 */ 1814 #define TV_CSC_Y 0x68010 1815 # define TV_RY_MASK 0x07ff0000 1816 # define TV_RY_SHIFT 16 1817 # define TV_GY_MASK 0x00000fff 1818 # define TV_GY_SHIFT 0 1819 1820 #define TV_CSC_Y2 0x68014 1821 # define TV_BY_MASK 0x07ff0000 1822 # define TV_BY_SHIFT 16 1823 /** 1824 * Y attenuation for component video. 1825 * 1826 * Stored in 1.9 fixed point. 1827 */ 1828 # define TV_AY_MASK 0x000003ff 1829 # define TV_AY_SHIFT 0 1830 1831 #define TV_CSC_U 0x68018 1832 # define TV_RU_MASK 0x07ff0000 1833 # define TV_RU_SHIFT 16 1834 # define TV_GU_MASK 0x000007ff 1835 # define TV_GU_SHIFT 0 1836 1837 #define TV_CSC_U2 0x6801c 1838 # define TV_BU_MASK 0x07ff0000 1839 # define TV_BU_SHIFT 16 1840 /** 1841 * U attenuation for component video. 1842 * 1843 * Stored in 1.9 fixed point. 1844 */ 1845 # define TV_AU_MASK 0x000003ff 1846 # define TV_AU_SHIFT 0 1847 1848 #define TV_CSC_V 0x68020 1849 # define TV_RV_MASK 0x0fff0000 1850 # define TV_RV_SHIFT 16 1851 # define TV_GV_MASK 0x000007ff 1852 # define TV_GV_SHIFT 0 1853 1854 #define TV_CSC_V2 0x68024 1855 # define TV_BV_MASK 0x07ff0000 1856 # define TV_BV_SHIFT 16 1857 /** 1858 * V attenuation for component video. 1859 * 1860 * Stored in 1.9 fixed point. 1861 */ 1862 # define TV_AV_MASK 0x000007ff 1863 # define TV_AV_SHIFT 0 1864 1865 #define TV_CLR_KNOBS 0x68028 1866 /** 2s-complement brightness adjustment */ 1867 # define TV_BRIGHTNESS_MASK 0xff000000 1868 # define TV_BRIGHTNESS_SHIFT 24 1869 /** Contrast adjustment, as a 2.6 unsigned floating point number */ 1870 # define TV_CONTRAST_MASK 0x00ff0000 1871 # define TV_CONTRAST_SHIFT 16 1872 /** Saturation adjustment, as a 2.6 unsigned floating point number */ 1873 # define TV_SATURATION_MASK 0x0000ff00 1874 # define TV_SATURATION_SHIFT 8 1875 /** Hue adjustment, as an integer phase angle in degrees */ 1876 # define TV_HUE_MASK 0x000000ff 1877 # define TV_HUE_SHIFT 0 1878 1879 #define TV_CLR_LEVEL 0x6802c 1880 /** Controls the DAC level for black */ 1881 # define TV_BLACK_LEVEL_MASK 0x01ff0000 1882 # define TV_BLACK_LEVEL_SHIFT 16 1883 /** Controls the DAC level for blanking */ 1884 # define TV_BLANK_LEVEL_MASK 0x000001ff 1885 # define TV_BLANK_LEVEL_SHIFT 0 1886 1887 #define TV_H_CTL_1 0x68030 1888 /** Number of pixels in the hsync. */ 1889 # define TV_HSYNC_END_MASK 0x1fff0000 1890 # define TV_HSYNC_END_SHIFT 16 1891 /** Total number of pixels minus one in the line (display and blanking). */ 1892 # define TV_HTOTAL_MASK 0x00001fff 1893 # define TV_HTOTAL_SHIFT 0 1894 1895 #define TV_H_CTL_2 0x68034 1896 /** Enables the colorburst (needed for non-component color) */ 1897 # define TV_BURST_ENA (1UL << 31) 1898 /** Offset of the colorburst from the start of hsync, in pixels minus one. */ 1899 # define TV_HBURST_START_SHIFT 16 1900 # define TV_HBURST_START_MASK 0x1fff0000 1901 /** Length of the colorburst */ 1902 # define TV_HBURST_LEN_SHIFT 0 1903 # define TV_HBURST_LEN_MASK 0x0001fff 1904 1905 #define TV_H_CTL_3 0x68038 1906 /** End of hblank, measured in pixels minus one from start of hsync */ 1907 # define TV_HBLANK_END_SHIFT 16 1908 # define TV_HBLANK_END_MASK 0x1fff0000 1909 /** Start of hblank, measured in pixels minus one from start of hsync */ 1910 # define TV_HBLANK_START_SHIFT 0 1911 # define TV_HBLANK_START_MASK 0x0001fff 1912 1913 #define TV_V_CTL_1 0x6803c 1914 /** XXX */ 1915 # define TV_NBR_END_SHIFT 16 1916 # define TV_NBR_END_MASK 0x07ff0000 1917 /** XXX */ 1918 # define TV_VI_END_F1_SHIFT 8 1919 # define TV_VI_END_F1_MASK 0x00003f00 1920 /** XXX */ 1921 # define TV_VI_END_F2_SHIFT 0 1922 # define TV_VI_END_F2_MASK 0x0000003f 1923 1924 #define TV_V_CTL_2 0x68040 1925 /** Length of vsync, in half lines */ 1926 # define TV_VSYNC_LEN_MASK 0x07ff0000 1927 # define TV_VSYNC_LEN_SHIFT 16 1928 /** Offset of the start of vsync in field 1, measured in one less than the 1929 * number of half lines. 1930 */ 1931 # define TV_VSYNC_START_F1_MASK 0x00007f00 1932 # define TV_VSYNC_START_F1_SHIFT 8 1933 /** 1934 * Offset of the start of vsync in field 2, measured in one less than the 1935 * number of half lines. 1936 */ 1937 # define TV_VSYNC_START_F2_MASK 0x0000007f 1938 # define TV_VSYNC_START_F2_SHIFT 0 1939 1940 #define TV_V_CTL_3 0x68044 1941 /** Enables generation of the equalization signal */ 1942 # define TV_EQUAL_ENA (1UL << 31) 1943 /** Length of vsync, in half lines */ 1944 # define TV_VEQ_LEN_MASK 0x007f0000 1945 # define TV_VEQ_LEN_SHIFT 16 1946 /** Offset of the start of equalization in field 1, measured in one less than 1947 * the number of half lines. 1948 */ 1949 # define TV_VEQ_START_F1_MASK 0x0007f00 1950 # define TV_VEQ_START_F1_SHIFT 8 1951 /** 1952 * Offset of the start of equalization in field 2, measured in one less than 1953 * the number of half lines. 1954 */ 1955 # define TV_VEQ_START_F2_MASK 0x000007f 1956 # define TV_VEQ_START_F2_SHIFT 0 1957 1958 #define TV_V_CTL_4 0x68048 1959 /** 1960 * Offset to start of vertical colorburst, measured in one less than the 1961 * number of lines from vertical start. 1962 */ 1963 # define TV_VBURST_START_F1_MASK 0x003f0000 1964 # define TV_VBURST_START_F1_SHIFT 16 1965 /** 1966 * Offset to the end of vertical colorburst, measured in one less than the 1967 * number of lines from the start of NBR. 1968 */ 1969 # define TV_VBURST_END_F1_MASK 0x000000ff 1970 # define TV_VBURST_END_F1_SHIFT 0 1971 1972 #define TV_V_CTL_5 0x6804c 1973 /** 1974 * Offset to start of vertical colorburst, measured in one less than the 1975 * number of lines from vertical start. 1976 */ 1977 # define TV_VBURST_START_F2_MASK 0x003f0000 1978 # define TV_VBURST_START_F2_SHIFT 16 1979 /** 1980 * Offset to the end of vertical colorburst, measured in one less than the 1981 * number of lines from the start of NBR. 1982 */ 1983 # define TV_VBURST_END_F2_MASK 0x000000ff 1984 # define TV_VBURST_END_F2_SHIFT 0 1985 1986 #define TV_V_CTL_6 0x68050 1987 /** 1988 * Offset to start of vertical colorburst, measured in one less than the 1989 * number of lines from vertical start. 1990 */ 1991 # define TV_VBURST_START_F3_MASK 0x003f0000 1992 # define TV_VBURST_START_F3_SHIFT 16 1993 /** 1994 * Offset to the end of vertical colorburst, measured in one less than the 1995 * number of lines from the start of NBR. 1996 */ 1997 # define TV_VBURST_END_F3_MASK 0x000000ff 1998 # define TV_VBURST_END_F3_SHIFT 0 1999 2000 #define TV_V_CTL_7 0x68054 2001 /** 2002 * Offset to start of vertical colorburst, measured in one less than the 2003 * number of lines from vertical start. 2004 */ 2005 # define TV_VBURST_START_F4_MASK 0x003f0000 2006 # define TV_VBURST_START_F4_SHIFT 16 2007 /** 2008 * Offset to the end of vertical colorburst, measured in one less than the 2009 * number of lines from the start of NBR. 2010 */ 2011 # define TV_VBURST_END_F4_MASK 0x000000ff 2012 # define TV_VBURST_END_F4_SHIFT 0 2013 2014 #define TV_SC_CTL_1 0x68060 2015 /** Turns on the first subcarrier phase generation DDA */ 2016 # define TV_SC_DDA1_EN (1UL << 31) 2017 /** Turns on the first subcarrier phase generation DDA */ 2018 # define TV_SC_DDA2_EN (1 << 30) 2019 /** Turns on the first subcarrier phase generation DDA */ 2020 # define TV_SC_DDA3_EN (1 << 29) 2021 /** Sets the subcarrier DDA to reset frequency every other field */ 2022 # define TV_SC_RESET_EVERY_2 (0 << 24) 2023 /** Sets the subcarrier DDA to reset frequency every fourth field */ 2024 # define TV_SC_RESET_EVERY_4 (1 << 24) 2025 /** Sets the subcarrier DDA to reset frequency every eighth field */ 2026 # define TV_SC_RESET_EVERY_8 (2 << 24) 2027 /** Sets the subcarrier DDA to never reset the frequency */ 2028 # define TV_SC_RESET_NEVER (3 << 24) 2029 /** Sets the peak amplitude of the colorburst.*/ 2030 # define TV_BURST_LEVEL_MASK 0x00ff0000 2031 # define TV_BURST_LEVEL_SHIFT 16 2032 /** Sets the increment of the first subcarrier phase generation DDA */ 2033 # define TV_SCDDA1_INC_MASK 0x00000fff 2034 # define TV_SCDDA1_INC_SHIFT 0 2035 2036 #define TV_SC_CTL_2 0x68064 2037 /** Sets the rollover for the second subcarrier phase generation DDA */ 2038 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 2039 # define TV_SCDDA2_SIZE_SHIFT 16 2040 /** Sets the increment of the second subcarrier phase generation DDA */ 2041 # define TV_SCDDA2_INC_MASK 0x00007fff 2042 # define TV_SCDDA2_INC_SHIFT 0 2043 2044 #define TV_SC_CTL_3 0x68068 2045 /** Sets the rollover for the third subcarrier phase generation DDA */ 2046 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 2047 # define TV_SCDDA3_SIZE_SHIFT 16 2048 /** Sets the increment of the third subcarrier phase generation DDA */ 2049 # define TV_SCDDA3_INC_MASK 0x00007fff 2050 # define TV_SCDDA3_INC_SHIFT 0 2051 2052 #define TV_WIN_POS 0x68070 2053 /** X coordinate of the display from the start of horizontal active */ 2054 # define TV_XPOS_MASK 0x1fff0000 2055 # define TV_XPOS_SHIFT 16 2056 /** Y coordinate of the display from the start of vertical active (NBR) */ 2057 # define TV_YPOS_MASK 0x00000fff 2058 # define TV_YPOS_SHIFT 0 2059 2060 #define TV_WIN_SIZE 0x68074 2061 /** Horizontal size of the display window, measured in pixels*/ 2062 # define TV_XSIZE_MASK 0x1fff0000 2063 # define TV_XSIZE_SHIFT 16 2064 /** 2065 * Vertical size of the display window, measured in pixels. 2066 * 2067 * Must be even for interlaced modes. 2068 */ 2069 # define TV_YSIZE_MASK 0x00000fff 2070 # define TV_YSIZE_SHIFT 0 2071 2072 #define TV_FILTER_CTL_1 0x68080 2073 /** 2074 * Enables automatic scaling calculation. 2075 * 2076 * If set, the rest of the registers are ignored, and the calculated values can 2077 * be read back from the register. 2078 */ 2079 # define TV_AUTO_SCALE (1UL << 31) 2080 /** 2081 * Disables the vertical filter. 2082 * 2083 * This is required on modes more than 1024 pixels wide */ 2084 # define TV_V_FILTER_BYPASS (1 << 29) 2085 /** Enables adaptive vertical filtering */ 2086 # define TV_VADAPT (1 << 28) 2087 # define TV_VADAPT_MODE_MASK (3 << 26) 2088 /** Selects the least adaptive vertical filtering mode */ 2089 # define TV_VADAPT_MODE_LEAST (0 << 26) 2090 /** Selects the moderately adaptive vertical filtering mode */ 2091 # define TV_VADAPT_MODE_MODERATE (1 << 26) 2092 /** Selects the most adaptive vertical filtering mode */ 2093 # define TV_VADAPT_MODE_MOST (3 << 26) 2094 /** 2095 * Sets the horizontal scaling factor. 2096 * 2097 * This should be the fractional part of the horizontal scaling factor divided 2098 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 2099 * 2100 * (src width - 1) / ((oversample * dest width) - 1) 2101 */ 2102 # define TV_HSCALE_FRAC_MASK 0x00003fff 2103 # define TV_HSCALE_FRAC_SHIFT 0 2104 2105 #define TV_FILTER_CTL_2 0x68084 2106 /** 2107 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 2108 * 2109 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 2110 */ 2111 # define TV_VSCALE_INT_MASK 0x00038000 2112 # define TV_VSCALE_INT_SHIFT 15 2113 /** 2114 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 2115 * 2116 * \sa TV_VSCALE_INT_MASK 2117 */ 2118 # define TV_VSCALE_FRAC_MASK 0x00007fff 2119 # define TV_VSCALE_FRAC_SHIFT 0 2120 2121 #define TV_FILTER_CTL_3 0x68088 2122 /** 2123 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 2124 * 2125 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 2126 * 2127 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 2128 */ 2129 # define TV_VSCALE_IP_INT_MASK 0x00038000 2130 # define TV_VSCALE_IP_INT_SHIFT 15 2131 /** 2132 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 2133 * 2134 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 2135 * 2136 * \sa TV_VSCALE_IP_INT_MASK 2137 */ 2138 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 2139 # define TV_VSCALE_IP_FRAC_SHIFT 0 2140 2141 #define TV_CC_CONTROL 0x68090 2142 # define TV_CC_ENABLE (1UL << 31) 2143 /** 2144 * Specifies which field to send the CC data in. 2145 * 2146 * CC data is usually sent in field 0. 2147 */ 2148 # define TV_CC_FID_MASK (1 << 27) 2149 # define TV_CC_FID_SHIFT 27 2150 /** Sets the horizontal position of the CC data. Usually 135. */ 2151 # define TV_CC_HOFF_MASK 0x03ff0000 2152 # define TV_CC_HOFF_SHIFT 16 2153 /** Sets the vertical position of the CC data. Usually 21 */ 2154 # define TV_CC_LINE_MASK 0x0000003f 2155 # define TV_CC_LINE_SHIFT 0 2156 2157 #define TV_CC_DATA 0x68094 2158 # define TV_CC_RDY (1UL << 31) 2159 /** Second word of CC data to be transmitted. */ 2160 # define TV_CC_DATA_2_MASK 0x007f0000 2161 # define TV_CC_DATA_2_SHIFT 16 2162 /** First word of CC data to be transmitted. */ 2163 # define TV_CC_DATA_1_MASK 0x0000007f 2164 # define TV_CC_DATA_1_SHIFT 0 2165 2166 #define TV_H_LUMA_0 0x68100 2167 #define TV_H_LUMA_59 0x681ec 2168 #define TV_H_CHROMA_0 0x68200 2169 #define TV_H_CHROMA_59 0x682ec 2170 #define TV_V_LUMA_0 0x68300 2171 #define TV_V_LUMA_42 0x683a8 2172 #define TV_V_CHROMA_0 0x68400 2173 #define TV_V_CHROMA_42 0x684a8 2174 2175 /* Display Port */ 2176 #define DP_A 0x64000 /* eDP */ 2177 #define DP_B 0x64100 2178 #define DP_C 0x64200 2179 #define DP_D 0x64300 2180 2181 #define DP_PORT_EN (1UL << 31) 2182 #define DP_PIPEB_SELECT (1 << 30) 2183 #define DP_PIPE_MASK (1 << 30) 2184 2185 /* Link training mode - select a suitable mode for each stage */ 2186 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 2187 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 2188 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 2189 #define DP_LINK_TRAIN_OFF (3 << 28) 2190 #define DP_LINK_TRAIN_MASK (3 << 28) 2191 #define DP_LINK_TRAIN_SHIFT 28 2192 2193 /* CPT Link training mode */ 2194 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 2195 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 2196 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 2197 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 2198 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 2199 #define DP_LINK_TRAIN_SHIFT_CPT 8 2200 2201 /* Signal voltages. These are mostly controlled by the other end */ 2202 #define DP_VOLTAGE_0_4 (0 << 25) 2203 #define DP_VOLTAGE_0_6 (1 << 25) 2204 #define DP_VOLTAGE_0_8 (2 << 25) 2205 #define DP_VOLTAGE_1_2 (3 << 25) 2206 #define DP_VOLTAGE_MASK (7 << 25) 2207 #define DP_VOLTAGE_SHIFT 25 2208 2209 /* Signal pre-emphasis levels, like voltages, the other end tells us what 2210 * they want 2211 */ 2212 #define DP_PRE_EMPHASIS_0 (0 << 22) 2213 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 2214 #define DP_PRE_EMPHASIS_6 (2 << 22) 2215 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 2216 #define DP_PRE_EMPHASIS_MASK (7 << 22) 2217 #define DP_PRE_EMPHASIS_SHIFT 22 2218 2219 /* How many wires to use. I guess 3 was too hard */ 2220 #define DP_PORT_WIDTH_1 (0 << 19) 2221 #define DP_PORT_WIDTH_2 (1 << 19) 2222 #define DP_PORT_WIDTH_4 (3 << 19) 2223 #define DP_PORT_WIDTH_MASK (7 << 19) 2224 2225 /* Mystic DPCD version 1.1 special mode */ 2226 #define DP_ENHANCED_FRAMING (1 << 18) 2227 2228 /* eDP */ 2229 #define DP_PLL_FREQ_270MHZ (0 << 16) 2230 #define DP_PLL_FREQ_160MHZ (1 << 16) 2231 #define DP_PLL_FREQ_MASK (3 << 16) 2232 2233 /** locked once port is enabled */ 2234 #define DP_PORT_REVERSAL (1 << 15) 2235 2236 /* eDP */ 2237 #define DP_PLL_ENABLE (1 << 14) 2238 2239 /** sends the clock on lane 15 of the PEG for debug */ 2240 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 2241 2242 #define DP_SCRAMBLING_DISABLE (1 << 12) 2243 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 2244 2245 /** limit RGB values to avoid confusing TVs */ 2246 #define DP_COLOR_RANGE_16_235 (1 << 8) 2247 2248 /** Turn on the audio link */ 2249 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 2250 2251 /** vs and hs sync polarity */ 2252 #define DP_SYNC_VS_HIGH (1 << 4) 2253 #define DP_SYNC_HS_HIGH (1 << 3) 2254 2255 /** A fantasy */ 2256 #define DP_DETECTED (1 << 2) 2257 2258 /** The aux channel provides a way to talk to the 2259 * signal sink for DDC etc. Max packet size supported 2260 * is 20 bytes in each direction, hence the 5 fixed 2261 * data registers 2262 */ 2263 #define DPA_AUX_CH_CTL 0x64010 2264 #define DPA_AUX_CH_DATA1 0x64014 2265 #define DPA_AUX_CH_DATA2 0x64018 2266 #define DPA_AUX_CH_DATA3 0x6401c 2267 #define DPA_AUX_CH_DATA4 0x64020 2268 #define DPA_AUX_CH_DATA5 0x64024 2269 2270 #define DPB_AUX_CH_CTL 0x64110 2271 #define DPB_AUX_CH_DATA1 0x64114 2272 #define DPB_AUX_CH_DATA2 0x64118 2273 #define DPB_AUX_CH_DATA3 0x6411c 2274 #define DPB_AUX_CH_DATA4 0x64120 2275 #define DPB_AUX_CH_DATA5 0x64124 2276 2277 #define DPC_AUX_CH_CTL 0x64210 2278 #define DPC_AUX_CH_DATA1 0x64214 2279 #define DPC_AUX_CH_DATA2 0x64218 2280 #define DPC_AUX_CH_DATA3 0x6421c 2281 #define DPC_AUX_CH_DATA4 0x64220 2282 #define DPC_AUX_CH_DATA5 0x64224 2283 2284 #define DPD_AUX_CH_CTL 0x64310 2285 #define DPD_AUX_CH_DATA1 0x64314 2286 #define DPD_AUX_CH_DATA2 0x64318 2287 #define DPD_AUX_CH_DATA3 0x6431c 2288 #define DPD_AUX_CH_DATA4 0x64320 2289 #define DPD_AUX_CH_DATA5 0x64324 2290 2291 #define DP_AUX_CH_CTL_SEND_BUSY (1UL << 31) 2292 #define DP_AUX_CH_CTL_DONE (1 << 30) 2293 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 2294 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 2295 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 2296 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 2297 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 2298 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) 2299 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 2300 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 2301 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 2302 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 2303 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 2304 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 2305 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 2306 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 2307 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 2308 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 2309 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 2310 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 2311 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 2312 2313 /* 2314 * Computing GMCH M and N values for the Display Port link 2315 * 2316 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 2317 * 2318 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 2319 * 2320 * The GMCH value is used internally 2321 * 2322 * bytes_per_pixel is the number of bytes coming out of the plane, 2323 * which is after the LUTs, so we want the bytes for our color format. 2324 * For our current usage, this is always 3, one byte for R, G and B. 2325 */ 2326 #define _PIPEA_GMCH_DATA_M 0x70050 2327 #define _PIPEB_GMCH_DATA_M 0x71050 2328 2329 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 2330 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) 2331 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 2332 2333 #define PIPE_GMCH_DATA_M_MASK (0xffffff) 2334 2335 #define _PIPEA_GMCH_DATA_N 0x70054 2336 #define _PIPEB_GMCH_DATA_N 0x71054 2337 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 2338 2339 /* 2340 * Computing Link M and N values for the Display Port link 2341 * 2342 * Link M / N = pixel_clock / ls_clk 2343 * 2344 * (the DP spec calls pixel_clock the 'strm_clk') 2345 * 2346 * The Link value is transmitted in the Main Stream 2347 * Attributes and VB-ID. 2348 */ 2349 2350 #define _PIPEA_DP_LINK_M 0x70060 2351 #define _PIPEB_DP_LINK_M 0x71060 2352 #define PIPEA_DP_LINK_M_MASK (0xffffff) 2353 2354 #define _PIPEA_DP_LINK_N 0x70064 2355 #define _PIPEB_DP_LINK_N 0x71064 2356 #define PIPEA_DP_LINK_N_MASK (0xffffff) 2357 2358 #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M) 2359 #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N) 2360 #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M) 2361 #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N) 2362 2363 /* Display & cursor control */ 2364 2365 /* Pipe A */ 2366 #define _PIPEADSL 0x70000 2367 #define DSL_LINEMASK_GEN2 0x00000fff 2368 #define DSL_LINEMASK_GEN3 0x00001fff 2369 #define _PIPEACONF 0x70008 2370 #define PIPECONF_ENABLE (1UL<<31) 2371 #define PIPECONF_DISABLE 0 2372 #define PIPECONF_DOUBLE_WIDE (1<<30) 2373 #define I965_PIPECONF_ACTIVE (1<<30) 2374 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) 2375 #define PIPECONF_SINGLE_WIDE 0 2376 #define PIPECONF_PIPE_UNLOCKED 0 2377 #define PIPECONF_PIPE_LOCKED (1<<25) 2378 #define PIPECONF_PALETTE 0 2379 #define PIPECONF_GAMMA (1<<24) 2380 #define PIPECONF_FORCE_BORDER (1<<25) 2381 #define PIPECONF_INTERLACE_MASK (7 << 21) 2382 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) 2383 /* Note that pre-gen3 does not support interlaced display directly. Panel 2384 * fitting must be disabled on pre-ilk for interlaced. */ 2385 #define PIPECONF_PROGRESSIVE (0 << 21) 2386 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ 2387 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ 2388 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 2389 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ 2390 /* Ironlake and later have a complete new set of values for interlaced. PFIT 2391 * means panel fitter required, PF means progressive fetch, DBL means power 2392 * saving pixel doubling. */ 2393 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) 2394 #define PIPECONF_INTERLACED_ILK (3 << 21) 2395 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ 2396 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ 2397 #define PIPECONF_CXSR_DOWNCLOCK (1<<16) 2398 #define PIPECONF_BPP_MASK (0x000000e0) 2399 #define PIPECONF_BPP_8 (0<<5) 2400 #define PIPECONF_BPP_10 (1<<5) 2401 #define PIPECONF_BPP_6 (2<<5) 2402 #define PIPECONF_BPP_12 (3<<5) 2403 #define PIPECONF_DITHER_EN (1<<4) 2404 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 2405 #define PIPECONF_DITHER_TYPE_SP (0<<2) 2406 #define PIPECONF_DITHER_TYPE_ST1 (1<<2) 2407 #define PIPECONF_DITHER_TYPE_ST2 (2<<2) 2408 #define PIPECONF_DITHER_TYPE_TEMP (3<<2) 2409 #define _PIPEASTAT 0x70024 2410 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 2411 #define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30) 2412 #define PIPE_CRC_ERROR_ENABLE (1UL<<29) 2413 #define PIPE_CRC_DONE_ENABLE (1UL<<28) 2414 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 2415 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) 2416 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 2417 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 2418 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 2419 #define PIPE_DPST_EVENT_ENABLE (1UL<<23) 2420 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<26) 2421 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 2422 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 2423 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 2424 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 2425 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 2426 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 2427 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) 2428 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 2429 #define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15) 2430 #define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<15) 2431 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 2432 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 2433 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 2434 #define PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10) 2435 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 2436 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 2437 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 2438 #define PIPE_DPST_EVENT_STATUS (1UL<<7) 2439 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 2440 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 2441 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 2442 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 2443 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 2444 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 2445 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 2446 #define PIPE_BPC_MASK (7 << 5) /* Ironlake */ 2447 #define PIPE_8BPC (0 << 5) 2448 #define PIPE_10BPC (1 << 5) 2449 #define PIPE_6BPC (2 << 5) 2450 #define PIPE_12BPC (3 << 5) 2451 2452 #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) 2453 #define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF) 2454 #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) 2455 #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) 2456 #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) 2457 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) 2458 2459 #define VLV_DPFLIPSTAT 0x70028 2460 #define PIPEB_LINE_COMPARE_INT_EN (1<<29) 2461 #define PIPEB_HLINE_INT_EN (1<<28) 2462 #define PIPEB_VBLANK_INT_EN (1<<27) 2463 #define SPRITED_FLIPDONE_INT_EN (1<<26) 2464 #define SPRITEC_FLIPDONE_INT_EN (1<<25) 2465 #define PLANEB_FLIPDONE_INT_EN (1<<24) 2466 #define PIPEA_LINE_COMPARE_INT_EN (1<<21) 2467 #define PIPEA_HLINE_INT_EN (1<<20) 2468 #define PIPEA_VBLANK_INT_EN (1<<19) 2469 #define SPRITEB_FLIPDONE_INT_EN (1<<18) 2470 #define SPRITEA_FLIPDONE_INT_EN (1<<17) 2471 #define PLANEA_FLIPDONE_INT_EN (1<<16) 2472 2473 #define DPINVGTT 0x7002c /* VLV only */ 2474 #define CURSORB_INVALID_GTT_INT_EN (1<<23) 2475 #define CURSORA_INVALID_GTT_INT_EN (1<<22) 2476 #define SPRITED_INVALID_GTT_INT_EN (1<<21) 2477 #define SPRITEC_INVALID_GTT_INT_EN (1<<20) 2478 #define PLANEB_INVALID_GTT_INT_EN (1<<19) 2479 #define SPRITEB_INVALID_GTT_INT_EN (1<<18) 2480 #define SPRITEA_INVALID_GTT_INT_EN (1<<17) 2481 #define PLANEA_INVALID_GTT_INT_EN (1<<16) 2482 #define DPINVGTT_EN_MASK 0xff0000 2483 #define CURSORB_INVALID_GTT_STATUS (1<<7) 2484 #define CURSORA_INVALID_GTT_STATUS (1<<6) 2485 #define SPRITED_INVALID_GTT_STATUS (1<<5) 2486 #define SPRITEC_INVALID_GTT_STATUS (1<<4) 2487 #define PLANEB_INVALID_GTT_STATUS (1<<3) 2488 #define SPRITEB_INVALID_GTT_STATUS (1<<2) 2489 #define SPRITEA_INVALID_GTT_STATUS (1<<1) 2490 #define PLANEA_INVALID_GTT_STATUS (1<<0) 2491 #define DPINVGTT_STATUS_MASK 0xff 2492 2493 #define DSPARB 0x70030 2494 #define DSPARB_CSTART_MASK (0x7f << 7) 2495 #define DSPARB_CSTART_SHIFT 7 2496 #define DSPARB_BSTART_MASK (0x7f) 2497 #define DSPARB_BSTART_SHIFT 0 2498 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 2499 #define DSPARB_AEND_SHIFT 0 2500 2501 #define DSPFW1 0x70034 2502 #define DSPFW_SR_SHIFT 23 2503 #define DSPFW_SR_MASK (0x1ff<<23) 2504 #define DSPFW_CURSORB_SHIFT 16 2505 #define DSPFW_CURSORB_MASK (0x3f<<16) 2506 #define DSPFW_PLANEB_SHIFT 8 2507 #define DSPFW_PLANEB_MASK (0x7f<<8) 2508 #define DSPFW_PLANEA_MASK (0x7f) 2509 #define DSPFW2 0x70038 2510 #define DSPFW_CURSORA_MASK 0x00003f00 2511 #define DSPFW_CURSORA_SHIFT 8 2512 #define DSPFW_PLANEC_MASK (0x7f) 2513 #define DSPFW3 0x7003c 2514 #define DSPFW_HPLL_SR_EN (1UL<<31) 2515 #define DSPFW_CURSOR_SR_SHIFT 24 2516 #define PINEVIEW_SELF_REFRESH_EN (1<<30) 2517 #define DSPFW_CURSOR_SR_MASK (0x3f<<24) 2518 #define DSPFW_HPLL_CURSOR_SHIFT 16 2519 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 2520 #define DSPFW_HPLL_SR_MASK (0x1ff) 2521 2522 /* drain latency register values*/ 2523 #define DRAIN_LATENCY_PRECISION_32 32 2524 #define DRAIN_LATENCY_PRECISION_16 16 2525 #define VLV_DDL1 0x70050 2526 #define DDL_CURSORA_PRECISION_32 (1UL<<31) 2527 #define DDL_CURSORA_PRECISION_16 (0UL<<31) 2528 #define DDL_CURSORA_SHIFT 24 2529 #define DDL_PLANEA_PRECISION_32 (1<<7) 2530 #define DDL_PLANEA_PRECISION_16 (0<<7) 2531 #define VLV_DDL2 0x70054 2532 #define DDL_CURSORB_PRECISION_32 (1UL<<31) 2533 #define DDL_CURSORB_PRECISION_16 (0UL<<31) 2534 #define DDL_CURSORB_SHIFT 24 2535 #define DDL_PLANEB_PRECISION_32 (1<<7) 2536 #define DDL_PLANEB_PRECISION_16 (0<<7) 2537 2538 /* FIFO watermark sizes etc */ 2539 #define G4X_FIFO_LINE_SIZE 64 2540 #define I915_FIFO_LINE_SIZE 64 2541 #define I830_FIFO_LINE_SIZE 32 2542 2543 #define VALLEYVIEW_FIFO_SIZE 255 2544 #define G4X_FIFO_SIZE 127 2545 #define I965_FIFO_SIZE 512 2546 #define I945_FIFO_SIZE 127 2547 #define I915_FIFO_SIZE 95 2548 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 2549 #define I830_FIFO_SIZE 95 2550 2551 #define VALLEYVIEW_MAX_WM 0xff 2552 #define G4X_MAX_WM 0x3f 2553 #define I915_MAX_WM 0x3f 2554 2555 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 2556 #define PINEVIEW_FIFO_LINE_SIZE 64 2557 #define PINEVIEW_MAX_WM 0x1ff 2558 #define PINEVIEW_DFT_WM 0x3f 2559 #define PINEVIEW_DFT_HPLLOFF_WM 0 2560 #define PINEVIEW_GUARD_WM 10 2561 #define PINEVIEW_CURSOR_FIFO 64 2562 #define PINEVIEW_CURSOR_MAX_WM 0x3f 2563 #define PINEVIEW_CURSOR_DFT_WM 0 2564 #define PINEVIEW_CURSOR_GUARD_WM 5 2565 2566 #define VALLEYVIEW_CURSOR_MAX_WM 64 2567 #define I965_CURSOR_FIFO 64 2568 #define I965_CURSOR_MAX_WM 32 2569 #define I965_CURSOR_DFT_WM 8 2570 2571 /* define the Watermark register on Ironlake */ 2572 #define WM0_PIPEA_ILK 0x45100 2573 #define WM0_PIPE_PLANE_MASK (0x7f<<16) 2574 #define WM0_PIPE_PLANE_SHIFT 16 2575 #define WM0_PIPE_SPRITE_MASK (0x3f<<8) 2576 #define WM0_PIPE_SPRITE_SHIFT 8 2577 #define WM0_PIPE_CURSOR_MASK (0x1f) 2578 2579 #define WM0_PIPEB_ILK 0x45104 2580 #define WM0_PIPEC_IVB 0x45200 2581 #define WM1_LP_ILK 0x45108 2582 #define WM1_LP_SR_EN (1UL<<31) 2583 #define WM1_LP_LATENCY_SHIFT 24 2584 #define WM1_LP_LATENCY_MASK (0x7f<<24) 2585 #define WM1_LP_FBC_MASK (0xf<<20) 2586 #define WM1_LP_FBC_SHIFT 20 2587 #define WM1_LP_SR_MASK (0x1ff<<8) 2588 #define WM1_LP_SR_SHIFT 8 2589 #define WM1_LP_CURSOR_MASK (0x3f) 2590 #define WM2_LP_ILK 0x4510c 2591 #define WM2_LP_EN (1UL<<31) 2592 #define WM3_LP_ILK 0x45110 2593 #define WM3_LP_EN (1UL<<31) 2594 #define WM1S_LP_ILK 0x45120 2595 #define WM2S_LP_IVB 0x45124 2596 #define WM3S_LP_IVB 0x45128 2597 #define WM1S_LP_EN (1UL<<31) 2598 2599 /* Memory latency timer register */ 2600 #define MLTR_ILK 0x11222 2601 #define MLTR_WM1_SHIFT 0 2602 #define MLTR_WM2_SHIFT 8 2603 /* the unit of memory self-refresh latency time is 0.5us */ 2604 #define ILK_SRLT_MASK 0x3f 2605 #define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK) 2606 #define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT) 2607 #define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT) 2608 2609 /* define the fifo size on Ironlake */ 2610 #define ILK_DISPLAY_FIFO 128 2611 #define ILK_DISPLAY_MAXWM 64 2612 #define ILK_DISPLAY_DFTWM 8 2613 #define ILK_CURSOR_FIFO 32 2614 #define ILK_CURSOR_MAXWM 16 2615 #define ILK_CURSOR_DFTWM 8 2616 2617 #define ILK_DISPLAY_SR_FIFO 512 2618 #define ILK_DISPLAY_MAX_SRWM 0x1ff 2619 #define ILK_DISPLAY_DFT_SRWM 0x3f 2620 #define ILK_CURSOR_SR_FIFO 64 2621 #define ILK_CURSOR_MAX_SRWM 0x3f 2622 #define ILK_CURSOR_DFT_SRWM 8 2623 2624 #define ILK_FIFO_LINE_SIZE 64 2625 2626 /* define the WM info on Sandybridge */ 2627 #define SNB_DISPLAY_FIFO 128 2628 #define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */ 2629 #define SNB_DISPLAY_DFTWM 8 2630 #define SNB_CURSOR_FIFO 32 2631 #define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */ 2632 #define SNB_CURSOR_DFTWM 8 2633 2634 #define SNB_DISPLAY_SR_FIFO 512 2635 #define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */ 2636 #define SNB_DISPLAY_DFT_SRWM 0x3f 2637 #define SNB_CURSOR_SR_FIFO 64 2638 #define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */ 2639 #define SNB_CURSOR_DFT_SRWM 8 2640 2641 #define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */ 2642 2643 #define SNB_FIFO_LINE_SIZE 64 2644 2645 /* 2646 * The two pipe frame counter registers are not synchronized, so 2647 * reading a stable value is somewhat tricky. The following code 2648 * should work: 2649 * 2650 * do { 2651 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2652 * PIPE_FRAME_HIGH_SHIFT; 2653 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 2654 * PIPE_FRAME_LOW_SHIFT); 2655 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2656 * PIPE_FRAME_HIGH_SHIFT); 2657 * } while (high1 != high2); 2658 * frame = (high1 << 8) | low1; 2659 */ 2660 #define _PIPEAFRAMEHIGH 0x70040 2661 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 2662 #define PIPE_FRAME_HIGH_SHIFT 0 2663 #define _PIPEAFRAMEPIXEL 0x70044 2664 #define PIPE_FRAME_LOW_MASK 0xff000000 2665 #define PIPE_FRAME_LOW_SHIFT 24 2666 #define PIPE_PIXEL_MASK 0x00ffffff 2667 #define PIPE_PIXEL_SHIFT 0 2668 /* GM45+ just has to be different */ 2669 #define _PIPEA_FRMCOUNT_GM45 0x70040 2670 #define _PIPEA_FLIPCOUNT_GM45 0x70044 2671 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45) 2672 2673 /* Cursor A & B regs */ 2674 #define _CURACNTR 0x70080 2675 /* Old style CUR*CNTR flags (desktop 8xx) */ 2676 #define CURSOR_ENABLE 0x80000000 2677 #define CURSOR_GAMMA_ENABLE 0x40000000 2678 #define CURSOR_STRIDE_MASK 0x30000000 2679 #define CURSOR_FORMAT_SHIFT 24 2680 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 2681 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 2682 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 2683 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 2684 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 2685 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 2686 /* New style CUR*CNTR flags */ 2687 #define CURSOR_MODE 0x27 2688 #define CURSOR_MODE_DISABLE 0x00 2689 #define CURSOR_MODE_64_32B_AX 0x07 2690 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 2691 #define MCURSOR_PIPE_SELECT (1 << 28) 2692 #define MCURSOR_PIPE_A 0x00 2693 #define MCURSOR_PIPE_B (1 << 28) 2694 #define MCURSOR_GAMMA_ENABLE (1 << 26) 2695 #define _CURABASE 0x70084 2696 #define _CURAPOS 0x70088 2697 #define CURSOR_POS_MASK 0x007FF 2698 #define CURSOR_POS_SIGN 0x8000 2699 #define CURSOR_X_SHIFT 0 2700 #define CURSOR_Y_SHIFT 16 2701 #define CURSIZE 0x700a0 2702 #define _CURBCNTR 0x700c0 2703 #define _CURBBASE 0x700c4 2704 #define _CURBPOS 0x700c8 2705 2706 #define _CURBCNTR_IVB 0x71080 2707 #define _CURBBASE_IVB 0x71084 2708 #define _CURBPOS_IVB 0x71088 2709 2710 #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR) 2711 #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE) 2712 #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS) 2713 2714 #define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB) 2715 #define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB) 2716 #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB) 2717 2718 /* Display A control */ 2719 #define _DSPACNTR 0x70180 2720 #define DISPLAY_PLANE_ENABLE (1UL<<31) 2721 #define DISPLAY_PLANE_DISABLE 0 2722 #define DISPPLANE_GAMMA_ENABLE (1<<30) 2723 #define DISPPLANE_GAMMA_DISABLE 0 2724 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 2725 #define DISPPLANE_YUV422 (0x0<<26) 2726 #define DISPPLANE_8BPP (0x2<<26) 2727 #define DISPPLANE_BGRA555 (0x3<<26) 2728 #define DISPPLANE_BGRX555 (0x4<<26) 2729 #define DISPPLANE_BGRX565 (0x5<<26) 2730 #define DISPPLANE_BGRX888 (0x6<<26) 2731 #define DISPPLANE_BGRA888 (0x7<<26) 2732 #define DISPPLANE_RGBX101010 (0x8<<26) 2733 #define DISPPLANE_RGBA101010 (0x9<<26) 2734 #define DISPPLANE_BGRX101010 (0xa<<26) 2735 #define DISPPLANE_RGBX161616 (0xc<<26) 2736 #define DISPPLANE_RGBX888 (0xe<<26) 2737 #define DISPPLANE_RGBA888 (0xf<<26) 2738 #define DISPPLANE_STEREO_ENABLE (1<<25) 2739 #define DISPPLANE_STEREO_DISABLE 0 2740 #define DISPPLANE_SEL_PIPE_SHIFT 24 2741 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) 2742 #define DISPPLANE_SEL_PIPE_A 0 2743 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) 2744 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 2745 #define DISPPLANE_SRC_KEY_DISABLE 0 2746 #define DISPPLANE_LINE_DOUBLE (1<<20) 2747 #define DISPPLANE_NO_LINE_DOUBLE 0 2748 #define DISPPLANE_STEREO_POLARITY_FIRST 0 2749 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 2750 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 2751 #define DISPPLANE_TILED (1<<10) 2752 #define _DSPAADDR 0x70184 2753 #define _DSPASTRIDE 0x70188 2754 #define _DSPAPOS 0x7018C /* reserved */ 2755 #define _DSPASIZE 0x70190 2756 #define _DSPASURF 0x7019C /* 965+ only */ 2757 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 2758 #define _DSPAOFFSET 0x701A4 /* HSW */ 2759 #define _DSPASURFLIVE 0x701AC 2760 2761 #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) 2762 #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) 2763 #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE) 2764 #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS) 2765 #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE) 2766 #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) 2767 #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) 2768 #define DSPLINOFF(plane) DSPADDR(plane) 2769 #define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET) 2770 #define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE) 2771 2772 /* Display/Sprite base address macros */ 2773 #define DISP_BASEADDR_MASK (0xfffff000) 2774 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) 2775 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) 2776 #define I915_MODIFY_DISPBASE(reg, gfx_addr) \ 2777 (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg)))) 2778 2779 /* VBIOS flags */ 2780 #define SWF00 0x71410 2781 #define SWF01 0x71414 2782 #define SWF02 0x71418 2783 #define SWF03 0x7141c 2784 #define SWF04 0x71420 2785 #define SWF05 0x71424 2786 #define SWF06 0x71428 2787 #define SWF10 0x70410 2788 #define SWF11 0x70414 2789 #define SWF14 0x71420 2790 #define SWF30 0x72414 2791 #define SWF31 0x72418 2792 #define SWF32 0x7241c 2793 2794 /* Pipe B */ 2795 #define _PIPEBDSL 0x71000 2796 #define _PIPEBCONF 0x71008 2797 #define _PIPEBSTAT 0x71024 2798 #define _PIPEBFRAMEHIGH 0x71040 2799 #define _PIPEBFRAMEPIXEL 0x71044 2800 #define _PIPEB_FRMCOUNT_GM45 0x71040 2801 #define _PIPEB_FLIPCOUNT_GM45 0x71044 2802 2803 /* Display B control */ 2804 #define _DSPBCNTR 0x71180 2805 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 2806 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 2807 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 2808 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 2809 #define _DSPBADDR 0x71184 2810 #define _DSPBSTRIDE 0x71188 2811 #define _DSPBPOS 0x7118C 2812 #define _DSPBSIZE 0x71190 2813 #define _DSPBSURF 0x7119C 2814 #define _DSPBTILEOFF 0x711A4 2815 #define _DSPBOFFSET 0x711A4 2816 #define _DSPBSURFLIVE 0x711AC 2817 2818 /* Sprite A control */ 2819 #define _DVSACNTR 0x72180 2820 #define DVS_ENABLE (1UL<<31) 2821 #define DVS_GAMMA_ENABLE (1<<30) 2822 #define DVS_PIXFORMAT_MASK (3<<25) 2823 #define DVS_FORMAT_YUV422 (0<<25) 2824 #define DVS_FORMAT_RGBX101010 (1<<25) 2825 #define DVS_FORMAT_RGBX888 (2<<25) 2826 #define DVS_FORMAT_RGBX161616 (3<<25) 2827 #define DVS_SOURCE_KEY (1<<22) 2828 #define DVS_RGB_ORDER_XBGR (1<<20) 2829 #define DVS_YUV_BYTE_ORDER_MASK (3<<16) 2830 #define DVS_YUV_ORDER_YUYV (0<<16) 2831 #define DVS_YUV_ORDER_UYVY (1<<16) 2832 #define DVS_YUV_ORDER_YVYU (2<<16) 2833 #define DVS_YUV_ORDER_VYUY (3<<16) 2834 #define DVS_DEST_KEY (1<<2) 2835 #define DVS_TRICKLE_FEED_DISABLE (1<<14) 2836 #define DVS_TILED (1<<10) 2837 #define _DVSALINOFF 0x72184 2838 #define _DVSASTRIDE 0x72188 2839 #define _DVSAPOS 0x7218c 2840 #define _DVSASIZE 0x72190 2841 #define _DVSAKEYVAL 0x72194 2842 #define _DVSAKEYMSK 0x72198 2843 #define _DVSASURF 0x7219c 2844 #define _DVSAKEYMAXVAL 0x721a0 2845 #define _DVSATILEOFF 0x721a4 2846 #define _DVSASURFLIVE 0x721ac 2847 #define _DVSASCALE 0x72204 2848 #define DVS_SCALE_ENABLE (1UL<<31) 2849 #define DVS_FILTER_MASK (3<<29) 2850 #define DVS_FILTER_MEDIUM (0<<29) 2851 #define DVS_FILTER_ENHANCING (1<<29) 2852 #define DVS_FILTER_SOFTENING (2<<29) 2853 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 2854 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) 2855 #define _DVSAGAMC 0x72300 2856 2857 #define _DVSBCNTR 0x73180 2858 #define _DVSBLINOFF 0x73184 2859 #define _DVSBSTRIDE 0x73188 2860 #define _DVSBPOS 0x7318c 2861 #define _DVSBSIZE 0x73190 2862 #define _DVSBKEYVAL 0x73194 2863 #define _DVSBKEYMSK 0x73198 2864 #define _DVSBSURF 0x7319c 2865 #define _DVSBKEYMAXVAL 0x731a0 2866 #define _DVSBTILEOFF 0x731a4 2867 #define _DVSBSURFLIVE 0x731ac 2868 #define _DVSBSCALE 0x73204 2869 #define _DVSBGAMC 0x73300 2870 2871 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) 2872 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 2873 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 2874 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) 2875 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) 2876 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 2877 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) 2878 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) 2879 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 2880 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 2881 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 2882 #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 2883 2884 #define _SPRA_CTL 0x70280 2885 #define SPRITE_ENABLE (1UL<<31) 2886 #define SPRITE_GAMMA_ENABLE (1<<30) 2887 #define SPRITE_PIXFORMAT_MASK (7<<25) 2888 #define SPRITE_FORMAT_YUV422 (0<<25) 2889 #define SPRITE_FORMAT_RGBX101010 (1<<25) 2890 #define SPRITE_FORMAT_RGBX888 (2<<25) 2891 #define SPRITE_FORMAT_RGBX161616 (3<<25) 2892 #define SPRITE_FORMAT_YUV444 (4<<25) 2893 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ 2894 #define SPRITE_CSC_ENABLE (1<<24) 2895 #define SPRITE_SOURCE_KEY (1<<22) 2896 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ 2897 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) 2898 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ 2899 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) 2900 #define SPRITE_YUV_ORDER_YUYV (0<<16) 2901 #define SPRITE_YUV_ORDER_UYVY (1<<16) 2902 #define SPRITE_YUV_ORDER_YVYU (2<<16) 2903 #define SPRITE_YUV_ORDER_VYUY (3<<16) 2904 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) 2905 #define SPRITE_INT_GAMMA_ENABLE (1<<13) 2906 #define SPRITE_TILED (1<<10) 2907 #define SPRITE_DEST_KEY (1<<2) 2908 #define _SPRA_LINOFF 0x70284 2909 #define _SPRA_STRIDE 0x70288 2910 #define _SPRA_POS 0x7028c 2911 #define _SPRA_SIZE 0x70290 2912 #define _SPRA_KEYVAL 0x70294 2913 #define _SPRA_KEYMSK 0x70298 2914 #define _SPRA_SURF 0x7029c 2915 #define _SPRA_KEYMAX 0x702a0 2916 #define _SPRA_TILEOFF 0x702a4 2917 #define _SPRA_OFFSET 0x702a4 2918 #define _SPRA_SURFLIVE 0x702ac 2919 #define _SPRA_SCALE 0x70304 2920 #define SPRITE_SCALE_ENABLE (1UL<<31) 2921 #define SPRITE_FILTER_MASK (3<<29) 2922 #define SPRITE_FILTER_MEDIUM (0<<29) 2923 #define SPRITE_FILTER_ENHANCING (1<<29) 2924 #define SPRITE_FILTER_SOFTENING (2<<29) 2925 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 2926 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) 2927 #define _SPRA_GAMC 0x70400 2928 2929 #define _SPRB_CTL 0x71280 2930 #define _SPRB_LINOFF 0x71284 2931 #define _SPRB_STRIDE 0x71288 2932 #define _SPRB_POS 0x7128c 2933 #define _SPRB_SIZE 0x71290 2934 #define _SPRB_KEYVAL 0x71294 2935 #define _SPRB_KEYMSK 0x71298 2936 #define _SPRB_SURF 0x7129c 2937 #define _SPRB_KEYMAX 0x712a0 2938 #define _SPRB_TILEOFF 0x712a4 2939 #define _SPRB_OFFSET 0x712a4 2940 #define _SPRB_SURFLIVE 0x712ac 2941 #define _SPRB_SCALE 0x71304 2942 #define _SPRB_GAMC 0x71400 2943 2944 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 2945 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 2946 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 2947 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS) 2948 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 2949 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 2950 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 2951 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 2952 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 2953 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 2954 #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 2955 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 2956 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) 2957 #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 2958 2959 /* VBIOS regs */ 2960 #define VGACNTRL 0x71400 2961 # define VGA_DISP_DISABLE (1UL << 31) 2962 # define VGA_2X_MODE (1 << 30) 2963 # define VGA_PIPE_B_SELECT (1 << 29) 2964 2965 /* Ironlake */ 2966 2967 #define CPU_VGACNTRL 0x41000 2968 #define CPU_VGA_DISABLE (1UL<<31) 2969 2970 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 2971 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 2972 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) 2973 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) 2974 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) 2975 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) 2976 #define DIGITAL_PORTA_NO_DETECT (0 << 0) 2977 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) 2978 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) 2979 2980 /* refresh rate hardware control */ 2981 #define RR_HW_CTL 0x45300 2982 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 2983 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 2984 2985 #define FDI_PLL_BIOS_0 0x46000 2986 #define FDI_PLL_FB_CLOCK_MASK 0xff 2987 #define FDI_PLL_BIOS_1 0x46004 2988 #define FDI_PLL_BIOS_2 0x46008 2989 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c 2990 #define DISPLAY_PORT_PLL_BIOS_1 0x46010 2991 #define DISPLAY_PORT_PLL_BIOS_2 0x46014 2992 2993 #define PCH_3DCGDIS0 0x46020 2994 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 2995 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 2996 2997 #define PCH_3DCGDIS1 0x46024 2998 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 2999 3000 #define FDI_PLL_FREQ_CTL 0x46030 3001 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 3002 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 3003 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 3004 3005 #define _PIPEA_DATA_M1 0x60030 3006 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 3007 #define TU_SIZE_MASK 0x7e000000 3008 3009 #define DATA_LINK_M_N_MASK (0xffffff) 3010 #define DATA_LINK_N_MAX (0x800000) 3011 3012 #define PIPE_DATA_M1_OFFSET 0 3013 #define _PIPEA_DATA_N1 0x60034 3014 #define PIPE_DATA_N1_OFFSET 0 3015 3016 #define _PIPEA_DATA_M2 0x60038 3017 #define PIPE_DATA_M2_OFFSET 0 3018 #define _PIPEA_DATA_N2 0x6003c 3019 #define PIPE_DATA_N2_OFFSET 0 3020 3021 #define _PIPEA_LINK_M1 0x60040 3022 #define PIPE_LINK_M1_OFFSET 0 3023 #define _PIPEA_LINK_N1 0x60044 3024 #define PIPE_LINK_N1_OFFSET 0 3025 3026 #define _PIPEA_LINK_M2 0x60048 3027 #define PIPE_LINK_M2_OFFSET 0 3028 #define _PIPEA_LINK_N2 0x6004c 3029 #define PIPE_LINK_N2_OFFSET 0 3030 3031 /* PIPEB timing regs are same start from 0x61000 */ 3032 3033 #define _PIPEB_DATA_M1 0x61030 3034 #define _PIPEB_DATA_N1 0x61034 3035 3036 #define _PIPEB_DATA_M2 0x61038 3037 #define _PIPEB_DATA_N2 0x6103c 3038 3039 #define _PIPEB_LINK_M1 0x61040 3040 #define _PIPEB_LINK_N1 0x61044 3041 3042 #define _PIPEB_LINK_M2 0x61048 3043 #define _PIPEB_LINK_N2 0x6104c 3044 3045 #define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1) 3046 #define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1) 3047 #define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2) 3048 #define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2) 3049 #define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1) 3050 #define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1) 3051 #define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2) 3052 #define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2) 3053 3054 /* CPU panel fitter */ 3055 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 3056 #define _PFA_CTL_1 0x68080 3057 #define _PFB_CTL_1 0x68880 3058 #define PF_ENABLE (1UL<<31) 3059 #define PF_PIPE_SEL_MASK_IVB (3<<29) 3060 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29) 3061 #define PF_FILTER_MASK (3<<23) 3062 #define PF_FILTER_PROGRAMMED (0<<23) 3063 #define PF_FILTER_MED_3x3 (1<<23) 3064 #define PF_FILTER_EDGE_ENHANCE (2<<23) 3065 #define PF_FILTER_EDGE_SOFTEN (3<<23) 3066 #define _PFA_WIN_SZ 0x68074 3067 #define _PFB_WIN_SZ 0x68874 3068 #define _PFA_WIN_POS 0x68070 3069 #define _PFB_WIN_POS 0x68870 3070 #define _PFA_VSCALE 0x68084 3071 #define _PFB_VSCALE 0x68884 3072 #define _PFA_HSCALE 0x68090 3073 #define _PFB_HSCALE 0x68890 3074 3075 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 3076 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 3077 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 3078 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 3079 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 3080 3081 /* legacy palette */ 3082 #define _LGC_PALETTE_A 0x4a000 3083 #define _LGC_PALETTE_B 0x4a800 3084 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) 3085 3086 /* interrupts */ 3087 #define DE_MASTER_IRQ_CONTROL (1UL << 31) 3088 #define DE_SPRITEB_FLIP_DONE (1 << 29) 3089 #define DE_SPRITEA_FLIP_DONE (1 << 28) 3090 #define DE_PLANEB_FLIP_DONE (1 << 27) 3091 #define DE_PLANEA_FLIP_DONE (1 << 26) 3092 #define DE_PCU_EVENT (1 << 25) 3093 #define DE_GTT_FAULT (1 << 24) 3094 #define DE_POISON (1 << 23) 3095 #define DE_PERFORM_COUNTER (1 << 22) 3096 #define DE_PCH_EVENT (1 << 21) 3097 #define DE_AUX_CHANNEL_A (1 << 20) 3098 #define DE_DP_A_HOTPLUG (1 << 19) 3099 #define DE_GSE (1 << 18) 3100 #define DE_PIPEB_VBLANK (1 << 15) 3101 #define DE_PIPEB_EVEN_FIELD (1 << 14) 3102 #define DE_PIPEB_ODD_FIELD (1 << 13) 3103 #define DE_PIPEB_LINE_COMPARE (1 << 12) 3104 #define DE_PIPEB_VSYNC (1 << 11) 3105 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 3106 #define DE_PIPEA_VBLANK (1 << 7) 3107 #define DE_PIPEA_EVEN_FIELD (1 << 6) 3108 #define DE_PIPEA_ODD_FIELD (1 << 5) 3109 #define DE_PIPEA_LINE_COMPARE (1 << 4) 3110 #define DE_PIPEA_VSYNC (1 << 3) 3111 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 3112 3113 /* More Ivybridge lolz */ 3114 #define DE_ERR_DEBUG_IVB (1<<30) 3115 #define DE_GSE_IVB (1<<29) 3116 #define DE_PCH_EVENT_IVB (1<<28) 3117 #define DE_DP_A_HOTPLUG_IVB (1<<27) 3118 #define DE_AUX_CHANNEL_A_IVB (1<<26) 3119 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) 3120 #define DE_PLANEC_FLIP_DONE_IVB (1<<13) 3121 #define DE_PIPEC_VBLANK_IVB (1<<10) 3122 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) 3123 #define DE_PLANEB_FLIP_DONE_IVB (1<<8) 3124 #define DE_PIPEB_VBLANK_IVB (1<<5) 3125 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) 3126 #define DE_PLANEA_FLIP_DONE_IVB (1<<3) 3127 #define DE_PIPEA_VBLANK_IVB (1<<0) 3128 3129 #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ 3130 #define MASTER_INTERRUPT_ENABLE (1UL<<31) 3131 3132 #define DEISR 0x44000 3133 #define DEIMR 0x44004 3134 #define DEIIR 0x44008 3135 #define DEIER 0x4400c 3136 3137 /* GT interrupt. 3138 * Note that for gen6+ the ring-specific interrupt bits do alias with the 3139 * corresponding bits in the per-ring interrupt control registers. */ 3140 #define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 3141 #define GT_GEN6_BLT_CS_ERROR_INTERRUPT (1 << 25) 3142 #define GT_GEN6_BLT_USER_INTERRUPT (1 << 22) 3143 #define GT_GEN6_BSD_CS_ERROR_INTERRUPT (1 << 15) 3144 #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) 3145 #define GT_BSD_USER_INTERRUPT (1 << 5) /* ilk only */ 3146 #define GT_GEN7_L3_PARITY_ERROR_INTERRUPT (1 << 5) 3147 #define GT_PIPE_NOTIFY (1 << 4) 3148 #define GT_RENDER_CS_ERROR_INTERRUPT (1 << 3) 3149 #define GT_SYNC_STATUS (1 << 2) 3150 #define GT_USER_INTERRUPT (1 << 0) 3151 3152 #define GTISR 0x44010 3153 #define GTIMR 0x44014 3154 #define GTIIR 0x44018 3155 #define GTIER 0x4401c 3156 3157 #define ILK_DISPLAY_CHICKEN2 0x42004 3158 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 3159 #define ILK_ELPIN_409_SELECT (1 << 25) 3160 #define ILK_DPARB_GATE (1<<22) 3161 #define ILK_VSDPFD_FULL (1<<21) 3162 #define ILK_DISPLAY_CHICKEN_FUSES 0x42014 3163 #define ILK_INTERNAL_GRAPHICS_DISABLE (1UL<<31) 3164 #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30) 3165 #define ILK_DISPLAY_DEBUG_DISABLE (1<<29) 3166 #define ILK_HDCP_DISABLE (1<<25) 3167 #define ILK_eDP_A_DISABLE (1<<24) 3168 #define ILK_DESKTOP (1<<23) 3169 3170 #define ILK_DSPCLK_GATE_D 0x42020 3171 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 3172 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 3173 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 3174 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 3175 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 3176 3177 #define IVB_CHICKEN3 0x4200c 3178 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 3179 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 3180 3181 #define DISP_ARB_CTL 0x45000 3182 #define DISP_TILE_SURFACE_SWIZZLING (1<<13) 3183 #define DISP_FBC_WM_DIS (1<<15) 3184 3185 /* GEN7 chicken */ 3186 #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 3187 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) 3188 3189 #define GEN7_L3CNTLREG1 0xB01C 3190 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C 3191 #define GEN7_L3AGDIS (1<<19) 3192 3193 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 3194 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 3195 3196 #define GEN7_L3SQCREG4 0xb034 3197 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) 3198 3199 /* WaCatErrorRejectionIssue */ 3200 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 3201 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) 3202 3203 #define HSW_FUSE_STRAP 0x42014 3204 #define HSW_CDCLK_LIMIT (1 << 24) 3205 3206 /* PCH */ 3207 3208 /* south display engine interrupt: IBX */ 3209 #define SDE_AUDIO_POWER_D (1 << 27) 3210 #define SDE_AUDIO_POWER_C (1 << 26) 3211 #define SDE_AUDIO_POWER_B (1 << 25) 3212 #define SDE_AUDIO_POWER_SHIFT (25) 3213 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 3214 #define SDE_GMBUS (1 << 24) 3215 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 3216 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 3217 #define SDE_AUDIO_HDCP_MASK (3 << 22) 3218 #define SDE_AUDIO_TRANSB (1 << 21) 3219 #define SDE_AUDIO_TRANSA (1 << 20) 3220 #define SDE_AUDIO_TRANS_MASK (3 << 20) 3221 #define SDE_POISON (1 << 19) 3222 /* 18 reserved */ 3223 #define SDE_FDI_RXB (1 << 17) 3224 #define SDE_FDI_RXA (1 << 16) 3225 #define SDE_FDI_MASK (3 << 16) 3226 #define SDE_AUXD (1 << 15) 3227 #define SDE_AUXC (1 << 14) 3228 #define SDE_AUXB (1 << 13) 3229 #define SDE_AUX_MASK (7 << 13) 3230 /* 12 reserved */ 3231 #define SDE_CRT_HOTPLUG (1 << 11) 3232 #define SDE_PORTD_HOTPLUG (1 << 10) 3233 #define SDE_PORTC_HOTPLUG (1 << 9) 3234 #define SDE_PORTB_HOTPLUG (1 << 8) 3235 #define SDE_SDVOB_HOTPLUG (1 << 6) 3236 #define SDE_HOTPLUG_MASK (0xf << 8) 3237 #define SDE_TRANSB_CRC_DONE (1 << 5) 3238 #define SDE_TRANSB_CRC_ERR (1 << 4) 3239 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 3240 #define SDE_TRANSA_CRC_DONE (1 << 2) 3241 #define SDE_TRANSA_CRC_ERR (1 << 1) 3242 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 3243 #define SDE_TRANS_MASK (0x3f) 3244 3245 /* south display engine interrupt: CPT/PPT */ 3246 #define SDE_AUDIO_POWER_D_CPT (1UL << 31) 3247 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 3248 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 3249 #define SDE_AUDIO_POWER_SHIFT_CPT 29 3250 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 3251 #define SDE_AUXD_CPT (1 << 27) 3252 #define SDE_AUXC_CPT (1 << 26) 3253 #define SDE_AUXB_CPT (1 << 25) 3254 #define SDE_AUX_MASK_CPT (7 << 25) 3255 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 3256 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 3257 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 3258 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 3259 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 3260 SDE_PORTD_HOTPLUG_CPT | \ 3261 SDE_PORTC_HOTPLUG_CPT | \ 3262 SDE_PORTB_HOTPLUG_CPT) 3263 #define SDE_GMBUS_CPT (1 << 17) 3264 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 3265 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 3266 #define SDE_FDI_RXC_CPT (1 << 8) 3267 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 3268 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 3269 #define SDE_FDI_RXB_CPT (1 << 4) 3270 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 3271 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 3272 #define SDE_FDI_RXA_CPT (1 << 0) 3273 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 3274 SDE_AUDIO_CP_REQ_B_CPT | \ 3275 SDE_AUDIO_CP_REQ_A_CPT) 3276 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 3277 SDE_AUDIO_CP_CHG_B_CPT | \ 3278 SDE_AUDIO_CP_CHG_A_CPT) 3279 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 3280 SDE_FDI_RXB_CPT | \ 3281 SDE_FDI_RXA_CPT) 3282 3283 #define SDEISR 0xc4000 3284 #define SDEIMR 0xc4004 3285 #define SDEIIR 0xc4008 3286 #define SDEIER 0xc400c 3287 3288 /* digital port hotplug */ 3289 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ 3290 #define PORTD_HOTPLUG_ENABLE (1 << 20) 3291 #define PORTD_PULSE_DURATION_2ms (0) 3292 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) 3293 #define PORTD_PULSE_DURATION_6ms (2 << 18) 3294 #define PORTD_PULSE_DURATION_100ms (3 << 18) 3295 #define PORTD_PULSE_DURATION_MASK (3 << 18) 3296 #define PORTD_HOTPLUG_NO_DETECT (0) 3297 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 3298 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17) 3299 #define PORTC_HOTPLUG_ENABLE (1 << 12) 3300 #define PORTC_PULSE_DURATION_2ms (0) 3301 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) 3302 #define PORTC_PULSE_DURATION_6ms (2 << 10) 3303 #define PORTC_PULSE_DURATION_100ms (3 << 10) 3304 #define PORTC_PULSE_DURATION_MASK (3 << 10) 3305 #define PORTC_HOTPLUG_NO_DETECT (0) 3306 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 3307 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9) 3308 #define PORTB_HOTPLUG_ENABLE (1 << 4) 3309 #define PORTB_PULSE_DURATION_2ms (0) 3310 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) 3311 #define PORTB_PULSE_DURATION_6ms (2 << 2) 3312 #define PORTB_PULSE_DURATION_100ms (3 << 2) 3313 #define PORTB_PULSE_DURATION_MASK (3 << 2) 3314 #define PORTB_HOTPLUG_NO_DETECT (0) 3315 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 3316 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1) 3317 3318 #define PCH_GPIOA 0xc5010 3319 #define PCH_GPIOB 0xc5014 3320 #define PCH_GPIOC 0xc5018 3321 #define PCH_GPIOD 0xc501c 3322 #define PCH_GPIOE 0xc5020 3323 #define PCH_GPIOF 0xc5024 3324 3325 #define PCH_GMBUS0 0xc5100 3326 #define PCH_GMBUS1 0xc5104 3327 #define PCH_GMBUS2 0xc5108 3328 #define PCH_GMBUS3 0xc510c 3329 #define PCH_GMBUS4 0xc5110 3330 #define PCH_GMBUS5 0xc5120 3331 3332 #define _PCH_DPLL_A 0xc6014 3333 #define _PCH_DPLL_B 0xc6018 3334 #define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 3335 3336 #define _PCH_FPA0 0xc6040 3337 #define FP_CB_TUNE (0x3<<22) 3338 #define _PCH_FPA1 0xc6044 3339 #define _PCH_FPB0 0xc6048 3340 #define _PCH_FPB1 0xc604c 3341 #define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) 3342 #define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) 3343 3344 #define PCH_DPLL_TEST 0xc606c 3345 3346 #define PCH_DREF_CONTROL 0xC6200 3347 #define DREF_CONTROL_MASK 0x7fc3 3348 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 3349 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 3350 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 3351 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 3352 #define DREF_SSC_SOURCE_DISABLE (0<<11) 3353 #define DREF_SSC_SOURCE_ENABLE (2<<11) 3354 #define DREF_SSC_SOURCE_MASK (3<<11) 3355 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 3356 #define DREF_NONSPREAD_CK505_ENABLE (1<<9) 3357 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 3358 #define DREF_NONSPREAD_SOURCE_MASK (3<<9) 3359 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 3360 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 3361 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) 3362 #define DREF_SSC4_DOWNSPREAD (0<<6) 3363 #define DREF_SSC4_CENTERSPREAD (1<<6) 3364 #define DREF_SSC1_DISABLE (0<<1) 3365 #define DREF_SSC1_ENABLE (1<<1) 3366 #define DREF_SSC4_DISABLE (0) 3367 #define DREF_SSC4_ENABLE (1) 3368 3369 #define PCH_RAWCLK_FREQ 0xc6204 3370 #define FDL_TP1_TIMER_SHIFT 12 3371 #define FDL_TP1_TIMER_MASK (3<<12) 3372 #define FDL_TP2_TIMER_SHIFT 10 3373 #define FDL_TP2_TIMER_MASK (3<<10) 3374 #define RAWCLK_FREQ_MASK 0x3ff 3375 3376 #define PCH_DPLL_TMR_CFG 0xc6208 3377 3378 #define PCH_SSC4_PARMS 0xc6210 3379 #define PCH_SSC4_AUX_PARMS 0xc6214 3380 3381 #define PCH_DPLL_SEL 0xc7000 3382 #define TRANSA_DPLL_ENABLE (1<<3) 3383 #define TRANSA_DPLLB_SEL (1<<0) 3384 #define TRANSA_DPLLA_SEL 0 3385 #define TRANSB_DPLL_ENABLE (1<<7) 3386 #define TRANSB_DPLLB_SEL (1<<4) 3387 #define TRANSB_DPLLA_SEL (0) 3388 #define TRANSC_DPLL_ENABLE (1<<11) 3389 #define TRANSC_DPLLB_SEL (1<<8) 3390 #define TRANSC_DPLLA_SEL (0) 3391 3392 /* transcoder */ 3393 3394 #define _TRANS_HTOTAL_A 0xe0000 3395 #define TRANS_HTOTAL_SHIFT 16 3396 #define TRANS_HACTIVE_SHIFT 0 3397 #define _TRANS_HBLANK_A 0xe0004 3398 #define TRANS_HBLANK_END_SHIFT 16 3399 #define TRANS_HBLANK_START_SHIFT 0 3400 #define _TRANS_HSYNC_A 0xe0008 3401 #define TRANS_HSYNC_END_SHIFT 16 3402 #define TRANS_HSYNC_START_SHIFT 0 3403 #define _TRANS_VTOTAL_A 0xe000c 3404 #define TRANS_VTOTAL_SHIFT 16 3405 #define TRANS_VACTIVE_SHIFT 0 3406 #define _TRANS_VBLANK_A 0xe0010 3407 #define TRANS_VBLANK_END_SHIFT 16 3408 #define TRANS_VBLANK_START_SHIFT 0 3409 #define _TRANS_VSYNC_A 0xe0014 3410 #define TRANS_VSYNC_END_SHIFT 16 3411 #define TRANS_VSYNC_START_SHIFT 0 3412 #define _TRANS_VSYNCSHIFT_A 0xe0028 3413 3414 #define _TRANSA_DATA_M1 0xe0030 3415 #define _TRANSA_DATA_N1 0xe0034 3416 #define _TRANSA_DATA_M2 0xe0038 3417 #define _TRANSA_DATA_N2 0xe003c 3418 #define _TRANSA_DP_LINK_M1 0xe0040 3419 #define _TRANSA_DP_LINK_N1 0xe0044 3420 #define _TRANSA_DP_LINK_M2 0xe0048 3421 #define _TRANSA_DP_LINK_N2 0xe004c 3422 3423 /* Per-transcoder DIP controls */ 3424 3425 #define _VIDEO_DIP_CTL_A 0xe0200 3426 #define _VIDEO_DIP_DATA_A 0xe0208 3427 #define _VIDEO_DIP_GCP_A 0xe0210 3428 3429 #define _VIDEO_DIP_CTL_B 0xe1200 3430 #define _VIDEO_DIP_DATA_B 0xe1208 3431 #define _VIDEO_DIP_GCP_B 0xe1210 3432 3433 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 3434 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 3435 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 3436 3437 #define VLV_VIDEO_DIP_CTL_A 0x60200 3438 #define VLV_VIDEO_DIP_DATA_A 0x60208 3439 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210 3440 3441 #define VLV_VIDEO_DIP_CTL_B 0x61170 3442 #define VLV_VIDEO_DIP_DATA_B 0x61174 3443 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178 3444 3445 #define VLV_TVIDEO_DIP_CTL(pipe) \ 3446 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B) 3447 #define VLV_TVIDEO_DIP_DATA(pipe) \ 3448 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B) 3449 #define VLV_TVIDEO_DIP_GCP(pipe) \ 3450 _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B) 3451 3452 /* Haswell DIP controls */ 3453 #define HSW_VIDEO_DIP_CTL_A 0x60200 3454 #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220 3455 #define HSW_VIDEO_DIP_VS_DATA_A 0x60260 3456 #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 3457 #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 3458 #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320 3459 #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240 3460 #define HSW_VIDEO_DIP_VS_ECC_A 0x60280 3461 #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 3462 #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300 3463 #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344 3464 #define HSW_VIDEO_DIP_GCP_A 0x60210 3465 3466 #define HSW_VIDEO_DIP_CTL_B 0x61200 3467 #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220 3468 #define HSW_VIDEO_DIP_VS_DATA_B 0x61260 3469 #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 3470 #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 3471 #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320 3472 #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240 3473 #define HSW_VIDEO_DIP_VS_ECC_B 0x61280 3474 #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 3475 #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300 3476 #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 3477 #define HSW_VIDEO_DIP_GCP_B 0x61210 3478 3479 #define HSW_TVIDEO_DIP_CTL(pipe) \ 3480 _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B) 3481 #define HSW_TVIDEO_DIP_AVI_DATA(pipe) \ 3482 _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B) 3483 #define HSW_TVIDEO_DIP_SPD_DATA(pipe) \ 3484 _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B) 3485 #define HSW_TVIDEO_DIP_GCP(pipe) \ 3486 _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B) 3487 3488 #define _TRANS_HTOTAL_B 0xe1000 3489 #define _TRANS_HBLANK_B 0xe1004 3490 #define _TRANS_HSYNC_B 0xe1008 3491 #define _TRANS_VTOTAL_B 0xe100c 3492 #define _TRANS_VBLANK_B 0xe1010 3493 #define _TRANS_VSYNC_B 0xe1014 3494 #define _TRANS_VSYNCSHIFT_B 0xe1028 3495 3496 #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B) 3497 #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B) 3498 #define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B) 3499 #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B) 3500 #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B) 3501 #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B) 3502 #define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \ 3503 _TRANS_VSYNCSHIFT_B) 3504 3505 #define _TRANSB_DATA_M1 0xe1030 3506 #define _TRANSB_DATA_N1 0xe1034 3507 #define _TRANSB_DATA_M2 0xe1038 3508 #define _TRANSB_DATA_N2 0xe103c 3509 #define _TRANSB_DP_LINK_M1 0xe1040 3510 #define _TRANSB_DP_LINK_N1 0xe1044 3511 #define _TRANSB_DP_LINK_M2 0xe1048 3512 #define _TRANSB_DP_LINK_N2 0xe104c 3513 3514 #define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1) 3515 #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1) 3516 #define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2) 3517 #define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2) 3518 #define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1) 3519 #define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1) 3520 #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2) 3521 #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2) 3522 3523 #define _TRANSACONF 0xf0008 3524 #define _TRANSBCONF 0xf1008 3525 #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF) 3526 #define _PCH_TRANSACONF 0xf0008 3527 #define _PCH_TRANSBCONF 0xf1008 3528 #define PCH_TRANSCONF(plane) _PIPE(plane, _PCH_TRANSACONF, _PCH_TRANSBCONF) 3529 #define TRANS_DISABLE (0UL<<31) 3530 #define TRANS_ENABLE (1UL<<31) 3531 #define TRANS_STATE_MASK (1<<30) 3532 #define TRANS_STATE_DISABLE (0<<30) 3533 #define TRANS_STATE_ENABLE (1<<30) 3534 #define TRANS_FSYNC_DELAY_HB1 (0<<27) 3535 #define TRANS_FSYNC_DELAY_HB2 (1<<27) 3536 #define TRANS_FSYNC_DELAY_HB3 (2<<27) 3537 #define TRANS_FSYNC_DELAY_HB4 (3<<27) 3538 #define TRANS_DP_AUDIO_ONLY (1<<26) 3539 #define TRANS_DP_VIDEO_AUDIO (0<<26) 3540 #define TRANS_INTERLACE_MASK (7<<21) 3541 #define TRANS_PROGRESSIVE (0<<21) 3542 #define TRANS_INTERLACED (3<<21) 3543 #define TRANS_LEGACY_INTERLACED_ILK (2<<21) 3544 #define TRANS_8BPC (0<<5) 3545 #define TRANS_10BPC (1<<5) 3546 #define TRANS_6BPC (2<<5) 3547 #define TRANS_12BPC (3<<5) 3548 3549 #define _TRANSA_CHICKEN1 0xf0060 3550 #define _TRANSB_CHICKEN1 0xf1060 3551 #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 3552 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) 3553 #define _TRANSA_CHICKEN2 0xf0064 3554 #define _TRANSB_CHICKEN2 0xf1064 3555 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 3556 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1UL<<31) 3557 3558 #define SOUTH_CHICKEN1 0xc2000 3559 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 3560 #define FDIA_PHASE_SYNC_SHIFT_EN 18 3561 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 3562 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 3563 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 3564 #define SOUTH_CHICKEN2 0xc2004 3565 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) 3566 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) 3567 #define LPT_PWM_GRANULARITY (1<<5) 3568 #define DPLS_EDP_PPS_FIX_DIS (1<<0) 3569 3570 #define _FDI_RXA_CHICKEN 0xc200c 3571 #define _FDI_RXB_CHICKEN 0xc2010 3572 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) 3573 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) 3574 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 3575 3576 #define SOUTH_DSPCLK_GATE_D 0xc2020 3577 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 3578 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) 3579 3580 /* CPU: FDI_TX */ 3581 #define _FDI_TXA_CTL 0x60100 3582 #define _FDI_TXB_CTL 0x61100 3583 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 3584 #define FDI_TX_DISABLE (0UL<<31) 3585 #define FDI_TX_ENABLE (1UL<<31) 3586 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 3587 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 3588 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 3589 #define FDI_LINK_TRAIN_NONE (3<<28) 3590 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 3591 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 3592 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 3593 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 3594 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 3595 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 3596 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 3597 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 3598 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 3599 SNB has different settings. */ 3600 /* SNB A-stepping */ 3601 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 3602 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 3603 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 3604 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 3605 /* SNB B-stepping */ 3606 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 3607 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 3608 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 3609 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 3610 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) 3611 #define FDI_DP_PORT_WIDTH_X1 (0<<19) 3612 #define FDI_DP_PORT_WIDTH_X2 (1<<19) 3613 #define FDI_DP_PORT_WIDTH_X3 (2<<19) 3614 #define FDI_DP_PORT_WIDTH_X4 (3<<19) 3615 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 3616 /* Ironlake: hardwired to 1 */ 3617 #define FDI_TX_PLL_ENABLE (1<<14) 3618 3619 /* Ivybridge has different bits for lolz */ 3620 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) 3621 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) 3622 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) 3623 #define FDI_LINK_TRAIN_NONE_IVB (3<<8) 3624 3625 /* both Tx and Rx */ 3626 #define FDI_COMPOSITE_SYNC (1<<11) 3627 #define FDI_LINK_TRAIN_AUTO (1<<10) 3628 #define FDI_SCRAMBLING_ENABLE (0<<7) 3629 #define FDI_SCRAMBLING_DISABLE (1<<7) 3630 3631 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 3632 #define _FDI_RXA_CTL 0xf000c 3633 #define _FDI_RXB_CTL 0xf100c 3634 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 3635 #define FDI_RX_ENABLE (1UL<<31) 3636 /* train, dp width same as FDI_TX */ 3637 #define FDI_FS_ERRC_ENABLE (1<<27) 3638 #define FDI_FE_ERRC_ENABLE (1<<26) 3639 #define FDI_DP_PORT_WIDTH_X8 (7<<19) 3640 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16) 3641 #define FDI_8BPC (0<<16) 3642 #define FDI_10BPC (1<<16) 3643 #define FDI_6BPC (2<<16) 3644 #define FDI_12BPC (3<<16) 3645 #define FDI_LINK_REVERSE_OVERWRITE (1<<15) 3646 #define FDI_DMI_LINK_REVERSE_MASK (1<<14) 3647 #define FDI_RX_PLL_ENABLE (1<<13) 3648 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 3649 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 3650 #define FDI_FS_ERR_REPORT_ENABLE (1<<9) 3651 #define FDI_FE_ERR_REPORT_ENABLE (1<<8) 3652 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 3653 #define FDI_PCDCLK (1<<4) 3654 /* CPT */ 3655 #define FDI_AUTO_TRAINING (1<<10) 3656 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 3657 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) 3658 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) 3659 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 3660 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 3661 /* LPT */ 3662 #define FDI_PORT_WIDTH_2X_LPT (1<<19) 3663 #define FDI_PORT_WIDTH_1X_LPT (0<<19) 3664 3665 #define _FDI_RXA_MISC 0xf0010 3666 #define _FDI_RXB_MISC 0xf1010 3667 #define FDI_RX_PWRDN_LANE1_MASK (3<<26) 3668 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) 3669 #define FDI_RX_PWRDN_LANE0_MASK (3<<24) 3670 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) 3671 #define FDI_RX_TP1_TO_TP2_48 (2<<20) 3672 #define FDI_RX_TP1_TO_TP2_64 (3<<20) 3673 #define FDI_RX_FDI_DELAY_90 (0x90<<0) 3674 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 3675 3676 #define _FDI_RXA_TUSIZE1 0xf0030 3677 #define _FDI_RXA_TUSIZE2 0xf0038 3678 #define _FDI_RXB_TUSIZE1 0xf1030 3679 #define _FDI_RXB_TUSIZE2 0xf1038 3680 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 3681 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 3682 3683 /* FDI_RX interrupt register format */ 3684 #define FDI_RX_INTER_LANE_ALIGN (1<<10) 3685 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 3686 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 3687 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 3688 #define FDI_RX_FS_CODE_ERR (1<<6) 3689 #define FDI_RX_FE_CODE_ERR (1<<5) 3690 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 3691 #define FDI_RX_HDCP_LINK_FAIL (1<<3) 3692 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 3693 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 3694 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 3695 3696 #define _FDI_RXA_IIR 0xf0014 3697 #define _FDI_RXA_IMR 0xf0018 3698 #define _FDI_RXB_IIR 0xf1014 3699 #define _FDI_RXB_IMR 0xf1018 3700 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 3701 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 3702 3703 #define FDI_PLL_CTL_1 0xfe000 3704 #define FDI_PLL_CTL_2 0xfe004 3705 3706 /* or SDVOB */ 3707 #define HDMIB 0xe1140 3708 #define PORT_ENABLE (1UL << 31) 3709 #define TRANSCODER(pipe) ((pipe) << 30) 3710 #define TRANSCODER_CPT(pipe) ((pipe) << 29) 3711 #define TRANSCODER_MASK (1 << 30) 3712 #define TRANSCODER_MASK_CPT (3 << 29) 3713 #define COLOR_FORMAT_8bpc (0) 3714 #define COLOR_FORMAT_12bpc (3 << 26) 3715 #define SDVOB_HOTPLUG_ENABLE (1 << 23) 3716 #define SDVO_ENCODING (0) 3717 #define TMDS_ENCODING (2 << 10) 3718 #define NULL_PACKET_VSYNC_ENABLE (1 << 9) 3719 /* CPT */ 3720 #define HDMI_MODE_SELECT (1 << 9) 3721 #define DVI_MODE_SELECT (0) 3722 #define SDVOB_BORDER_ENABLE (1 << 7) 3723 #define AUDIO_ENABLE (1 << 6) 3724 #define VSYNC_ACTIVE_HIGH (1 << 4) 3725 #define HSYNC_ACTIVE_HIGH (1 << 3) 3726 #define PORT_DETECTED (1 << 2) 3727 3728 /* PCH SDVOB multiplex with HDMIB */ 3729 #define PCH_SDVOB HDMIB 3730 3731 #define HDMIC 0xe1150 3732 #define HDMID 0xe1160 3733 3734 #define PCH_LVDS 0xe1180 3735 #define LVDS_DETECTED (1 << 1) 3736 #define LVDS_BORDER_ENABLE (1 << 15) 3737 #define LVDS_PORT_ENABLE (1UL << 31) 3738 #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) 3739 #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) 3740 #define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) 3741 3742 /* vlv has 2 sets of panel control regs. */ 3743 #define PIPEA_PP_STATUS 0x61200 3744 #define PIPEA_PP_CONTROL 0x61204 3745 #define PIPEA_PP_ON_DELAYS 0x61208 3746 #define PIPEA_PP_OFF_DELAYS 0x6120c 3747 #define PIPEA_PP_DIVISOR 0x61210 3748 3749 #define PIPEB_PP_STATUS 0x61300 3750 #define PIPEB_PP_CONTROL 0x61304 3751 #define PIPEB_PP_ON_DELAYS 0x61308 3752 #define PIPEB_PP_OFF_DELAYS 0x6130c 3753 #define PIPEB_PP_DIVISOR 0x61310 3754 3755 #define PCH_PP_STATUS 0xc7200 3756 #define PANEL_POWER_CYCLE_ACTIVE (1 << 27) 3757 3758 #define PCH_PP_CONTROL 0xc7204 3759 #define PANEL_UNLOCK_REGS (0xabcd << 16) 3760 #define PANEL_UNLOCK_MASK (0xffff << 16) 3761 #define EDP_FORCE_VDD (1 << 3) 3762 #define EDP_BLC_ENABLE (1 << 2) 3763 #define PANEL_POWER_RESET (1 << 1) 3764 #define PANEL_POWER_OFF (0 << 0) 3765 #define PANEL_POWER_ON (1 << 0) 3766 #define PCH_PP_ON_DELAYS 0xc7208 3767 #define PANEL_PORT_SELECT_MASK (3 << 30) 3768 #define PANEL_PORT_SELECT_LVDS (0 << 30) 3769 #define PANEL_PORT_SELECT_DPA (1 << 30) 3770 #define EDP_PANEL (1 << 30) 3771 #define PANEL_PORT_SELECT_DPC (2 << 30) 3772 #define PANEL_PORT_SELECT_DPD (3 << 30) 3773 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) 3774 #define PANEL_POWER_UP_DELAY_SHIFT 16 3775 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) 3776 #define PANEL_LIGHT_ON_DELAY_SHIFT 0 3777 3778 #define PCH_PP_OFF_DELAYS 0xc720c 3779 #define PANEL_POWER_PORT_SELECT_MASK (0x3 << 30) 3780 #define PANEL_POWER_PORT_LVDS (0 << 30) 3781 #define PANEL_POWER_PORT_DP_A (1 << 30) 3782 #define PANEL_POWER_PORT_DP_C (2 << 30) 3783 #define PANEL_POWER_PORT_DP_D (3 << 30) 3784 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) 3785 #define PANEL_POWER_DOWN_DELAY_SHIFT 16 3786 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) 3787 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 3788 3789 #define PCH_PP_DIVISOR 0xc7210 3790 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) 3791 #define PP_REFERENCE_DIVIDER_SHIFT 8 3792 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) 3793 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 3794 3795 #define PCH_DP_B 0xe4100 3796 #define PCH_DPB_AUX_CH_CTL 0xe4110 3797 #define PCH_DPB_AUX_CH_DATA1 0xe4114 3798 #define PCH_DPB_AUX_CH_DATA2 0xe4118 3799 #define PCH_DPB_AUX_CH_DATA3 0xe411c 3800 #define PCH_DPB_AUX_CH_DATA4 0xe4120 3801 #define PCH_DPB_AUX_CH_DATA5 0xe4124 3802 3803 #define PCH_DP_C 0xe4200 3804 #define PCH_DPC_AUX_CH_CTL 0xe4210 3805 #define PCH_DPC_AUX_CH_DATA1 0xe4214 3806 #define PCH_DPC_AUX_CH_DATA2 0xe4218 3807 #define PCH_DPC_AUX_CH_DATA3 0xe421c 3808 #define PCH_DPC_AUX_CH_DATA4 0xe4220 3809 #define PCH_DPC_AUX_CH_DATA5 0xe4224 3810 3811 #define PCH_DP_D 0xe4300 3812 #define PCH_DPD_AUX_CH_CTL 0xe4310 3813 #define PCH_DPD_AUX_CH_DATA1 0xe4314 3814 #define PCH_DPD_AUX_CH_DATA2 0xe4318 3815 #define PCH_DPD_AUX_CH_DATA3 0xe431c 3816 #define PCH_DPD_AUX_CH_DATA4 0xe4320 3817 #define PCH_DPD_AUX_CH_DATA5 0xe4324 3818 3819 /* CPT */ 3820 #define PORT_TRANS_A_SEL_CPT 0 3821 #define PORT_TRANS_B_SEL_CPT (1<<29) 3822 #define PORT_TRANS_C_SEL_CPT (2<<29) 3823 #define PORT_TRANS_SEL_MASK (3<<29) 3824 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) 3825 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) 3826 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) 3827 3828 #define TRANS_DP_CTL_A 0xe0300 3829 #define TRANS_DP_CTL_B 0xe1300 3830 #define TRANS_DP_CTL_C 0xe2300 3831 #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B) 3832 #define TRANS_DP_OUTPUT_ENABLE (1UL<<31) 3833 #define TRANS_DP_PORT_SEL_B (0<<29) 3834 #define TRANS_DP_PORT_SEL_C (1<<29) 3835 #define TRANS_DP_PORT_SEL_D (2<<29) 3836 #define TRANS_DP_PORT_SEL_NONE (3<<29) 3837 #define TRANS_DP_PORT_SEL_MASK (3<<29) 3838 #define TRANS_DP_AUDIO_ONLY (1<<26) 3839 #define TRANS_DP_ENH_FRAMING (1<<18) 3840 #define TRANS_DP_8BPC (0<<9) 3841 #define TRANS_DP_10BPC (1<<9) 3842 #define TRANS_DP_6BPC (2<<9) 3843 #define TRANS_DP_12BPC (3<<9) 3844 #define TRANS_DP_BPC_MASK (3<<9) 3845 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 3846 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 3847 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 3848 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 3849 #define TRANS_DP_SYNC_MASK (3<<3) 3850 3851 /* SNB eDP training params */ 3852 /* SNB A-stepping */ 3853 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 3854 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 3855 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 3856 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 3857 /* SNB B-stepping */ 3858 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) 3859 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) 3860 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) 3861 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) 3862 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) 3863 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) 3864 3865 /* IVB */ 3866 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) 3867 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) 3868 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) 3869 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) 3870 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) 3871 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) 3872 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 <<22) 3873 3874 /* legacy values */ 3875 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) 3876 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) 3877 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) 3878 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) 3879 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) 3880 3881 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) 3882 3883 #define FORCEWAKE 0xA18C 3884 #define FORCEWAKE_VLV 0x1300b0 3885 #define FORCEWAKE_ACK_VLV 0x1300b4 3886 #define FORCEWAKE_ACK_HSW 0x130044 3887 #define FORCEWAKE_ACK 0x130090 3888 #define FORCEWAKE_MT 0xa188 /* multi-threaded */ 3889 #define FORCEWAKE_KERNEL 0x1 3890 #define FORCEWAKE_USER 0x2 3891 #define FORCEWAKE_MT_ACK 0x130040 3892 #define ECOBUS 0xa180 3893 #define FORCEWAKE_MT_ENABLE (1<<5) 3894 3895 #define GTFIFODBG 0x120000 3896 #define GT_FIFO_CPU_ERROR_MASK 7 3897 #define GT_FIFO_OVFERR (1<<2) 3898 #define GT_FIFO_IAWRERR (1<<1) 3899 #define GT_FIFO_IARDERR (1<<0) 3900 3901 #define GT_FIFO_FREE_ENTRIES 0x120008 3902 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 3903 3904 #define GEN6_UCGCTL1 0x9400 3905 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 3906 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) 3907 3908 #define GEN6_UCGCTL2 0x9404 3909 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) 3910 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) 3911 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 3912 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 3913 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 3914 3915 #define GEN7_UCGCTL4 0x940c 3916 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) 3917 3918 #define GEN6_RPNSWREQ 0xA008 3919 #define GEN6_TURBO_DISABLE (1UL<<31) 3920 #define GEN6_FREQUENCY(x) ((x)<<25) 3921 #define GEN6_OFFSET(x) ((x)<<19) 3922 #define GEN6_AGGRESSIVE_TURBO (0<<15) 3923 #define GEN6_RC_VIDEO_FREQ 0xA00C 3924 #define GEN6_RC_CONTROL 0xA090 3925 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) 3926 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) 3927 #define GEN6_RC_CTL_RC6_ENABLE (1<<18) 3928 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) 3929 #define GEN6_RC_CTL_RC7_ENABLE (1<<22) 3930 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) 3931 #define GEN6_RC_CTL_HW_ENABLE (1UL<<31) 3932 #define GEN6_RP_DOWN_TIMEOUT 0xA010 3933 #define GEN6_RP_INTERRUPT_LIMITS 0xA014 3934 #define GEN6_RPSTAT1 0xA01C 3935 #define GEN6_CAGF_SHIFT 8 3936 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) 3937 #define GEN6_RP_CONTROL 0xA024 3938 #define GEN6_RP_MEDIA_TURBO (1<<11) 3939 #define GEN6_RP_MEDIA_MODE_MASK (3<<9) 3940 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) 3941 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) 3942 #define GEN6_RP_MEDIA_HW_MODE (1<<9) 3943 #define GEN6_RP_MEDIA_SW_MODE (0<<9) 3944 #define GEN6_RP_MEDIA_IS_GFX (1<<8) 3945 #define GEN6_RP_ENABLE (1<<7) 3946 #define GEN6_RP_UP_IDLE_MIN (0x1<<3) 3947 #define GEN6_RP_UP_BUSY_AVG (0x2<<3) 3948 #define GEN6_RP_UP_BUSY_CONT (0x4<<3) 3949 #define GEN7_RP_DOWN_IDLE_AVG (0x2<<0) 3950 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) 3951 #define GEN6_RP_UP_THRESHOLD 0xA02C 3952 #define GEN6_RP_DOWN_THRESHOLD 0xA030 3953 #define GEN6_RP_CUR_UP_EI 0xA050 3954 #define GEN6_CURICONT_MASK 0xffffff 3955 #define GEN6_RP_CUR_UP 0xA054 3956 #define GEN6_CURBSYTAVG_MASK 0xffffff 3957 #define GEN6_RP_PREV_UP 0xA058 3958 #define GEN6_RP_CUR_DOWN_EI 0xA05C 3959 #define GEN6_CURIAVG_MASK 0xffffff 3960 #define GEN6_RP_CUR_DOWN 0xA060 3961 #define GEN6_RP_PREV_DOWN 0xA064 3962 #define GEN6_RP_UP_EI 0xA068 3963 #define GEN6_RP_DOWN_EI 0xA06C 3964 #define GEN6_RP_IDLE_HYSTERSIS 0xA070 3965 #define GEN6_RC_STATE 0xA094 3966 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 3967 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C 3968 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 3969 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 3970 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC 3971 #define GEN6_RC_SLEEP 0xA0B0 3972 #define GEN6_RC1e_THRESHOLD 0xA0B4 3973 #define GEN6_RC6_THRESHOLD 0xA0B8 3974 #define GEN6_RC6p_THRESHOLD 0xA0BC 3975 #define GEN6_RC6pp_THRESHOLD 0xA0C0 3976 #define GEN6_PMINTRMSK 0xA168 3977 3978 #define GEN6_PMISR 0x44020 3979 #define GEN6_PMIMR 0x44024 /* rps_lock */ 3980 #define GEN6_PMIIR 0x44028 3981 #define GEN6_PMIER 0x4402C 3982 #define GEN6_PM_MBOX_EVENT (1<<25) 3983 #define GEN6_PM_THERMAL_EVENT (1<<24) 3984 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) 3985 #define GEN6_PM_RP_UP_THRESHOLD (1<<5) 3986 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) 3987 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) 3988 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) 3989 #define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ 3990 GEN6_PM_RP_DOWN_THRESHOLD | \ 3991 GEN6_PM_RP_DOWN_TIMEOUT) 3992 3993 #define GEN6_GT_GFX_RC6_LOCKED 0x138104 3994 #define GEN6_GT_GFX_RC6 0x138108 3995 #define GEN6_GT_GFX_RC6p 0x13810C 3996 #define GEN6_GT_GFX_RC6pp 0x138110 3997 3998 #define GEN6_PCODE_MAILBOX 0x138124 3999 #define GEN6_PCODE_READY (1UL<<31) 4000 #define GEN6_READ_OC_PARAMS 0xc 4001 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 4002 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 4003 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 4004 #define GEN6_PCODE_READ_RC6VIDS 0x5 4005 #define GEN6_ENCODE_RC6_VID(mv) (((mv) / 5) - 245) < 0 ?: 0 4006 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) > 0 ? ((vids) * 5) + 245 : 0) 4007 #define GEN6_PCODE_DATA 0x138128 4008 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 4009 4010 #define GEN6_GT_CORE_STATUS 0x138060 4011 #define GEN6_CORE_CPD_STATE_MASK (7<<4) 4012 #define GEN6_RCn_MASK 7 4013 #define GEN6_RC0 0 4014 #define GEN6_RC3 2 4015 #define GEN6_RC6 3 4016 #define GEN6_RC7 4 4017 4018 #define GEN7_MISCCPCTL (0x9424) 4019 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) 4020 4021 /* IVYBRIDGE DPF */ 4022 #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ 4023 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) 4024 #define GEN7_PARITY_ERROR_VALID (1<<13) 4025 #define GEN7_L3CDERRST1_BANK_MASK (3<<11) 4026 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) 4027 #define GEN7_PARITY_ERROR_ROW(reg) \ 4028 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) 4029 #define GEN7_PARITY_ERROR_BANK(reg) \ 4030 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) 4031 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 4032 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 4033 #define GEN7_L3CDERRST1_ENABLE (1<<7) 4034 4035 #define GEN7_L3LOG_BASE 0xB070 4036 #define GEN7_L3LOG_SIZE 0x80 4037 4038 #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ 4039 #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 4040 #define GEN7_MAX_PS_THREAD_DEP (8<<12) 4041 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) 4042 4043 #define GEN7_ROW_CHICKEN2 0xe4f4 4044 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 4045 #define DOP_CLOCK_GATING_DISABLE (1<<0) 4046 4047 #define G4X_AUD_VID_DID 0x62020 4048 #define INTEL_AUDIO_DEVCL 0x808629FB 4049 #define INTEL_AUDIO_DEVBLC 0x80862801 4050 #define INTEL_AUDIO_DEVCTG 0x80862802 4051 4052 #define G4X_AUD_CNTL_ST 0x620B4 4053 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 4054 #define G4X_ELDV_DEVCTG (1 << 14) 4055 #define G4X_ELD_ADDR (0xf << 5) 4056 #define G4X_ELD_ACK (1 << 4) 4057 #define G4X_HDMIW_HDMIEDID 0x6210C 4058 4059 #define IBX_HDMIW_HDMIEDID_A 0xE2050 4060 #define IBX_HDMIW_HDMIEDID_B 0xE2150 4061 #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ 4062 IBX_HDMIW_HDMIEDID_A, \ 4063 IBX_HDMIW_HDMIEDID_B) 4064 #define IBX_AUD_CNTL_ST_A 0xE20B4 4065 #define IBX_AUD_CNTL_ST_B 0xE21B4 4066 #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \ 4067 IBX_AUD_CNTL_ST_A, \ 4068 IBX_AUD_CNTL_ST_B) 4069 #define IBX_ELD_BUFFER_SIZE (0x1f << 10) 4070 #define IBX_ELD_ADDRESS (0x1f << 5) 4071 #define IBX_ELD_ACK (1 << 4) 4072 #define IBX_AUD_CNTL_ST2 0xE20C0 4073 #define IBX_ELD_VALIDB (1 << 0) 4074 #define IBX_CP_READYB (1 << 1) 4075 4076 #define CPT_HDMIW_HDMIEDID_A 0xE5050 4077 #define CPT_HDMIW_HDMIEDID_B 0xE5150 4078 #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ 4079 CPT_HDMIW_HDMIEDID_A, \ 4080 CPT_HDMIW_HDMIEDID_B) 4081 #define CPT_AUD_CNTL_ST_A 0xE50B4 4082 #define CPT_AUD_CNTL_ST_B 0xE51B4 4083 #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \ 4084 CPT_AUD_CNTL_ST_A, \ 4085 CPT_AUD_CNTL_ST_B) 4086 #define CPT_AUD_CNTRL_ST2 0xE50C0 4087 4088 /* These are the 4 32-bit write offset registers for each stream 4089 * output buffer. It determines the offset from the 4090 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 4091 */ 4092 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) 4093 4094 #define IBX_AUD_CONFIG_A 0xe2000 4095 #define IBX_AUD_CONFIG_B 0xe2100 4096 #define IBX_AUD_CFG(pipe) _PIPE(pipe, \ 4097 IBX_AUD_CONFIG_A, \ 4098 IBX_AUD_CONFIG_B) 4099 #define CPT_AUD_CONFIG_A 0xe5000 4100 #define CPT_AUD_CONFIG_B 0xe5100 4101 #define CPT_AUD_CFG(pipe) _PIPE(pipe, \ 4102 CPT_AUD_CONFIG_A, \ 4103 CPT_AUD_CONFIG_B) 4104 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 4105 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 4106 #define AUD_CONFIG_UPPER_N_SHIFT 20 4107 #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) 4108 #define AUD_CONFIG_LOWER_N_SHIFT 4 4109 #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) 4110 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 4111 #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) 4112 #define AUD_CONFIG_DISABLE_NCTS (1 << 3) 4113 4114 /* HSW Audio */ 4115 #define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */ 4116 #define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */ 4117 #define HSW_AUD_CFG(pipe) _PIPE(pipe, \ 4118 HSW_AUD_CONFIG_A, \ 4119 HSW_AUD_CONFIG_B) 4120 4121 #define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */ 4122 #define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */ 4123 #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \ 4124 HSW_AUD_MISC_CTRL_A, \ 4125 HSW_AUD_MISC_CTRL_B) 4126 4127 #define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */ 4128 #define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */ 4129 #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \ 4130 HSW_AUD_DIP_ELD_CTRL_ST_A, \ 4131 HSW_AUD_DIP_ELD_CTRL_ST_B) 4132 4133 /* Audio Digital Converter */ 4134 #define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */ 4135 #define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */ 4136 #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \ 4137 HSW_AUD_DIG_CNVT_1, \ 4138 HSW_AUD_DIG_CNVT_2) 4139 #define DIP_PORT_SEL_MASK 0x3 4140 4141 #define HSW_AUD_EDID_DATA_A 0x65050 4142 #define HSW_AUD_EDID_DATA_B 0x65150 4143 #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \ 4144 HSW_AUD_EDID_DATA_A, \ 4145 HSW_AUD_EDID_DATA_B) 4146 4147 #define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */ 4148 #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */ 4149 #define AUDIO_INACTIVE_C (1<<11) 4150 #define AUDIO_INACTIVE_B (1<<7) 4151 #define AUDIO_INACTIVE_A (1<<3) 4152 #define AUDIO_OUTPUT_ENABLE_A (1<<2) 4153 #define AUDIO_OUTPUT_ENABLE_B (1<<6) 4154 #define AUDIO_OUTPUT_ENABLE_C (1<<10) 4155 #define AUDIO_ELD_VALID_A (1<<0) 4156 #define AUDIO_ELD_VALID_B (1<<4) 4157 #define AUDIO_ELD_VALID_C (1<<8) 4158 #define AUDIO_CP_READY_A (1<<1) 4159 #define AUDIO_CP_READY_B (1<<5) 4160 #define AUDIO_CP_READY_C (1<<9) 4161 4162 /* HSW Power Wells */ 4163 #define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */ 4164 #define HSW_PWR_WELL_CTL2 0x45404 /* Driver */ 4165 #define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */ 4166 #define HSW_PWR_WELL_CTL4 0x4540C /* Debug */ 4167 #define HSW_PWR_WELL_ENABLE (1UL<<31) 4168 #define HSW_PWR_WELL_STATE (1<<30) 4169 #define HSW_PWR_WELL_CTL5 0x45410 4170 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1UL<<31) 4171 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) 4172 #define HSW_PWR_WELL_FORCE_ON (1<<19) 4173 #define HSW_PWR_WELL_CTL6 0x45414 4174 4175 /* Per-pipe DDI Function Control */ 4176 #define TRANS_DDI_FUNC_CTL_A 0x60400 4177 #define TRANS_DDI_FUNC_CTL_B 0x61400 4178 #define TRANS_DDI_FUNC_CTL_C 0x62400 4179 #define TRANS_DDI_FUNC_CTL_EDP 0x6F400 4180 #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \ 4181 TRANS_DDI_FUNC_CTL_B) 4182 #define TRANS_DDI_FUNC_ENABLE (1UL<<31) 4183 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 4184 #if CONFIG(INTEL_GMA_VERSION_2) 4185 #define TRANS_DDI_PORT_SHIFT 27 4186 #define TRANS_DDI_PORT_WIDTH 0xf 4187 #define TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TRANS_DDI_PORT_SHIFT) 4188 #else 4189 #define TRANS_DDI_PORT_SHIFT 28 4190 #define TRANS_DDI_PORT_WIDTH 7 4191 #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) 4192 #endif 4193 #define TRANS_DDI_PORT_MASK (TRANS_DDI_PORT_WIDTH << TRANS_DDI_PORT_SHIFT) 4194 #define TRANS_DDI_PORT_NONE (0 << TRANS_DDI_PORT_SHIFT) 4195 #define TRANS_DDI_MODE_SELECT_MASK (7<<24) 4196 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24) 4197 #define TRANS_DDI_MODE_SELECT_DVI (1<<24) 4198 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24) 4199 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24) 4200 #define TRANS_DDI_MODE_SELECT_FDI (4<<24) 4201 #define TRANS_DDI_BPC_MASK (7<<20) 4202 #define TRANS_DDI_BPC_8 (0<<20) 4203 #define TRANS_DDI_BPC_10 (1<<20) 4204 #define TRANS_DDI_BPC_6 (2<<20) 4205 #define TRANS_DDI_BPC_12 (3<<20) 4206 #define TRANS_DDI_PVSYNC (1<<17) 4207 #define TRANS_DDI_PHSYNC (1<<16) 4208 #define TRANS_DDI_EDP_INPUT_MASK (7<<12) 4209 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12) 4210 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) 4211 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) 4212 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) 4213 #define TRANS_DDI_BFI_ENABLE (1<<4) 4214 #define TRANS_DDI_PORT_WIDTH_X1 (0<<1) 4215 #define TRANS_DDI_PORT_WIDTH_X2 (1<<1) 4216 #define TRANS_DDI_PORT_WIDTH_X4 (3<<1) 4217 4218 /* DisplayPort Transport Control */ 4219 #define DP_TP_CTL_A 0x64040 4220 #define DP_TP_CTL_B 0x64140 4221 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B) 4222 #define DP_TP_CTL_ENABLE (1UL<<31) 4223 #define DP_TP_CTL_MODE_SST (0<<27) 4224 #define DP_TP_CTL_MODE_MST (1<<27) 4225 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) 4226 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) 4227 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) 4228 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) 4229 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) 4230 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8) 4231 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8) 4232 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) 4233 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) 4234 4235 /* DisplayPort Transport Status */ 4236 #define DP_TP_STATUS_A 0x64044 4237 #define DP_TP_STATUS_B 0x64144 4238 #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B) 4239 #define DP_TP_STATUS_IDLE_DONE (1<<25) 4240 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) 4241 4242 /* DDI Buffer Control */ 4243 #define DDI_BUF_CTL_A 0x64000 4244 #define DDI_BUF_CTL_B 0x64100 4245 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) 4246 #define DDI_BUF_CTL_ENABLE (1UL<<31) 4247 #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ 4248 #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */ 4249 #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */ 4250 #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */ 4251 #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */ 4252 #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */ 4253 #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */ 4254 #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ 4255 #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ 4256 #define DDI_BUF_EMP_MASK (0xf<<24) 4257 #define DDI_BUF_IS_IDLE (1<<7) 4258 #define DDI_A_4_LANES (1<<4) 4259 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 4260 #define DDI_PORT_WIDTH_X1 (0<<1) 4261 #define DDI_PORT_WIDTH_X2 (1<<1) 4262 #define DDI_PORT_WIDTH_X4 (3<<1) 4263 #define DDI_INIT_DISPLAY_DETECTED (1<<0) 4264 4265 /* DDI Buffer Translations */ 4266 #define DDI_BUF_TRANS_A 0x64E00 4267 #define DDI_BUF_TRANS_B 0x64E60 4268 #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) 4269 4270 /* Sideband Interface (SBI) is programmed indirectly, via 4271 * SBI_ADDR, which contains the register offset; and SBI_DATA, 4272 * which contains the payload */ 4273 #define SBI_ADDR 0xC6000 4274 #define SBI_DATA 0xC6004 4275 #define SBI_CTL_STAT 0xC6008 4276 #define SBI_CTL_DEST_ICLK (0x0<<16) 4277 #define SBI_CTL_DEST_MPHY (0x1<<16) 4278 #define SBI_CTL_OP_IORD (0x2<<8) 4279 #define SBI_CTL_OP_IOWR (0x3<<8) 4280 #define SBI_CTL_OP_CRRD (0x6<<8) 4281 #define SBI_CTL_OP_CRWR (0x7<<8) 4282 #define SBI_RESPONSE_FAIL (0x1<<1) 4283 #define SBI_RESPONSE_SUCCESS (0x0<<1) 4284 #define SBI_BUSY (0x1<<0) 4285 #define SBI_READY (0x0<<0) 4286 4287 /* SBI offsets */ 4288 #define SBI_SSCDIVINTPHASE6 0x0600 4289 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) 4290 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) 4291 #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) 4292 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) 4293 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) 4294 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) 4295 #define SBI_SSCCTL 0x020c 4296 #define SBI_SSCCTL6 0x060C 4297 #define SBI_SSCCTL_PATHALT (1<<3) 4298 #define SBI_SSCCTL_DISABLE (1<<0) 4299 #define SBI_SSCAUXDIV6 0x0610 4300 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) 4301 #define SBI_DBUFF0 0x2a00 4302 #define SBI_DBUFF0_ENABLE (1<<0) 4303 4304 /* LPT PIXCLK_GATE */ 4305 #define PIXCLK_GATE 0xC6020 4306 #define PIXCLK_GATE_UNGATE (1<<0) 4307 #define PIXCLK_GATE_GATE (0<<0) 4308 4309 /* SPLL */ 4310 #define SPLL_CTL 0x46020 4311 #define SPLL_PLL_ENABLE (1UL<<31) 4312 #define SPLL_PLL_SSC (1<<28) 4313 #define SPLL_PLL_NON_SSC (2<<28) 4314 #define SPLL_PLL_FREQ_810MHz (0<<26) 4315 #define SPLL_PLL_FREQ_1350MHz (1<<26) 4316 4317 /* WRPLL */ 4318 #define WRPLL_CTL1 0x46040 4319 #define WRPLL_CTL2 0x46060 4320 #define WRPLL_PLL_ENABLE (1UL<<31) 4321 #define WRPLL_PLL_SELECT_SSC (0x01<<28) 4322 #define WRPLL_PLL_SELECT_NON_SSC (0x02<<28) 4323 #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28) 4324 /* WRPLL divider programming */ 4325 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) 4326 #define WRPLL_DIVIDER_POST(x) ((x)<<8) 4327 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) 4328 4329 /* Port clock selection */ 4330 #define PORT_CLK_SEL_A 0x46100 4331 #define PORT_CLK_SEL_B 0x46104 4332 #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B) 4333 #define PORT_CLK_SEL_LCPLL_2700 (0<<29) 4334 #define PORT_CLK_SEL_LCPLL_1350 (1<<29) 4335 #define PORT_CLK_SEL_LCPLL_810 (2<<29) 4336 #define PORT_CLK_SEL_SPLL (3<<29) 4337 #define PORT_CLK_SEL_WRPLL1 (4<<29) 4338 #define PORT_CLK_SEL_WRPLL2 (5<<29) 4339 #define PORT_CLK_SEL_NONE (7<<29) 4340 4341 /* Transcoder clock selection */ 4342 #define TRANS_CLK_SEL_A 0x46140 4343 #define TRANS_CLK_SEL_B 0x46144 4344 #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B) 4345 /* For each transcoder, we need to select the corresponding port clock */ 4346 #define TRANS_CLK_SEL_DISABLED (0x0<<29) 4347 #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) 4348 4349 #define _TRANSA_MSA_MISC 0x60410 4350 #define _TRANSB_MSA_MISC 0x61410 4351 #define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \ 4352 _TRANSB_MSA_MISC) 4353 #define TRANS_MSA_SYNC_CLK (1<<0) 4354 #define TRANS_MSA_6_BPC (0<<5) 4355 #define TRANS_MSA_8_BPC (1<<5) 4356 #define TRANS_MSA_10_BPC (2<<5) 4357 #define TRANS_MSA_12_BPC (3<<5) 4358 #define TRANS_MSA_16_BPC (4<<5) 4359 4360 /* LCPLL Control */ 4361 #define LCPLL_CTL 0x130040 4362 #define LCPLL_PLL_DISABLE (1UL<<31) 4363 #define LCPLL_PLL_LOCK (1<<30) 4364 #define LCPLL_CLK_FREQ_MASK (3<<26) 4365 #define LCPLL_CLK_FREQ_450 (0<<26) 4366 #define LCPLL_CD_CLOCK_DISABLE (1<<25) 4367 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) 4368 #define LCPLL_CD_SOURCE_FCLK (1<<21) 4369 4370 /* Pipe WM_LINETIME - watermark line time */ 4371 #define PIPE_WM_LINETIME_A 0x45270 4372 #define PIPE_WM_LINETIME_B 0x45274 4373 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \ 4374 PIPE_WM_LINETIME_B) 4375 #define PIPE_WM_LINETIME_MASK (0x1ff) 4376 #define PIPE_WM_LINETIME_TIME(x) ((x)) 4377 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) 4378 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) 4379 4380 /* SFUSE_STRAP */ 4381 #define SFUSE_STRAP 0xc2014 4382 #define SFUSE_STRAP_DDIB_DETECTED (1<<2) 4383 #define SFUSE_STRAP_DDIC_DETECTED (1<<1) 4384 #define SFUSE_STRAP_DDID_DETECTED (1<<0) 4385 4386 #define WM_DBG 0x45280 4387 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) 4388 #define WM_DBG_DISALLOW_MAXFIFO (1<<1) 4389 #define WM_DBG_DISALLOW_SPRITE (1<<2) 4390 4391 /* North Display Engine Reset Warn Options */ 4392 #define NDE_RSTWRN_OPT 0x46408 4393 #define RST_PCH_HNDSHK_EN (1<<4) 4394 4395 #endif /* _I915_REG_H_ */ 4396