1 /*
2 * Copyright (c) 2015-2020, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file vphal_render_common.c
24 //! \brief The file of common utilities definitions shared by low level renderers
25 //! \details Common utilities for different renderers, e.g. DNDI or Comp
26 //!
27 #include "vphal_render_common.h"
28 #include "vphal_render_composite.h"
29 #include "mos_os.h"
30 #include "mos_solo_generic.h"
31 #include "hal_oca_interface.h"
32
33 extern const MEDIA_OBJECT_KA2_INLINE_DATA g_cInit_MEDIA_OBJECT_KA2_INLINE_DATA =
34 {
35 // DWORD 0
36 {
37 0, // DestinationBlockHorizontalOrigin
38 0 // DestinationBlockVerticalOrigin
39 },
40
41 // DWORD 1
42 {
43 0, // HorizontalBlockCompositeMaskLayer0
44 0 // VerticalBlockCompositeMaskLayer0
45 },
46
47 // DWORD 2
48 {
49 0, // HorizontalBlockCompositeMaskLayer1
50 0 // VerticalBlockCompositeMaskLayer1
51 },
52
53 // DWORD 3
54 {
55 0, // HorizontalBlockCompositeMaskLayer2
56 0 // VerticalBlockCompositeMaskLayer2
57 },
58
59 // DWORD 4
60 0.0F, // VideoXScalingStep
61
62 // DWORD 5
63 0.0F, // VideoStepDelta
64
65 // DWORD 6
66 {
67 0, // VerticalBlockNumber
68 0 // AreaOfInterest
69 },
70
71 // DWORD 7
72 {
73 0, // GroupIDNumber
74 },
75
76 // DWORD 8
77 {
78 0, // HorizontalBlockCompositeMaskLayer3
79 0 // VerticalBlockCompositeMaskLayer3
80 },
81
82 // DWORD 9
83 {
84 0, // HorizontalBlockCompositeMaskLayer4
85 0 // VerticalBlockCompositeMaskLayer4
86 },
87
88 // DWORD 10
89 {
90 0, // HorizontalBlockCompositeMaskLayer5
91 0 // VerticalBlockCompositeMaskLayer5
92 },
93
94 // DWORD 11
95 {
96 0, // HorizontalBlockCompositeMaskLayer6
97 0 // VerticalBlockCompositeMaskLayer6
98 },
99
100 // DWORD 12
101 {
102 0, // HorizontalBlockCompositeMaskLayer7
103 0 // VerticalBlockCompositeMaskLayer7
104 },
105
106 // DWORD 13
107 0, // Reserved
108
109 // DWORD 14
110 0, // Reserved
111
112 // DWORD 15
113 0 // Reserved
114 };
115
116 //!
117 //! \brief Initialized RenderHal Surface Type
118 //! \details Initialized RenderHal Surface Type according to input VPHAL Surface Type
119 //! \param [in] vpSurfType
120 //! VPHAL surface type
121 //! \return RENDERHAL_SURFACE_TYPE
122 //!
VpHal_RndrInitRenderHalSurfType(VPHAL_SURFACE_TYPE vpSurfType)123 static inline RENDERHAL_SURFACE_TYPE VpHal_RndrInitRenderHalSurfType(VPHAL_SURFACE_TYPE vpSurfType)
124 {
125 switch (vpSurfType)
126 {
127 case SURF_IN_BACKGROUND:
128 return RENDERHAL_SURF_IN_BACKGROUND;
129
130 case SURF_IN_PRIMARY:
131 return RENDERHAL_SURF_IN_PRIMARY;
132
133 case SURF_IN_SUBSTREAM:
134 return RENDERHAL_SURF_IN_SUBSTREAM;
135
136 case SURF_IN_REFERENCE:
137 return RENDERHAL_SURF_IN_REFERENCE;
138
139 case SURF_OUT_RENDERTARGET:
140 return RENDERHAL_SURF_OUT_RENDERTARGET;
141
142 case SURF_NONE:
143 default:
144 return RENDERHAL_SURF_NONE;
145 }
146 }
147
148 //!
149 //! \brief Initialized RenderHal Scaling Mode
150 //! \details Initialized RenderHal Scaling Mode according to input VPHAL Scaling Mode
151 //! \param [in] vpScalingMode
152 //! VPHAL Scaling Mode
153 //! \return RENDERHAL_SCALING_MODE
154 //!
VpHal_RndrInitRenderHalScalingMode(VPHAL_SCALING_MODE vpScalingMode)155 static inline RENDERHAL_SCALING_MODE VpHal_RndrInitRenderHalScalingMode(VPHAL_SCALING_MODE vpScalingMode)
156 {
157 switch (vpScalingMode)
158 {
159 case VPHAL_SCALING_NEAREST:
160 return RENDERHAL_SCALING_NEAREST;
161
162 case VPHAL_SCALING_BILINEAR:
163 return RENDERHAL_SCALING_BILINEAR;
164
165 case VPHAL_SCALING_AVS:
166 return RENDERHAL_SCALING_AVS;
167
168 default:
169 VPHAL_RENDER_ASSERTMESSAGE("Invalid VPHAL_SCALING_MODE %d, force to nearest mode.", vpScalingMode);
170 return RENDERHAL_SCALING_NEAREST;
171 }
172 }
173
174 //!
175 //! \brief Get VpHal Scaling Mode
176 //! \details Get VpHal Scaling Mode according to RenderHal Scaling Mode
177 //! \param [in] RenderHalScalingMode
178 //! RENDERHAL Scaling Mode
179 //! \return VPHAL_SCALING_MODE
180 //!
VpHal_RndrGetVpHalScalingMode(RENDERHAL_SCALING_MODE RenderHalScalingMode)181 static inline VPHAL_SCALING_MODE VpHal_RndrGetVpHalScalingMode(RENDERHAL_SCALING_MODE RenderHalScalingMode)
182 {
183 switch (RenderHalScalingMode)
184 {
185 case RENDERHAL_SCALING_NEAREST:
186 return VPHAL_SCALING_NEAREST;
187
188 case RENDERHAL_SCALING_BILINEAR:
189 return VPHAL_SCALING_BILINEAR;
190
191 case RENDERHAL_SCALING_AVS:
192 return VPHAL_SCALING_AVS;
193
194 default:
195 VPHAL_RENDER_ASSERTMESSAGE("Invalid RENDERHAL_SCALING_MODE %d, force to nearest mode.", RenderHalScalingMode);
196 return VPHAL_SCALING_NEAREST;
197 }
198 }
199
200 //!
201 //! \brief Initialized RenderHal Sample Type
202 //! \details Initialized RenderHal Sample Type according to input VPHAL Sample Type
203 //! \param [in] SampleType
204 //! VPHAL Sample Type
205 //! \return RENDERHAL_SAMPLE_TYPE
206 //!
VpHal_RndrInitRenderHalSampleType(VPHAL_SAMPLE_TYPE SampleType)207 static inline RENDERHAL_SAMPLE_TYPE VpHal_RndrInitRenderHalSampleType(VPHAL_SAMPLE_TYPE SampleType)
208 {
209 switch (SampleType)
210 {
211 case SAMPLE_PROGRESSIVE:
212 return RENDERHAL_SAMPLE_PROGRESSIVE;
213
214 case SAMPLE_SINGLE_TOP_FIELD:
215 return RENDERHAL_SAMPLE_SINGLE_TOP_FIELD;
216
217 case SAMPLE_SINGLE_BOTTOM_FIELD:
218 return RENDERHAL_SAMPLE_SINGLE_BOTTOM_FIELD;
219
220 case SAMPLE_INTERLEAVED_EVEN_FIRST_TOP_FIELD:
221 return RENDERHAL_SAMPLE_INTERLEAVED_EVEN_FIRST_TOP_FIELD;
222
223 case SAMPLE_INTERLEAVED_EVEN_FIRST_BOTTOM_FIELD:
224 return RENDERHAL_SAMPLE_INTERLEAVED_EVEN_FIRST_BOTTOM_FIELD;
225
226 case SAMPLE_INTERLEAVED_ODD_FIRST_TOP_FIELD:
227 return RENDERHAL_SAMPLE_INTERLEAVED_ODD_FIRST_TOP_FIELD;
228
229 case SAMPLE_INTERLEAVED_ODD_FIRST_BOTTOM_FIELD:
230 return RENDERHAL_SAMPLE_INTERLEAVED_ODD_FIRST_BOTTOM_FIELD;
231
232 case SAMPLE_INVALID:
233 default:
234 VPHAL_RENDER_ASSERTMESSAGE("Invalid VPHAL_SAMPLE_TYPE %d.\n", SampleType);
235 return RENDERHAL_SAMPLE_INVALID;
236 }
237 }
238
VpHal_RndrInitPlaneOffset(PMOS_PLANE_OFFSET pMosPlaneOffset,PVPHAL_PLANE_OFFSET pVpPlaneOffset)239 static inline void VpHal_RndrInitPlaneOffset(
240 PMOS_PLANE_OFFSET pMosPlaneOffset,
241 PVPHAL_PLANE_OFFSET pVpPlaneOffset)
242 {
243 pMosPlaneOffset->iSurfaceOffset = pVpPlaneOffset->iSurfaceOffset;
244 pMosPlaneOffset->iXOffset = pVpPlaneOffset->iXOffset;
245 pMosPlaneOffset->iYOffset = pVpPlaneOffset->iYOffset;
246 pMosPlaneOffset->iLockSurfaceOffset = pVpPlaneOffset->iLockSurfaceOffset;
247
248 }
249
250 //!
251 //! \brief Initialized MHW Rotation mode
252 //! \details Initialized MHW Rotation mode according to input VPHAL Rotation Type
253 //! \param [in] Rotation
254 //! VPHAL Rotation mode
255 //! \return MHW_ROTATION
256 //!
VpHal_RndrInitRotationMode(VPHAL_ROTATION Rotation)257 static inline MHW_ROTATION VpHal_RndrInitRotationMode(VPHAL_ROTATION Rotation)
258 {
259 MHW_ROTATION Mode = MHW_ROTATION_IDENTITY;
260
261 switch (Rotation)
262 {
263 case VPHAL_ROTATION_IDENTITY:
264 Mode = MHW_ROTATION_IDENTITY;
265 break;
266
267 case VPHAL_ROTATION_90:
268 Mode = MHW_ROTATION_90;
269 break;
270
271 case VPHAL_ROTATION_180:
272 Mode = MHW_ROTATION_180;
273 break;
274
275 case VPHAL_ROTATION_270:
276 Mode = MHW_ROTATION_270;
277 break;
278
279 case VPHAL_MIRROR_HORIZONTAL:
280 Mode = MHW_MIRROR_HORIZONTAL;
281 break;
282
283 case VPHAL_MIRROR_VERTICAL:
284 Mode = MHW_MIRROR_VERTICAL;
285 break;
286
287 case VPHAL_ROTATE_90_MIRROR_VERTICAL:
288 Mode = MHW_ROTATE_90_MIRROR_VERTICAL;
289 break;
290
291 case VPHAL_ROTATE_90_MIRROR_HORIZONTAL:
292 Mode = MHW_ROTATE_90_MIRROR_HORIZONTAL;
293 break;
294
295 default:
296 VPHAL_RENDER_ASSERTMESSAGE("Invalid Rotation Angle.");
297 break;
298 }
299
300 return Mode;
301 }
302
303 //!
304 //! \brief Set the numbers of Slice, Sub-slice, EUs for power mode
305 //! \details Set the numbers of Slice, Sub-slice, EUs recommended for
306 //! the given kernel type for power mode
307 //! \param [in] pRenderHal
308 //! Pointer to RenderHal Interface Structure
309 //! \param [in] KernelID
310 //! VP render Kernel ID
311 //! \return MOS_STATUS
312 //! MOS_STATUS_SUCCESS if success. Error code otherwise
313 //!
VpHal_RndrCommonSetPowerMode(PRENDERHAL_INTERFACE pRenderHal,VpKernelID KernelID)314 MOS_STATUS VpHal_RndrCommonSetPowerMode(
315 PRENDERHAL_INTERFACE pRenderHal,
316 VpKernelID KernelID)
317 {
318 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
319 uint16_t wNumRequestedEUSlices = 1; // Default to 1 slice
320 uint16_t wNumRequestedSubSlices = 3; // Default to 3 subslice
321 uint16_t wNumRequestedEUs = 8; // Default to 8 EUs
322 RENDERHAL_POWEROPTION PowerOption;
323 bool bSetRequestedSlices = false;
324 const VphalSseuSetting *pcSSEUTable = nullptr;
325 MediaUserSettingSharedPtr userSettingPtr = nullptr;
326 uint32_t value = 0;
327
328 VPHAL_RENDER_CHK_NULL(pRenderHal);
329
330 if ((pRenderHal->bRequestSingleSlice) || (pRenderHal->bEUSaturationNoSSD))
331 {
332 bSetRequestedSlices = true;
333 // bEUSaturationNoSSD: No slice shutdown, must request 2 slices [CM EU saturation on].
334 // bRequestSingleSlice: Always single slice.
335 wNumRequestedEUSlices = (pRenderHal->bEUSaturationNoSSD) ? 2 : 1;
336 }
337 else
338 {
339 bSetRequestedSlices = false;
340 }
341
342 if (pRenderHal->sseuTable)
343 {
344 pcSSEUTable = (const VphalSseuSetting*)pRenderHal->sseuTable;
345 }
346 else
347 {
348 VPHAL_RENDER_ASSERTMESSAGE("SSEU Table not valid.");
349 eStatus = MOS_STATUS_UNKNOWN;
350 goto finish;
351 }
352
353 VPHAL_RENDER_CHK_NULL(pcSSEUTable);
354 pcSSEUTable += KernelID;
355 if (!bSetRequestedSlices) // If num Slices is already programmed, then don't change it
356 {
357 if (wNumRequestedEUSlices < pcSSEUTable->numSlices)
358 {
359 wNumRequestedEUSlices = pcSSEUTable->numSlices;
360 }
361 }
362
363 wNumRequestedSubSlices = pcSSEUTable->numSubSlices;
364 wNumRequestedEUs = pcSSEUTable->numEUs;
365
366 #if (_DEBUG || _RELEASE_INTERNAL)
367 // User feature key reads
368 userSettingPtr = pRenderHal->pOsInterface->pfnGetUserSettingInstance(pRenderHal->pOsInterface);
369 ReadUserSettingForDebug(
370 userSettingPtr,
371 value,
372 __MEDIA_USER_FEATURE_VALUE_SSEU_SETTING_OVERRIDE,
373 MediaUserSetting::Group::Device);
374 if (value != 0xDEADC0DE)
375 {
376 wNumRequestedEUSlices = value & 0xFF; // Bits 0-7
377 wNumRequestedSubSlices = (value >> 8) & 0xFF; // Bits 8-15
378 wNumRequestedEUs = (value >> 16) & 0xFFFF; // Bits 16-31
379 }
380 #endif
381
382 PowerOption.nSlice = wNumRequestedEUSlices;
383 PowerOption.nSubSlice = wNumRequestedSubSlices;
384 PowerOption.nEU = wNumRequestedEUs;
385 pRenderHal->pfnSetPowerOptionMode(pRenderHal, &PowerOption);
386
387 finish:
388 return eStatus;
389 }
390
391 // so will enable other renderers like frc and istab support status report.
392 //!
393 //! \brief Submit commands for rendering
394 //! \details Submit commands for rendering. The KMD related fields in pGenericPrologParam might be modified by this
395 //! function in order to maintain the synchronization mechanism for resource.
396 //! \param [in] pRenderHal
397 //! Pointer to RenderHal Interface Structure
398 //! \param [in] pBatchBuffer
399 //! Pointer to batch buffer
400 //! \param [in] bNullRendering
401 //! Indicate whether is Null rendering
402 //! \param [in] pWalkerParams
403 //! Pointer to walker parameters
404 //! \param [in] pGpGpuWalkerParams
405 //! Pointer to GPGPU walker parameters
406 //! \param [in] KernelID
407 //! VP Kernel ID
408 //! \param [in] bLastSubmission
409 //! Is last submission
410 //! \return MOS_STATUS
411 //!
VpHal_RndrCommonSubmitCommands(PRENDERHAL_INTERFACE pRenderHal,PMHW_BATCH_BUFFER pBatchBuffer,bool bNullRendering,PMHW_WALKER_PARAMS pWalkerParams,PMHW_GPGPU_WALKER_PARAMS pGpGpuWalkerParams,VpKernelID KernelID,bool bLastSubmission)412 MOS_STATUS VpHal_RndrCommonSubmitCommands(
413 PRENDERHAL_INTERFACE pRenderHal,
414 PMHW_BATCH_BUFFER pBatchBuffer,
415 bool bNullRendering,
416 PMHW_WALKER_PARAMS pWalkerParams,
417 PMHW_GPGPU_WALKER_PARAMS pGpGpuWalkerParams,
418 VpKernelID KernelID,
419 bool bLastSubmission)
420 {
421 PMOS_INTERFACE pOsInterface = nullptr;
422 MOS_COMMAND_BUFFER CmdBuffer = {};
423 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
424 uint32_t dwSyncTag = 0;
425 int32_t i = 0, iRemaining = 0;
426 PMHW_MI_INTERFACE pMhwMiInterface = nullptr;
427 MhwRenderInterface *pMhwRender = nullptr;
428 MHW_MEDIA_STATE_FLUSH_PARAM FlushParam = {};
429 bool bEnableSLM = false;
430 RENDERHAL_GENERIC_PROLOG_PARAMS GenericPrologParams = {};
431 PMOS_RESOURCE gpuStatusBuffer = nullptr;
432 MediaPerfProfiler *pPerfProfiler = nullptr;
433 MOS_CONTEXT *pOsContext = nullptr;
434 PMHW_MI_MMIOREGISTERS pMmioRegisters = nullptr;
435 PRENDERHAL_INTERFACE_LEGACY pRenderHalLegacy = (PRENDERHAL_INTERFACE_LEGACY)pRenderHal;
436
437 MHW_RENDERHAL_CHK_NULL(pRenderHalLegacy);
438 MHW_RENDERHAL_CHK_NULL(pRenderHalLegacy->pMhwRenderInterface);
439 MHW_RENDERHAL_CHK_NULL(pRenderHalLegacy->pMhwMiInterface);
440 MHW_RENDERHAL_CHK_NULL(pRenderHalLegacy->pMhwRenderInterface->GetMmioRegisters());
441 MHW_RENDERHAL_CHK_NULL(pRenderHalLegacy->pOsInterface);
442 MHW_RENDERHAL_CHK_NULL(pRenderHalLegacy->pOsInterface->pOsContext);
443 MHW_RENDERHAL_CHK_NULL(pRenderHalLegacy->pPerfProfiler);
444
445 eStatus = MOS_STATUS_UNKNOWN;
446 pOsInterface = pRenderHalLegacy->pOsInterface;
447 pMhwMiInterface = pRenderHalLegacy->pMhwMiInterface;
448 pMhwRender = pRenderHalLegacy->pMhwRenderInterface;
449 iRemaining = 0;
450 FlushParam = g_cRenderHal_InitMediaStateFlushParams;
451 MOS_ZeroMemory(&CmdBuffer, sizeof(CmdBuffer));
452 pPerfProfiler = pRenderHalLegacy->pPerfProfiler;
453 pOsContext = pOsInterface->pOsContext;
454 pMmioRegisters = pMhwRender->GetMmioRegisters();
455
456 // Allocate all available space, unused buffer will be returned later
457 VPHAL_RENDER_CHK_STATUS(pOsInterface->pfnGetCommandBuffer(pOsInterface, &CmdBuffer, 0));
458
459 // Set initial state
460 iRemaining = CmdBuffer.iRemaining;
461
462 VPHAL_RENDER_CHK_STATUS(VpHal_RndrCommonSetPowerMode(
463 pRenderHalLegacy,
464 KernelID));
465
466 #ifndef EMUL
467 if (bLastSubmission && pOsInterface->bEnableKmdMediaFrameTracking)
468 {
469 // Get GPU Status buffer
470 VPHAL_RENDER_CHK_STATUS(pOsInterface->pfnGetGpuStatusBufferResource(pOsInterface, gpuStatusBuffer));
471 VPHAL_RENDER_CHK_NULL(gpuStatusBuffer);
472 // Register the buffer
473 VPHAL_RENDER_CHK_STATUS(pOsInterface->pfnRegisterResource(pOsInterface, gpuStatusBuffer, true, true));
474
475 GenericPrologParams.bEnableMediaFrameTracking = true;
476 GenericPrologParams.presMediaFrameTrackingSurface = gpuStatusBuffer;
477 GenericPrologParams.dwMediaFrameTrackingTag = pOsInterface->pfnGetGpuStatusTag(pOsInterface, pOsInterface->CurrentGpuContextOrdinal);
478 GenericPrologParams.dwMediaFrameTrackingAddrOffset = pOsInterface->pfnGetGpuStatusTagOffset(pOsInterface, pOsInterface->CurrentGpuContextOrdinal);
479
480 // Increment GPU Status Tag
481 pOsInterface->pfnIncrementGpuStatusTag(pOsInterface, pOsInterface->CurrentGpuContextOrdinal);
482 }
483 #endif
484
485 HalOcaInterface::On1stLevelBBStart(CmdBuffer, *pOsContext, pOsInterface->CurrentGpuContextHandle,
486 *pRenderHalLegacy->pMhwMiInterface, *pMmioRegisters);
487
488 // Add kernel info to log.
489 HalOcaInterface::DumpVpKernelInfo(CmdBuffer, (MOS_CONTEXT_HANDLE)pOsContext, KernelID, 0, nullptr);
490 // Add vphal param to log.
491 HalOcaInterface::DumpVphalParam(CmdBuffer, (MOS_CONTEXT_HANDLE)pOsContext, pRenderHalLegacy->pVphalOcaDumper);
492
493 // Initialize command buffer and insert prolog
494 VPHAL_RENDER_CHK_STATUS(pRenderHalLegacy->pfnInitCommandBuffer(pRenderHalLegacy, &CmdBuffer, &GenericPrologParams));
495
496 // Write timing data for 3P budget
497 VPHAL_RENDER_CHK_STATUS(pRenderHalLegacy->pfnSendTimingData(pRenderHalLegacy, &CmdBuffer, true));
498 VPHAL_RENDER_CHK_STATUS(pPerfProfiler->AddPerfCollectStartCmd((void*)pRenderHalLegacy, pOsInterface, pMhwMiInterface, &CmdBuffer));
499
500 VPHAL_RENDER_CHK_STATUS(NullHW::StartPredicate(pOsInterface, pRenderHalLegacy->pMhwMiInterface, &CmdBuffer));
501
502 bEnableSLM = (pGpGpuWalkerParams && pGpGpuWalkerParams->SLMSize > 0)? true : false;
503 VPHAL_RENDER_CHK_STATUS(pRenderHalLegacy->pfnSetCacheOverrideParams(
504 pRenderHalLegacy,
505 &pRenderHalLegacy->L3CacheSettings,
506 bEnableSLM));
507
508 // Flush media states
509 VPHAL_RENDER_CHK_STATUS(pRenderHalLegacy->pfnSendMediaStates(
510 pRenderHalLegacy,
511 &CmdBuffer,
512 pWalkerParams,
513 pGpGpuWalkerParams));
514
515 if (pBatchBuffer)
516 {
517 // Register batch buffer for rendering
518 VPHAL_RENDER_CHK_STATUS(pOsInterface->pfnRegisterResource(
519 pOsInterface,
520 &pBatchBuffer->OsResource,
521 false,
522 true));
523
524 HalOcaInterface::OnSubLevelBBStart(CmdBuffer, (MOS_CONTEXT_HANDLE)pOsContext, &pBatchBuffer->OsResource, 0, true, 0);
525
526 // Send Start 2nd level batch buffer command (HW/OS dependent)
527 VPHAL_RENDER_CHK_STATUS(pMhwMiInterface->AddMiBatchBufferStartCmd(
528 &CmdBuffer,
529 pBatchBuffer));
530 }
531
532 // Write back GPU Status tag
533 if (!pOsInterface->bEnableKmdMediaFrameTracking)
534 {
535 VPHAL_RENDER_CHK_STATUS(pRenderHalLegacy->pfnSendRcsStatusTag(pRenderHalLegacy, &CmdBuffer));
536 }
537
538 VPHAL_RENDER_CHK_STATUS(NullHW::StopPredicate(pOsInterface, pRenderHalLegacy->pMhwMiInterface, &CmdBuffer));
539
540 VPHAL_RENDER_CHK_STATUS(pPerfProfiler->AddPerfCollectEndCmd((void*)pRenderHalLegacy, pOsInterface, pMhwMiInterface, &CmdBuffer));
541
542 // Write timing data for 3P budget
543 VPHAL_RENDER_CHK_STATUS(pRenderHalLegacy->pfnSendTimingData(pRenderHalLegacy, &CmdBuffer, false));
544
545 if (GFX_IS_GEN_9_OR_LATER(pRenderHalLegacy->Platform))
546 {
547 MHW_PIPE_CONTROL_PARAMS PipeControlParams;
548
549 MOS_ZeroMemory(&PipeControlParams, sizeof(PipeControlParams));
550 PipeControlParams.dwFlushMode = MHW_FLUSH_WRITE_CACHE;
551 PipeControlParams.bGenericMediaStateClear = true;
552 PipeControlParams.bIndirectStatePointersDisable = true;
553 PipeControlParams.bDisableCSStall = false;
554 VPHAL_RENDER_CHK_STATUS(pMhwMiInterface->AddPipeControl(&CmdBuffer, nullptr, &PipeControlParams));
555
556 if (MEDIA_IS_WA(pRenderHalLegacy->pWaTable, WaSendDummyVFEafterPipelineSelect))
557 {
558 MHW_VFE_PARAMS VfeStateParams = {};
559 VfeStateParams.dwNumberofURBEntries = 1;
560 VPHAL_RENDER_CHK_STATUS(pMhwRender->AddMediaVfeCmd(&CmdBuffer, &VfeStateParams));
561 }
562 }
563
564 if (GFX_IS_GEN_8_OR_LATER(pRenderHalLegacy->Platform))
565 {
566 // Add media flush command in case HW not cleaning the media state
567 if (MEDIA_IS_WA(pRenderHalLegacy->pWaTable, WaMSFWithNoWatermarkTSGHang))
568 {
569 FlushParam.bFlushToGo = true;
570 if (pWalkerParams)
571 {
572 FlushParam.ui8InterfaceDescriptorOffset = pWalkerParams->InterfaceDescriptorOffset;
573 }
574 else
575 {
576 VPHAL_RENDER_ASSERTMESSAGE("ERROR, pWalkerParams is nullptr and cannot get InterfaceDescriptorOffset.");
577 }
578 VPHAL_RENDER_CHK_STATUS(pMhwMiInterface->AddMediaStateFlush(&CmdBuffer, nullptr, &FlushParam));
579 }
580 else if (MEDIA_IS_WA(pRenderHalLegacy->pWaTable, WaAddMediaStateFlushCmd))
581 {
582 VPHAL_RENDER_CHK_STATUS(pMhwMiInterface->AddMediaStateFlush(&CmdBuffer, nullptr, &FlushParam));
583 }
584 }
585
586 HalOcaInterface::On1stLevelBBEnd(CmdBuffer, *pOsInterface);
587
588 if (pBatchBuffer)
589 {
590 // Send Batch Buffer end command (HW/OS dependent)
591 VPHAL_RENDER_CHK_STATUS(pMhwMiInterface->AddMiBatchBufferEnd(&CmdBuffer, nullptr));
592 }
593 else if (VpHal_RndrCommonIsMiBBEndNeeded(pOsInterface))
594 {
595 // Send Batch Buffer end command for 1st level Batch Buffer
596 VPHAL_RENDER_CHK_STATUS(pMhwMiInterface->AddMiBatchBufferEnd(&CmdBuffer, nullptr));
597 }
598 else if (GFX_IS_GEN_8_OR_LATER(pRenderHalLegacy->Platform) &&
599 Mos_Solo_IsInUse(pOsInterface) &&
600 pRenderHalLegacy->pOsInterface->bNoParsingAssistanceInKmd)
601 {
602 VPHAL_RENDER_CHK_STATUS(pMhwMiInterface->AddMiBatchBufferEnd(&CmdBuffer, nullptr));
603 }
604
605 // Return unused command buffer space to OS
606 pOsInterface->pfnReturnCommandBuffer(pOsInterface, &CmdBuffer, 0);
607
608 // VPHAL_DBG_STATE_DUMPPER_DUMP_COMMAND_BUFFER(pRenderHal, &CmdBuffer);
609
610 // Submit command buffer
611 VPHAL_RENDER_CHK_STATUS(pOsInterface->pfnSubmitCommandBuffer(pOsInterface, &CmdBuffer, bNullRendering));
612
613 if (bNullRendering == false)
614 {
615 dwSyncTag = pRenderHalLegacy->pStateHeap->dwNextTag++;
616
617 // Set media state and batch buffer as busy
618 pRenderHalLegacy->pStateHeap->pCurMediaState->bBusy = true;
619 if (pBatchBuffer)
620 {
621 pBatchBuffer->bBusy = true;
622 pBatchBuffer->dwSyncTag = dwSyncTag;
623 }
624 }
625
626 eStatus = MOS_STATUS_SUCCESS;
627
628 finish:
629 // Failed -> discard all changes in Command Buffer
630 if (eStatus != MOS_STATUS_SUCCESS)
631 {
632 // Buffer overflow - display overflow size
633 if (CmdBuffer.iRemaining < 0)
634 {
635 VPHAL_RENDER_ASSERTMESSAGE("Command Buffer overflow by %d bytes", -CmdBuffer.iRemaining);
636 }
637
638 // Move command buffer back to beginning
639 i = iRemaining - CmdBuffer.iRemaining;
640 CmdBuffer.iRemaining = iRemaining;
641 CmdBuffer.iOffset -= i;
642 CmdBuffer.pCmdPtr =
643 CmdBuffer.pCmdBase + CmdBuffer.iOffset / sizeof(uint32_t);
644
645 // Return unused command buffer space to OS
646 if (pOsInterface)
647 {
648 pOsInterface->pfnReturnCommandBuffer(pOsInterface, &CmdBuffer, 0);
649 }
650 }
651
652 return eStatus;
653 }
654
655 //!
656 //! \brief Submit commands for rendering
657 //! \details Submit commands for rendering with status table update enabling
658 //! \param [in] pRenderHal
659 //! Pointer to RenderHal Interface Structure
660 //! \param [in] pBatchBuffer
661 //! Pointer to batch buffer
662 //! \param [in] bNullRendering
663 //! Indicate whether is Null rendering
664 //! \param [in] pWalkerParams
665 //! Pointer to walker parameters
666 //! \param [in] pGpGpuWalkerParams
667 //! Pointer to GPGPU walker parameters
668 //! \param [in] pStatusTableUpdateParams
669 //! Pointer to pStatusTableUpdateParams
670 //! \param [in] KernelID
671 //! VP Kernel ID
672 //! \param [in] FcKernelCount
673 //! VP FC Kernel Count
674 //! \param [in] FcKernelList
675 //! VP FC Kernel List
676 //! \param [in] bLastSubmission
677 //! Is last submission
678 //! \return MOS_STATUS
679 //!
VpHal_RndrSubmitCommands(PRENDERHAL_INTERFACE pRenderHal,PMHW_BATCH_BUFFER pBatchBuffer,bool bNullRendering,PMHW_WALKER_PARAMS pWalkerParams,PMHW_GPGPU_WALKER_PARAMS pGpGpuWalkerParams,PSTATUS_TABLE_UPDATE_PARAMS pStatusTableUpdateParams,VpKernelID KernelID,int FcKernelCount,int * FcKernelList,bool bLastSubmission)680 MOS_STATUS VpHal_RndrSubmitCommands(
681 PRENDERHAL_INTERFACE pRenderHal,
682 PMHW_BATCH_BUFFER pBatchBuffer,
683 bool bNullRendering,
684 PMHW_WALKER_PARAMS pWalkerParams,
685 PMHW_GPGPU_WALKER_PARAMS pGpGpuWalkerParams,
686 PSTATUS_TABLE_UPDATE_PARAMS pStatusTableUpdateParams,
687 VpKernelID KernelID,
688 int FcKernelCount,
689 int *FcKernelList,
690 bool bLastSubmission)
691 {
692 PMOS_INTERFACE pOsInterface = nullptr;
693 MOS_COMMAND_BUFFER CmdBuffer = {};
694 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
695 uint32_t dwSyncTag = 0;
696 int32_t i = 0, iRemaining = 0;
697 PMHW_MI_INTERFACE pMhwMiInterface = nullptr;
698 MhwRenderInterface *pMhwRender = nullptr;
699 MHW_MEDIA_STATE_FLUSH_PARAM FlushParam = {};
700 bool bEnableSLM = false;
701 RENDERHAL_GENERIC_PROLOG_PARAMS GenericPrologParams = {};
702 PMOS_RESOURCE gpuStatusBuffer = nullptr;
703 MediaPerfProfiler *pPerfProfiler = nullptr;
704 MOS_CONTEXT *pOsContext = nullptr;
705 PMHW_MI_MMIOREGISTERS pMmioRegisters = nullptr;
706 PRENDERHAL_INTERFACE_LEGACY pRenderHalLegacy = (PRENDERHAL_INTERFACE_LEGACY)pRenderHal;
707
708 MHW_RENDERHAL_CHK_NULL(pRenderHalLegacy);
709 MHW_RENDERHAL_CHK_NULL(pRenderHalLegacy->pMhwRenderInterface);
710 MHW_RENDERHAL_CHK_NULL(pRenderHalLegacy->pMhwMiInterface);
711 MHW_RENDERHAL_CHK_NULL(pRenderHalLegacy->pMhwRenderInterface->GetMmioRegisters());
712 MHW_RENDERHAL_CHK_NULL(pRenderHalLegacy->pOsInterface);
713 MHW_RENDERHAL_CHK_NULL(pRenderHalLegacy->pOsInterface->pOsContext);
714 MHW_RENDERHAL_CHK_NULL(pRenderHalLegacy->pPerfProfiler);
715
716 eStatus = MOS_STATUS_UNKNOWN;
717 pOsInterface = pRenderHalLegacy->pOsInterface;
718 pMhwMiInterface = pRenderHalLegacy->pMhwMiInterface;
719 pMhwRender = pRenderHalLegacy->pMhwRenderInterface;
720 iRemaining = 0;
721 FlushParam = g_cRenderHal_InitMediaStateFlushParams;
722 MOS_ZeroMemory(&CmdBuffer, sizeof(CmdBuffer));
723 pPerfProfiler = pRenderHalLegacy->pPerfProfiler;
724 pOsContext = pOsInterface->pOsContext;
725 pMmioRegisters = pMhwRender->GetMmioRegisters();
726
727 // Allocate all available space, unused buffer will be returned later
728 VPHAL_RENDER_CHK_STATUS(pOsInterface->pfnGetCommandBuffer(pOsInterface, &CmdBuffer, 0));
729
730 // Set initial state
731 iRemaining = CmdBuffer.iRemaining;
732
733 VPHAL_RENDER_CHK_STATUS(VpHal_RndrCommonSetPowerMode(
734 pRenderHalLegacy,
735 KernelID));
736
737 #ifndef EMUL
738 if (bLastSubmission && pOsInterface->bEnableKmdMediaFrameTracking)
739 {
740 // Get GPU Status buffer
741 VPHAL_RENDER_CHK_STATUS(pOsInterface->pfnGetGpuStatusBufferResource(pOsInterface, gpuStatusBuffer));
742 VPHAL_RENDER_CHK_NULL(gpuStatusBuffer);
743
744 // Register the buffer
745 VPHAL_RENDER_CHK_STATUS(pOsInterface->pfnRegisterResource(pOsInterface, gpuStatusBuffer, true, true));
746
747 GenericPrologParams.bEnableMediaFrameTracking = true;
748 GenericPrologParams.presMediaFrameTrackingSurface = gpuStatusBuffer;
749 GenericPrologParams.dwMediaFrameTrackingTag = pOsInterface->pfnGetGpuStatusTag(pOsInterface, pOsInterface->CurrentGpuContextOrdinal);
750 GenericPrologParams.dwMediaFrameTrackingAddrOffset = pOsInterface->pfnGetGpuStatusTagOffset(pOsInterface, pOsInterface->CurrentGpuContextOrdinal);
751
752 // Increment GPU Status Tag
753 pOsInterface->pfnIncrementGpuStatusTag(pOsInterface, pOsInterface->CurrentGpuContextOrdinal);
754 }
755 #endif
756
757 HalOcaInterface::On1stLevelBBStart(CmdBuffer, *pOsContext, pOsInterface->CurrentGpuContextHandle,
758 *pRenderHalLegacy->pMhwMiInterface, *pMmioRegisters);
759
760 // Add kernel info to log.
761 HalOcaInterface::DumpVpKernelInfo(CmdBuffer, (MOS_CONTEXT_HANDLE)pOsContext, KernelID, FcKernelCount, FcKernelList);
762 // Add vphal param to log.
763 HalOcaInterface::DumpVphalParam(CmdBuffer, (MOS_CONTEXT_HANDLE)pOsContext, pRenderHalLegacy->pVphalOcaDumper);
764
765 // Initialize command buffer and insert prolog
766 VPHAL_RENDER_CHK_STATUS(pRenderHalLegacy->pfnInitCommandBuffer(pRenderHalLegacy, &CmdBuffer, &GenericPrologParams));
767
768 VPHAL_RENDER_CHK_STATUS(pPerfProfiler->AddPerfCollectStartCmd((void*)pRenderHalLegacy, pOsInterface, pMhwMiInterface, &CmdBuffer));
769
770 VPHAL_RENDER_CHK_STATUS(NullHW::StartPredicate(pOsInterface, pRenderHalLegacy->pMhwMiInterface, &CmdBuffer));
771
772 // Write timing data for 3P budget
773 VPHAL_RENDER_CHK_STATUS(pRenderHalLegacy->pfnSendTimingData(pRenderHalLegacy, &CmdBuffer, true));
774
775 bEnableSLM = (pGpGpuWalkerParams && pGpGpuWalkerParams->SLMSize > 0)? true : false;
776 VPHAL_RENDER_CHK_STATUS(pRenderHalLegacy->pfnSetCacheOverrideParams(
777 pRenderHalLegacy,
778 &pRenderHalLegacy->L3CacheSettings,
779 bEnableSLM));
780
781 if (pRenderHalLegacy->bCmfcCoeffUpdate)
782 {
783 VPHAL_RENDER_CHK_STATUS(pRenderHalLegacy->pfnSendCscCoeffSurface(pRenderHalLegacy,
784 &CmdBuffer,
785 pRenderHalLegacy->pCmfcCoeffSurface,
786 pRenderHalLegacy->pStateHeap->pKernelAllocation[pRenderHalLegacy->iKernelAllocationID].pKernelEntry));
787 }
788
789 // Flush media states
790 VPHAL_RENDER_CHK_STATUS(pRenderHalLegacy->pfnSendMediaStates(
791 pRenderHalLegacy,
792 &CmdBuffer,
793 pWalkerParams,
794 pGpGpuWalkerParams));
795
796 if (pBatchBuffer)
797 {
798 // Register batch buffer for rendering
799 VPHAL_RENDER_CHK_STATUS(pOsInterface->pfnRegisterResource(
800 pOsInterface,
801 &pBatchBuffer->OsResource,
802 false,
803 true));
804
805 HalOcaInterface::OnSubLevelBBStart(CmdBuffer, (MOS_CONTEXT_HANDLE)pOsContext, &pBatchBuffer->OsResource, 0, true, 0);
806
807 // Send Start 2nd level batch buffer command (HW/OS dependent)
808 VPHAL_RENDER_CHK_STATUS(pMhwMiInterface->AddMiBatchBufferStartCmd(
809 &CmdBuffer,
810 pBatchBuffer));
811 }
812
813 // Write back GPU Status tag
814 if (!pOsInterface->bEnableKmdMediaFrameTracking)
815 {
816 VPHAL_RENDER_CHK_STATUS(pRenderHalLegacy->pfnSendRcsStatusTag(pRenderHalLegacy, &CmdBuffer));
817 }
818
819 VPHAL_RENDER_CHK_STATUS(NullHW::StopPredicate(pOsInterface, pRenderHalLegacy->pMhwMiInterface, &CmdBuffer));
820
821 VPHAL_RENDER_CHK_STATUS(pPerfProfiler->AddPerfCollectEndCmd((void*)pRenderHalLegacy, pOsInterface, pMhwMiInterface, &CmdBuffer));
822
823 // Write timing data for 3P budget
824 VPHAL_RENDER_CHK_STATUS(pRenderHalLegacy->pfnSendTimingData(pRenderHalLegacy, &CmdBuffer, false));
825
826 if (GFX_IS_GEN_9_OR_LATER(pRenderHalLegacy->Platform))
827 {
828 MHW_PIPE_CONTROL_PARAMS PipeControlParams;
829
830 MOS_ZeroMemory(&PipeControlParams, sizeof(PipeControlParams));
831 PipeControlParams.dwFlushMode = MHW_FLUSH_WRITE_CACHE;
832 PipeControlParams.bGenericMediaStateClear = true;
833 PipeControlParams.bIndirectStatePointersDisable = true;
834 PipeControlParams.bDisableCSStall = false;
835 VPHAL_RENDER_CHK_STATUS(pMhwMiInterface->AddPipeControl(&CmdBuffer, nullptr, &PipeControlParams));
836
837 if (MEDIA_IS_WA(pRenderHalLegacy->pWaTable, WaSendDummyVFEafterPipelineSelect))
838 {
839 MHW_VFE_PARAMS VfeStateParams = {};
840 VfeStateParams.dwNumberofURBEntries = 1;
841 VPHAL_RENDER_CHK_STATUS(pMhwRender->AddMediaVfeCmd(&CmdBuffer, &VfeStateParams));
842 }
843 }
844
845 if (GFX_IS_GEN_8_OR_LATER(pRenderHalLegacy->Platform))
846 {
847 // Add media flush command in case HW not cleaning the media state
848 if (MEDIA_IS_WA(pRenderHalLegacy->pWaTable, WaMSFWithNoWatermarkTSGHang))
849 {
850 FlushParam.bFlushToGo = true;
851 if (pWalkerParams)
852 {
853 FlushParam.ui8InterfaceDescriptorOffset = pWalkerParams->InterfaceDescriptorOffset;
854 }
855 else
856 {
857 VPHAL_RENDER_ASSERTMESSAGE("ERROR, pWalkerParams is nullptr and cannot get InterfaceDescriptorOffset.");
858 }
859 VPHAL_RENDER_CHK_STATUS(pMhwMiInterface->AddMediaStateFlush(&CmdBuffer, nullptr, &FlushParam));
860 }
861 else if (MEDIA_IS_WA(pRenderHalLegacy->pWaTable, WaAddMediaStateFlushCmd))
862 {
863 VPHAL_RENDER_CHK_STATUS(pMhwMiInterface->AddMediaStateFlush(&CmdBuffer, nullptr, &FlushParam));
864 }
865 }
866
867 HalOcaInterface::On1stLevelBBEnd(CmdBuffer, *pOsInterface);
868
869 if (pBatchBuffer)
870 {
871 // Send Batch Buffer end command (HW/OS dependent)
872 VPHAL_RENDER_CHK_STATUS(pMhwMiInterface->AddMiBatchBufferEnd(&CmdBuffer, nullptr));
873 }
874 else if (VpHal_RndrCommonIsMiBBEndNeeded(pOsInterface))
875 {
876 // Send Batch Buffer end command for 1st level Batch Buffer
877 VPHAL_RENDER_CHK_STATUS(pMhwMiInterface->AddMiBatchBufferEnd(&CmdBuffer, nullptr));
878 }
879 else if (GFX_IS_GEN_8_OR_LATER(pRenderHalLegacy->Platform) &&
880 Mos_Solo_IsInUse(pOsInterface) &&
881 pRenderHalLegacy->pOsInterface->bNoParsingAssistanceInKmd)
882 {
883 VPHAL_RENDER_CHK_STATUS(pMhwMiInterface->AddMiBatchBufferEnd(&CmdBuffer, nullptr));
884 }
885
886 // Return unused command buffer space to OS
887 pOsInterface->pfnReturnCommandBuffer(pOsInterface, &CmdBuffer, 0);
888
889 // VPHAL_DBG_STATE_DUMPPER_DUMP_COMMAND_BUFFER(pRenderHal, &CmdBuffer);
890
891 #if (_DEBUG || _RELEASE_INTERNAL)
892 if (pStatusTableUpdateParams->bTriggerGPUHang == true)
893 {
894 // Set the GPU HANG Trigger flag here
895 pOsInterface->bTriggerVPHang = true;
896 pStatusTableUpdateParams->bTriggerGPUHang = false;
897 }
898 #endif
899
900 // Submit command buffer
901 VPHAL_RENDER_CHK_STATUS(pOsInterface->pfnSubmitCommandBuffer(pOsInterface, &CmdBuffer, bNullRendering));
902
903 if (bNullRendering == false)
904 {
905 dwSyncTag = pRenderHalLegacy->pStateHeap->dwNextTag++;
906
907 // Set media state and batch buffer as busy
908 pRenderHalLegacy->pStateHeap->pCurMediaState->bBusy = true;
909 if (pBatchBuffer)
910 {
911 pBatchBuffer->bBusy = true;
912 pBatchBuffer->dwSyncTag = dwSyncTag;
913 }
914 }
915
916 eStatus = MOS_STATUS_SUCCESS;
917
918 finish:
919
920 if (pStatusTableUpdateParams && pOsInterface)
921 {
922 VpHal_RndrUpdateStatusTableAfterSubmit(pOsInterface, pStatusTableUpdateParams, pOsInterface->CurrentGpuContextOrdinal, eStatus);
923 }
924
925 // Failed -> discard all changes in Command Buffer
926 if (eStatus != MOS_STATUS_SUCCESS)
927 {
928 // Buffer overflow - display overflow size
929 if (CmdBuffer.iRemaining < 0)
930 {
931 VPHAL_RENDER_ASSERTMESSAGE("Command Buffer overflow by %d bytes", -CmdBuffer.iRemaining);
932 }
933
934 // Move command buffer back to beginning
935 i = iRemaining - CmdBuffer.iRemaining;
936 CmdBuffer.iRemaining = iRemaining;
937 CmdBuffer.iOffset -= i;
938 CmdBuffer.pCmdPtr =
939 CmdBuffer.pCmdBase + CmdBuffer.iOffset / sizeof(uint32_t);
940
941 // Return unused command buffer space to OS
942 if (pOsInterface)
943 {
944 pOsInterface->pfnReturnCommandBuffer(pOsInterface, &CmdBuffer, 0);
945 }
946 }
947
948 return eStatus;
949 }
950
951 //!
952 //! \brief Initialized RenderHal Surface according to incoming VPHAL Surface
953 //! \param [in] pVpSurface
954 //! Pointer to the VPHAL surface
955 //! \param [out] pRenderHalSurface
956 //! Pointer to the RenderHal surface
957 //! \return MOS_STATUS
958 //!
VpHal_RndrCommonInitRenderHalSurface(PVPHAL_SURFACE pVpSurface,PRENDERHAL_SURFACE pRenderHalSurface)959 MOS_STATUS VpHal_RndrCommonInitRenderHalSurface(
960 PVPHAL_SURFACE pVpSurface,
961 PRENDERHAL_SURFACE pRenderHalSurface)
962 {
963 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
964
965 //---------------------------------------
966 VPHAL_RENDER_CHK_NULL(pVpSurface);
967 VPHAL_RENDER_CHK_NULL(pRenderHalSurface);
968 //---------------------------------------
969
970 MOS_ZeroMemory(pRenderHalSurface, sizeof(*pRenderHalSurface));
971
972 pRenderHalSurface->OsSurface.OsResource = pVpSurface->OsResource;
973 pRenderHalSurface->OsSurface.dwWidth = pVpSurface->dwWidth;
974 pRenderHalSurface->OsSurface.dwHeight = pVpSurface->dwHeight;
975 pRenderHalSurface->OsSurface.dwPitch = pVpSurface->dwPitch;
976 pRenderHalSurface->OsSurface.dwYPitch = pVpSurface->dwYPitch;
977 pRenderHalSurface->OsSurface.dwUPitch = pVpSurface->dwUPitch;
978 pRenderHalSurface->OsSurface.dwVPitch = pVpSurface->dwVPitch;
979 pRenderHalSurface->OsSurface.Format = pVpSurface->Format;
980 pRenderHalSurface->OsSurface.TileType = pVpSurface->TileType;
981 pRenderHalSurface->OsSurface.TileModeGMM = pVpSurface->TileModeGMM;
982 pRenderHalSurface->OsSurface.bGMMTileEnabled = pVpSurface->bGMMTileEnabled;
983 pRenderHalSurface->OsSurface.dwOffset = pVpSurface->dwOffset;
984 pRenderHalSurface->OsSurface.bIsCompressed = pVpSurface->bIsCompressed;
985 pRenderHalSurface->OsSurface.bCompressible = pVpSurface->bCompressible;
986 pRenderHalSurface->OsSurface.CompressionMode = pVpSurface->CompressionMode;
987 pRenderHalSurface->OsSurface.dwDepth = pVpSurface->dwDepth;
988 pRenderHalSurface->OsSurface.dwQPitch = pVpSurface->dwHeight;
989 pRenderHalSurface->OsSurface.MmcState = (MOS_MEMCOMP_STATE)pVpSurface->CompressionMode;
990 pRenderHalSurface->OsSurface.CompressionFormat = pVpSurface->CompressionFormat;
991
992 VpHal_RndrInitPlaneOffset(
993 &pRenderHalSurface->OsSurface.YPlaneOffset,
994 &pVpSurface->YPlaneOffset);
995 VpHal_RndrInitPlaneOffset(
996 &pRenderHalSurface->OsSurface.UPlaneOffset,
997 &pVpSurface->UPlaneOffset);
998 VpHal_RndrInitPlaneOffset(
999 &pRenderHalSurface->OsSurface.VPlaneOffset,
1000 &pVpSurface->VPlaneOffset);
1001
1002 pRenderHalSurface->rcSrc = pVpSurface->rcSrc;
1003 pRenderHalSurface->rcDst = pVpSurface->rcDst;
1004 pRenderHalSurface->rcMaxSrc = pVpSurface->rcMaxSrc;
1005 pRenderHalSurface->SurfType =
1006 VpHal_RndrInitRenderHalSurfType(pVpSurface->SurfType);
1007 pRenderHalSurface->ScalingMode =
1008 VpHal_RndrInitRenderHalScalingMode(pVpSurface->ScalingMode);
1009 pRenderHalSurface->ChromaSiting = pVpSurface->ChromaSiting;
1010
1011 if (pVpSurface->pDeinterlaceParams != nullptr)
1012 {
1013 pRenderHalSurface->bDeinterlaceEnable = true;
1014 }
1015 else
1016 {
1017 pRenderHalSurface->bDeinterlaceEnable = false;
1018 }
1019
1020 pRenderHalSurface->iPaletteID = pVpSurface->iPalette;
1021
1022 pRenderHalSurface->bQueryVariance = pVpSurface->bQueryVariance;
1023 pRenderHalSurface->bInterlacedScaling = pVpSurface->bInterlacedScaling;
1024 pRenderHalSurface->pDeinterlaceParams = (void *)pVpSurface->pDeinterlaceParams;
1025 pRenderHalSurface->SampleType =
1026 VpHal_RndrInitRenderHalSampleType(pVpSurface->SampleType);
1027
1028 pRenderHalSurface->Rotation =
1029 VpHal_RndrInitRotationMode(pVpSurface->Rotation);
1030
1031 finish:
1032 return eStatus;
1033 }
1034
1035 //!
1036 //! \brief Get output RenderHal Surface parameters back to VPHAL Surface
1037 //! \param [in] pRenderHalSurface
1038 //! Pointer to the RenderHal surface
1039 //! \param [in,out] pVpSurface
1040 //! Pointer to the VPHAL surface
1041 //! \return MOS_STATUS
1042 //!
VpHal_RndrCommonGetBackVpSurfaceParams(PRENDERHAL_SURFACE pRenderHalSurface,PVPHAL_SURFACE pVpSurface)1043 MOS_STATUS VpHal_RndrCommonGetBackVpSurfaceParams(
1044 PRENDERHAL_SURFACE pRenderHalSurface,
1045 PVPHAL_SURFACE pVpSurface)
1046 {
1047 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1048
1049 //---------------------------------------
1050 VPHAL_RENDER_CHK_NULL(pVpSurface);
1051 VPHAL_RENDER_CHK_NULL(pRenderHalSurface);
1052 //---------------------------------------
1053
1054 // The following params are mostly for b32MWColorFillKern on Gen75/Gen8 only
1055 pVpSurface->dwHeight = pRenderHalSurface->OsSurface.dwHeight;
1056 pVpSurface->dwPitch = pRenderHalSurface->OsSurface.dwPitch;
1057 pVpSurface->Format = pRenderHalSurface->OsSurface.Format;
1058 pVpSurface->dwOffset = pRenderHalSurface->OsSurface.dwOffset;
1059 pVpSurface->YPlaneOffset.iXOffset = pRenderHalSurface->OsSurface.YPlaneOffset.iXOffset;
1060 pVpSurface->YPlaneOffset.iYOffset = pRenderHalSurface->OsSurface.YPlaneOffset.iYOffset;
1061 pVpSurface->UPlaneOffset.iSurfaceOffset = pRenderHalSurface->OsSurface.UPlaneOffset.iSurfaceOffset;
1062 pVpSurface->VPlaneOffset.iSurfaceOffset = pRenderHalSurface->OsSurface.VPlaneOffset.iSurfaceOffset;
1063 pVpSurface->rcDst = pRenderHalSurface->rcDst;
1064
1065 pVpSurface->dwWidth = pRenderHalSurface->OsSurface.dwWidth;
1066 pVpSurface->ScalingMode =
1067 VpHal_RndrGetVpHalScalingMode(pRenderHalSurface->ScalingMode);
1068
1069 finish:
1070 return eStatus;
1071 }
1072
1073 //!
1074 //! \brief Set Surface for HW Access
1075 //! \details Common Function for setting up surface state, if render would
1076 //! use CP HM, need use VpHal_CommonSetSurfaceForHwAccess instead
1077 //! \param [in] pRenderHal
1078 //! Pointer to RenderHal Interface Structure
1079 //! \param [in] pSurface
1080 //! Pointer to Surface
1081 //! \param [in] pSurfaceParams
1082 //! Pointer to RenderHal Surface Params
1083 //! \param [in] iBindingTable
1084 //! Binding Table to bind surface
1085 //! \param [in] iBTEntry
1086 //! Binding Table Entry index
1087 //! \param [in] bWrite
1088 //! Write mode flag
1089 //! \return MOS_STATUS
1090 //! MOS_STATUS_SUCCESS if success. Error code otherwise
1091 //!
VpHal_RndrCommonSetSurfaceForHwAccess(PRENDERHAL_INTERFACE pRenderHal,PVPHAL_SURFACE pSurface,PRENDERHAL_SURFACE_STATE_PARAMS pSurfaceParams,int32_t iBindingTable,int32_t iBTEntry,bool bWrite)1092 MOS_STATUS VpHal_RndrCommonSetSurfaceForHwAccess(
1093 PRENDERHAL_INTERFACE pRenderHal,
1094 PVPHAL_SURFACE pSurface,
1095 PRENDERHAL_SURFACE_STATE_PARAMS pSurfaceParams,
1096 int32_t iBindingTable,
1097 int32_t iBTEntry,
1098 bool bWrite)
1099 {
1100
1101 PMOS_INTERFACE pOsInterface;
1102 PRENDERHAL_SURFACE_STATE_ENTRY pSurfaceEntries[MHW_MAX_SURFACE_PLANES];
1103 int32_t iSurfaceEntries;
1104 RENDERHAL_SURFACE RenderHalSurface;
1105 int32_t i;
1106 MOS_STATUS eStatus;
1107
1108 // Initialize Variables
1109 eStatus = MOS_STATUS_SUCCESS;
1110 pOsInterface = pRenderHal->pOsInterface;
1111
1112 if (pOsInterface->osCpInterface->IsHMEnabled())
1113 {
1114 VPHAL_RENDER_ASSERTMESSAGE("ERROR, need to use VpHal_CommonSetSurfaceForHwAccess if under CP HM.");
1115 }
1116
1117 // Register surfaces for rendering (GfxAddress/Allocation index)
1118 // Register resource
1119 VPHAL_RENDER_CHK_STATUS(pOsInterface->pfnRegisterResource(
1120 pOsInterface,
1121 &pSurface->OsResource,
1122 bWrite,
1123 true));
1124
1125 VPHAL_RENDER_CHK_STATUS(VpHal_RndrCommonInitRenderHalSurface(
1126 pSurface,
1127 &RenderHalSurface));
1128
1129 // Setup surface states-----------------------------------------------------
1130 VPHAL_RENDER_CHK_STATUS(pRenderHal->pfnSetupSurfaceState(
1131 pRenderHal,
1132 &RenderHalSurface,
1133 pSurfaceParams,
1134 &iSurfaceEntries,
1135 pSurfaceEntries,
1136 nullptr));
1137
1138 VPHAL_RENDER_CHK_STATUS(VpHal_RndrCommonGetBackVpSurfaceParams(
1139 &RenderHalSurface,
1140 pSurface));
1141
1142 // Bind surface states------------------------------------------------------
1143 for (i = 0; i < iSurfaceEntries; i++, iBTEntry++)
1144 {
1145 VPHAL_RENDER_CHK_STATUS(pRenderHal->pfnBindSurfaceState(
1146 pRenderHal,
1147 iBindingTable,
1148 iBTEntry,
1149 pSurfaceEntries[i]));
1150 }
1151
1152 finish:
1153 return eStatus;
1154 }
1155
1156 //!
1157 //! \brief Set Buffer Surface for HW Access
1158 //! \details Common Function for setting up buffer surface state, if render would
1159 //! use CP HM, need use VpHal_CommonSetBufferSurfaceForHwAccess instead
1160 //! \param [in] pRenderHal
1161 //! Pointer to RenderHal Interface Structure
1162 //! \param [in] pSurface
1163 //! Pointer to Surface
1164 //! \param [in,out] pSurfaceParams
1165 //! Pointer to RenderHal Surface Params
1166 //! \param [in] iBindingTable
1167 //! Binding Table to Bind Surface
1168 //! \param [in] iBTEntry
1169 //! Binding Table Entry index
1170 //! \param [in] bWrite
1171 //! Write mode flag
1172 //! \return MOS_STATUS
1173 //! MOS_STATUS_SUCCESS if success. Error code otherwise
1174 //!
VpHal_RndrCommonSetBufferSurfaceForHwAccess(PRENDERHAL_INTERFACE pRenderHal,PVPHAL_SURFACE pSurface,PRENDERHAL_SURFACE_STATE_PARAMS pSurfaceParams,int32_t iBindingTable,int32_t iBTEntry,bool bWrite)1175 MOS_STATUS VpHal_RndrCommonSetBufferSurfaceForHwAccess(
1176 PRENDERHAL_INTERFACE pRenderHal,
1177 PVPHAL_SURFACE pSurface,
1178 PRENDERHAL_SURFACE_STATE_PARAMS pSurfaceParams,
1179 int32_t iBindingTable,
1180 int32_t iBTEntry,
1181 bool bWrite)
1182 {
1183 PMOS_INTERFACE pOsInterface;
1184 RENDERHAL_SURFACE RenderHalSurface;
1185 RENDERHAL_SURFACE_STATE_PARAMS SurfaceParam;
1186 PRENDERHAL_SURFACE_STATE_ENTRY pSurfaceEntry;
1187 MOS_STATUS eStatus;
1188
1189 VPHAL_RENDER_CHK_NULL(pRenderHal);
1190 VPHAL_RENDER_CHK_NULL(pRenderHal->pOsInterface);
1191
1192 // Initialize Variables
1193 eStatus = MOS_STATUS_SUCCESS;
1194 pOsInterface = pRenderHal->pOsInterface;
1195
1196 if (pOsInterface->osCpInterface->IsHMEnabled())
1197 {
1198 VPHAL_RENDER_ASSERTMESSAGE("ERROR, need to use VpHal_CommonSetBufferSurfaceForHwAccess if under CP HM.");
1199 }
1200
1201 // Register surfaces for rendering (GfxAddress/Allocation index)
1202 // Register resource
1203 VPHAL_RENDER_CHK_STATUS(pOsInterface->pfnRegisterResource(
1204 pOsInterface,
1205 &pSurface->OsResource,
1206 bWrite,
1207 true));
1208
1209 // Setup Buffer surface-----------------------------------------------------
1210 if (pSurfaceParams == nullptr)
1211 {
1212 MOS_ZeroMemory(&SurfaceParam, sizeof(SurfaceParam));
1213
1214 //set mem object control for cache
1215 SurfaceParam.MemObjCtl = (pRenderHal->pOsInterface->pfnCachePolicyGetMemoryObject(
1216 MOS_MP_RESOURCE_USAGE_DEFAULT,
1217 pRenderHal->pOsInterface->pfnGetGmmClientContext(pRenderHal->pOsInterface))).DwordValue;
1218
1219 pSurfaceParams = &SurfaceParam;
1220 }
1221
1222 VPHAL_RENDER_CHK_STATUS(VpHal_RndrCommonInitRenderHalSurface(
1223 pSurface,
1224 &RenderHalSurface));
1225
1226 VPHAL_RENDER_CHK_STATUS(pRenderHal->pfnSetupBufferSurfaceState(
1227 pRenderHal,
1228 &RenderHalSurface,
1229 pSurfaceParams,
1230 &pSurfaceEntry));
1231
1232 // Bind surface state-------------------------------------------------------
1233 VPHAL_RENDER_CHK_STATUS(pRenderHal->pfnBindSurfaceState(
1234 pRenderHal,
1235 iBindingTable,
1236 iBTEntry,
1237 pSurfaceEntry));
1238
1239 finish:
1240 return eStatus;
1241 }
1242
1243 //!
1244 //! \brief Set Surface for HW Access for CP HM
1245 //! \details Common Function for setting up surface state, need to use this function
1246 //! if render would use CP HM
1247 //! \param [in] pRenderHal
1248 //! Pointer to RenderHal Interface Structure
1249 //! \param [in] pSurface
1250 //! Pointer to Surface
1251 //! \param [in] pRenderSurface
1252 //! Pointer to Render Surface
1253 //! \param [in] pSurfaceParams
1254 //! Pointer to RenderHal Surface Params
1255 //! \param [in] iBindingTable
1256 //! Binding Table to bind surface
1257 //! \param [in] iBTEntry
1258 //! Binding Table Entry index
1259 //! \param [in] bWrite
1260 //! Write mode flag
1261 //! \return MOS_STATUS
1262 //! MOS_STATUS_SUCCESS if success. Error code otherwise
1263 //!
VpHal_CommonSetSurfaceForHwAccess(PRENDERHAL_INTERFACE pRenderHal,PVPHAL_SURFACE pSurface,PRENDERHAL_SURFACE pRenderSurface,PRENDERHAL_SURFACE_STATE_PARAMS pSurfaceParams,int32_t iBindingTable,int32_t iBTEntry,bool bWrite)1264 MOS_STATUS VpHal_CommonSetSurfaceForHwAccess(
1265 PRENDERHAL_INTERFACE pRenderHal,
1266 PVPHAL_SURFACE pSurface,
1267 PRENDERHAL_SURFACE pRenderSurface,
1268 PRENDERHAL_SURFACE_STATE_PARAMS pSurfaceParams,
1269 int32_t iBindingTable,
1270 int32_t iBTEntry,
1271 bool bWrite)
1272 {
1273
1274 PMOS_INTERFACE pOsInterface;
1275 PRENDERHAL_SURFACE_STATE_ENTRY pSurfaceEntries[MHW_MAX_SURFACE_PLANES];
1276 int32_t iSurfaceEntries;
1277 int32_t i;
1278 MOS_STATUS eStatus;
1279
1280 // Initialize Variables
1281 eStatus = MOS_STATUS_SUCCESS;
1282 pOsInterface = pRenderHal->pOsInterface;
1283
1284 // Register surfaces for rendering (GfxAddress/Allocation index)
1285 // Register resource
1286 VPHAL_RENDER_CHK_STATUS(pOsInterface->pfnRegisterResource(
1287 pOsInterface,
1288 &pSurface->OsResource,
1289 bWrite,
1290 true));
1291
1292 VPHAL_RENDER_CHK_STATUS(VpHal_RndrCommonInitRenderHalSurface(
1293 pSurface,
1294 pRenderSurface));
1295
1296 // Setup surface states-----------------------------------------------------
1297 VPHAL_RENDER_CHK_STATUS(pRenderHal->pfnSetupSurfaceState(
1298 pRenderHal,
1299 pRenderSurface,
1300 pSurfaceParams,
1301 &iSurfaceEntries,
1302 pSurfaceEntries,
1303 nullptr));
1304
1305 VPHAL_RENDER_CHK_STATUS(VpHal_RndrCommonGetBackVpSurfaceParams(
1306 pRenderSurface,
1307 pSurface));
1308
1309 // Bind surface states------------------------------------------------------
1310 for (i = 0; i < iSurfaceEntries; i++, iBTEntry++)
1311 {
1312 VPHAL_RENDER_CHK_STATUS(pRenderHal->pfnBindSurfaceState(
1313 pRenderHal,
1314 iBindingTable,
1315 iBTEntry,
1316 pSurfaceEntries[i]));
1317 }
1318
1319 finish:
1320 return eStatus;
1321 }
1322
1323 //!
1324 //! \brief Set Buffer Surface for HW Access for CP HM
1325 //! \details Common Function for setting up buffer surface state, need to use this function
1326 //! if render would use CP HM
1327 //! \param [in] pRenderHal
1328 //! Pointer to RenderHal Interface Structure
1329 //! \param [in] pSurface
1330 //! Pointer to Surface
1331 //! \param [in] pRenderSurface
1332 //! Pointer to Render Surface
1333 //! \param [in,out] pSurfaceParams
1334 //! Pointer to RenderHal Surface Params
1335 //! \param [in] iBindingTable
1336 //! Binding Table to Bind Surface
1337 //! \param [in] iBTEntry
1338 //! Binding Table Entry index
1339 //! \param [in] bWrite
1340 //! Write mode flag
1341 //! \return MOS_STATUS
1342 //! MOS_STATUS_SUCCESS if success. Error code otherwise
1343 //!
VpHal_CommonSetBufferSurfaceForHwAccess(PRENDERHAL_INTERFACE pRenderHal,PVPHAL_SURFACE pSurface,PRENDERHAL_SURFACE pRenderSurface,PRENDERHAL_SURFACE_STATE_PARAMS pSurfaceParams,int32_t iBindingTable,int32_t iBTEntry,bool bWrite)1344 MOS_STATUS VpHal_CommonSetBufferSurfaceForHwAccess(
1345 PRENDERHAL_INTERFACE pRenderHal,
1346 PVPHAL_SURFACE pSurface,
1347 PRENDERHAL_SURFACE pRenderSurface,
1348 PRENDERHAL_SURFACE_STATE_PARAMS pSurfaceParams,
1349 int32_t iBindingTable,
1350 int32_t iBTEntry,
1351 bool bWrite)
1352 {
1353 PMOS_INTERFACE pOsInterface;
1354 RENDERHAL_SURFACE_STATE_PARAMS SurfaceParam;
1355 PRENDERHAL_SURFACE_STATE_ENTRY pSurfaceEntry;
1356 MOS_STATUS eStatus;
1357
1358 VPHAL_RENDER_CHK_NULL(pRenderHal);
1359 VPHAL_RENDER_CHK_NULL(pRenderHal->pOsInterface);
1360
1361 // Initialize Variables
1362 eStatus = MOS_STATUS_SUCCESS;
1363 pOsInterface = pRenderHal->pOsInterface;
1364
1365 // Register surfaces for rendering (GfxAddress/Allocation index)
1366 // Register resource
1367 VPHAL_RENDER_CHK_STATUS(pOsInterface->pfnRegisterResource(
1368 pOsInterface,
1369 &pSurface->OsResource,
1370 bWrite,
1371 true));
1372
1373 // Setup Buffer surface-----------------------------------------------------
1374 if (pSurfaceParams == nullptr)
1375 {
1376 MOS_ZeroMemory(&SurfaceParam, sizeof(SurfaceParam));
1377
1378 //set mem object control for cache
1379 SurfaceParam.MemObjCtl = (pRenderHal->pOsInterface->pfnCachePolicyGetMemoryObject(
1380 MOS_MP_RESOURCE_USAGE_DEFAULT,
1381 pRenderHal->pOsInterface->pfnGetGmmClientContext(pRenderHal->pOsInterface))).DwordValue;
1382
1383 pSurfaceParams = &SurfaceParam;
1384 }
1385
1386 VPHAL_RENDER_CHK_STATUS(VpHal_RndrCommonInitRenderHalSurface(
1387 pSurface,
1388 pRenderSurface));
1389
1390 VPHAL_RENDER_CHK_STATUS(pRenderHal->pfnSetupBufferSurfaceState(
1391 pRenderHal,
1392 pRenderSurface,
1393 pSurfaceParams,
1394 &pSurfaceEntry));
1395
1396 // Bind surface state-------------------------------------------------------
1397 VPHAL_RENDER_CHK_STATUS(pRenderHal->pfnBindSurfaceState(
1398 pRenderHal,
1399 iBindingTable,
1400 iBTEntry,
1401 pSurfaceEntry));
1402
1403 finish:
1404 return eStatus;
1405 }
1406
1407 //!
1408 //! \brief Is Alignment WA needed
1409 //! \details Decide WA is needed for VEBOX/Render engine
1410 //! RENDER limitation with composition BOB:
1411 //! Height should be a multiple of 4, otherwise disable DI in Comp
1412 //! VEBOX limitation with TiledY NV12 input(Gen75):
1413 //! Height should be a multiple of 4, otherwise bypass adv render
1414 //! VEBOX limitation with TiledY NV12 input(Gen8/9):
1415 //! 3D/GMM regresses to allocate linear surface when height is not
1416 //! a multiple of 4, no need to bypass adv render
1417 //! \param [in] pSurface
1418 //! Input surface
1419 //! \param [in] GpuContext
1420 //! GpuContext to indicate Render/Vebox
1421 //! \return bool
1422 //! true - Solution is needed; false - Solution is not needed
1423 //!
VpHal_RndrCommonIsAlignmentWANeeded(PVPHAL_SURFACE pSurface,MOS_GPU_CONTEXT GpuContext)1424 bool VpHal_RndrCommonIsAlignmentWANeeded(
1425 PVPHAL_SURFACE pSurface,
1426 MOS_GPU_CONTEXT GpuContext)
1427 {
1428 bool bRetVal;
1429
1430 switch (GpuContext)
1431 {
1432 case MOS_GPU_CONTEXT_RENDER:
1433 case MOS_GPU_CONTEXT_VEBOX:
1434 case MOS_GPU_CONTEXT_RENDER3:
1435 case MOS_GPU_CONTEXT_RENDER4:
1436 case MOS_GPU_CONTEXT_COMPUTE:
1437 case MOS_GPU_CONTEXT_COMPUTE_RA:
1438 case MOS_GPU_CONTEXT_RENDER_RA:
1439 if (!(MOS_IS_ALIGNED(MOS_MIN((uint32_t)pSurface->dwHeight, (uint32_t)pSurface->rcMaxSrc.bottom), 4)) &&
1440 (pSurface->Format == Format_NV12))
1441 {
1442 bRetVal = true;
1443 }
1444 else
1445 {
1446 bRetVal = false;
1447 }
1448 break;
1449
1450 default:
1451 VPHAL_RENDER_ASSERTMESSAGE("Incorrect GPU context: %d.", GpuContext);
1452 bRetVal = false;
1453 break;
1454 }
1455
1456 return bRetVal;
1457 }
1458
1459 //!
1460 //! \brief Sets AVS table
1461 //! \details Set 4-tap or 8-tap filtering AVS table
1462 //! \param [in] pAvsParams
1463 //! Pointer to avs parameter
1464 //! \param [in,out] pMhwSamplerAvsTableParam
1465 //! Pointer to avs table parameter
1466 //! \return MOS_STATUS
1467 //!
VpHal_RenderCommonSetAVSTableParam(PMHW_AVS_PARAMS pAvsParams,PMHW_SAMPLER_AVS_TABLE_PARAM pMhwSamplerAvsTableParam)1468 MOS_STATUS VpHal_RenderCommonSetAVSTableParam(
1469 PMHW_AVS_PARAMS pAvsParams,
1470 PMHW_SAMPLER_AVS_TABLE_PARAM pMhwSamplerAvsTableParam)
1471 {
1472 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1473 int32_t iCoeffTableIdx;
1474 int32_t iFilterCoeffIdx;
1475 int32_t* piYCoefsX;
1476 int32_t* piYCoefsY;
1477 int32_t* piUVCoefsX;
1478 int32_t* piUVCoefsY;
1479
1480 VPHAL_RENDER_CHK_NULL(pAvsParams);
1481 VPHAL_RENDER_CHK_NULL(pMhwSamplerAvsTableParam);
1482 VPHAL_RENDER_CHK_NULL(pAvsParams->piYCoefsX);
1483 VPHAL_RENDER_CHK_NULL(pAvsParams->piYCoefsY);
1484 VPHAL_RENDER_CHK_NULL(pAvsParams->piUVCoefsX);
1485 VPHAL_RENDER_CHK_NULL(pAvsParams->piUVCoefsY);
1486
1487 piYCoefsX = pAvsParams->piYCoefsX;
1488 piYCoefsY = pAvsParams->piYCoefsY;
1489 piUVCoefsX = pAvsParams->piUVCoefsX;
1490 piUVCoefsY = pAvsParams->piUVCoefsY;
1491
1492 for (iCoeffTableIdx = 0; iCoeffTableIdx < MHW_NUM_HW_POLYPHASE_TABLES; iCoeffTableIdx++)
1493 {
1494 PMHW_AVS_COEFFICIENT_PARAM pCoeffTable = &pMhwSamplerAvsTableParam->paMhwAvsCoeffParam[iCoeffTableIdx];
1495 // 4-tap filtering for G-channel, update only center 4 coeffs.
1496 if (pMhwSamplerAvsTableParam->b4TapGY)
1497 {
1498 pCoeffTable->ZeroXFilterCoefficient[0] = 0;
1499 pCoeffTable->ZeroXFilterCoefficient[1] = 0;
1500 pCoeffTable->ZeroXFilterCoefficient[2] = (int8_t)*(piYCoefsX++);
1501 pCoeffTable->ZeroXFilterCoefficient[3] = (int8_t)*(piYCoefsX++);
1502 pCoeffTable->ZeroXFilterCoefficient[4] = (int8_t)*(piYCoefsX++);
1503 pCoeffTable->ZeroXFilterCoefficient[5] = (int8_t)*(piYCoefsX++);
1504 pCoeffTable->ZeroXFilterCoefficient[6] = 0;
1505 pCoeffTable->ZeroXFilterCoefficient[7] = 0;
1506
1507 pCoeffTable->ZeroYFilterCoefficient[0] = 0;
1508 pCoeffTable->ZeroYFilterCoefficient[1] = 0;
1509 pCoeffTable->ZeroYFilterCoefficient[2] = (int8_t)*(piYCoefsY++);
1510 pCoeffTable->ZeroYFilterCoefficient[3] = (int8_t)*(piYCoefsY++);
1511 pCoeffTable->ZeroYFilterCoefficient[4] = (int8_t)*(piYCoefsY++);
1512 pCoeffTable->ZeroYFilterCoefficient[5] = (int8_t)*(piYCoefsY++);
1513 pCoeffTable->ZeroYFilterCoefficient[6] = 0;
1514 pCoeffTable->ZeroYFilterCoefficient[7] = 0;
1515 }
1516 else // for gen8+, using 8-tap filter
1517 {
1518 for (iFilterCoeffIdx = 0; iFilterCoeffIdx < 8; iFilterCoeffIdx++)
1519 {
1520 pCoeffTable->ZeroXFilterCoefficient[iFilterCoeffIdx] = (int8_t)*(piYCoefsX++);
1521 pCoeffTable->ZeroYFilterCoefficient[iFilterCoeffIdx] = (int8_t)*(piYCoefsY++);
1522 }
1523 }
1524
1525 // If 8-tap adaptive filter is enabled, then UV/RB will share the same coefficients with Y/G
1526 if (pMhwSamplerAvsTableParam->b4TapRBUV)
1527 {
1528 // [0..3] maps to filter coefficients [2..5], in actual table [0..1] are reserved
1529 for (iFilterCoeffIdx = 0; iFilterCoeffIdx < 4; iFilterCoeffIdx++)
1530 {
1531 pCoeffTable->OneXFilterCoefficient[iFilterCoeffIdx] = (int8_t)*(piUVCoefsX++);
1532 pCoeffTable->OneYFilterCoefficient[iFilterCoeffIdx] = (int8_t)*(piUVCoefsY++);
1533 }
1534 }
1535 }
1536
1537 if (pMhwSamplerAvsTableParam->bIsCoeffExtraEnabled)
1538 {
1539 for (iCoeffTableIdx = 0; iCoeffTableIdx < MHW_NUM_HW_POLYPHASE_EXTRA_TABLES_G9; iCoeffTableIdx++)
1540 {
1541 PMHW_AVS_COEFFICIENT_PARAM pCoeffTable = &pMhwSamplerAvsTableParam->paMhwAvsCoeffParamExtra[iCoeffTableIdx];
1542 // 4-tap filtering for G-channel, update only center 4 coeffs.
1543 if (pMhwSamplerAvsTableParam->b4TapGY)
1544 {
1545 pCoeffTable->ZeroXFilterCoefficient[0] = 0;
1546 pCoeffTable->ZeroXFilterCoefficient[1] = 0;
1547 pCoeffTable->ZeroXFilterCoefficient[2] = (int8_t)*(piYCoefsX++);
1548 pCoeffTable->ZeroXFilterCoefficient[3] = (int8_t)*(piYCoefsX++);
1549 pCoeffTable->ZeroXFilterCoefficient[4] = (int8_t)*(piYCoefsX++);
1550 pCoeffTable->ZeroXFilterCoefficient[5] = (int8_t)*(piYCoefsX++);
1551 pCoeffTable->ZeroXFilterCoefficient[6] = 0;
1552 pCoeffTable->ZeroXFilterCoefficient[7] = 0;
1553
1554 pCoeffTable->ZeroYFilterCoefficient[0] = 0;
1555 pCoeffTable->ZeroYFilterCoefficient[1] = 0;
1556 pCoeffTable->ZeroYFilterCoefficient[2] = (int8_t)*(piYCoefsY++);
1557 pCoeffTable->ZeroYFilterCoefficient[3] = (int8_t)*(piYCoefsY++);
1558 pCoeffTable->ZeroYFilterCoefficient[4] = (int8_t)*(piYCoefsY++);
1559 pCoeffTable->ZeroYFilterCoefficient[5] = (int8_t)*(piYCoefsY++);
1560 pCoeffTable->ZeroYFilterCoefficient[6] = 0;
1561 pCoeffTable->ZeroYFilterCoefficient[7] = 0;
1562 }
1563 else
1564 {
1565 for (iFilterCoeffIdx = 0; iFilterCoeffIdx < 8; iFilterCoeffIdx++)
1566 {
1567 pCoeffTable->ZeroXFilterCoefficient[iFilterCoeffIdx] = (int8_t)*(piYCoefsX++);
1568 pCoeffTable->ZeroYFilterCoefficient[iFilterCoeffIdx] = (int8_t)*(piYCoefsY++);
1569 }
1570 }
1571
1572 // If 8-tap adaptive filter is enabled, then UV/RB will share the same coefficients with Y/G
1573 if (pMhwSamplerAvsTableParam->b4TapRBUV)
1574 {
1575 for (iFilterCoeffIdx = 0; iFilterCoeffIdx < 4; iFilterCoeffIdx++)
1576 {
1577 // [0..3] maps to filter coefficients [2..5], in actual table [0..1] are reserved
1578 pCoeffTable->OneXFilterCoefficient[iFilterCoeffIdx] = (int8_t)*(piUVCoefsX++);
1579 pCoeffTable->OneYFilterCoefficient[iFilterCoeffIdx] = (int8_t)*(piUVCoefsY++);
1580 }
1581 }
1582 }
1583 }
1584
1585 finish:
1586 return eStatus;
1587 }
1588
1589 //!
1590 //! \brief Initialize AVS parameters shared by Renderers
1591 //! \details Initialize the members of the AVS parameter and allocate memory for its coefficient tables
1592 //! \param [in,out] pAVS_Params
1593 //! Pointer to MHW AVS parameter
1594 //! \param [in] uiYCoeffTableSize
1595 //! Size of the Y coefficient table
1596 //! \param [in] uiUVCoeffTableSize
1597 //! Size of the UV coefficient table
1598 //! \return MOS_STATUS
1599 //! Return MOS_STATUS_SUCCESS if successful, otherwise failed
1600 //!
VpHal_RndrCommonInitAVSParams(PMHW_AVS_PARAMS pAVS_Params,uint32_t uiYCoeffTableSize,uint32_t uiUVCoeffTableSize)1601 MOS_STATUS VpHal_RndrCommonInitAVSParams(
1602 PMHW_AVS_PARAMS pAVS_Params,
1603 uint32_t uiYCoeffTableSize,
1604 uint32_t uiUVCoeffTableSize)
1605 {
1606 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1607 int32_t size;
1608 char* ptr;
1609
1610 VPHAL_RENDER_CHK_NULL(pAVS_Params);
1611 VPHAL_RENDER_CHK_NULL((void*)(uiYCoeffTableSize > 0));
1612 VPHAL_RENDER_CHK_NULL((void*)(uiUVCoeffTableSize > 0));
1613
1614 // Init AVS parameters
1615 pAVS_Params->Format = Format_None;
1616 pAVS_Params->fScaleX = 0.0F;
1617 pAVS_Params->fScaleY = 0.0F;
1618 pAVS_Params->piYCoefsX = nullptr;
1619
1620 // Allocate AVS coefficients, One set each for X and Y
1621 size = (uiYCoeffTableSize + uiUVCoeffTableSize) * 2;
1622
1623 ptr = (char*)MOS_AllocAndZeroMemory(size);
1624 if (ptr == nullptr)
1625 {
1626 VPHAL_RENDER_ASSERTMESSAGE("No memory to allocate AVS coefficient tables.");
1627 eStatus = MOS_STATUS_NO_SPACE;
1628 goto finish;
1629 }
1630
1631 pAVS_Params->piYCoefsX = (int32_t*)ptr;
1632
1633 ptr += uiYCoeffTableSize;
1634 pAVS_Params->piUVCoefsX = (int32_t*)ptr;
1635
1636 ptr += uiUVCoeffTableSize;
1637 pAVS_Params->piYCoefsY = (int32_t*)ptr;
1638
1639 ptr += uiYCoeffTableSize;
1640 pAVS_Params->piUVCoefsY = (int32_t*)ptr;
1641
1642 finish:
1643 return eStatus;
1644 }
1645
1646 //!
1647 //! \brief Destroy AVS parameters shared by Renderers
1648 //! \details Free the memory of AVS parameter's coefficient tables
1649 //! \param [in,out] pAVS_Params
1650 //! Pointer to VPHAL AVS parameter
1651 //! \return void
1652 //!
VpHal_RndrCommonDestroyAVSParams(PMHW_AVS_PARAMS pAVS_Params)1653 void VpHal_RndrCommonDestroyAVSParams(
1654 PMHW_AVS_PARAMS pAVS_Params)
1655 {
1656 VPHAL_RENDER_ASSERT(pAVS_Params);
1657 MOS_SafeFreeMemory(pAVS_Params->piYCoefsX);
1658 pAVS_Params->piYCoefsX = nullptr;
1659 }
1660
1661 //!
1662 //! \brief update status report rely on command buffer sync tag
1663 //! \param [in] pOsInterface
1664 //! pointer to os interface
1665 //! \param [in,out] pStatusTableUpdateParams
1666 //! pointer to STATUS_TABLE_UPDATE_PARAMS for updating status table
1667 //! \param [in] eMosGpuContext
1668 //! current mos contexnt enum
1669 //! \param [in] eLastStatus
1670 //! indicating last submition is successful or not
1671 //! \return MOS_STATUS
1672 //! Return MOS_STATUS_SUCCESS if successful, otherwise failed
1673 //!
VpHal_RndrUpdateStatusTableAfterSubmit(PMOS_INTERFACE pOsInterface,PSTATUS_TABLE_UPDATE_PARAMS pStatusTableUpdateParams,MOS_GPU_CONTEXT eMosGpuContext,MOS_STATUS eLastStatus)1674 MOS_STATUS VpHal_RndrUpdateStatusTableAfterSubmit(
1675 PMOS_INTERFACE pOsInterface,
1676 PSTATUS_TABLE_UPDATE_PARAMS pStatusTableUpdateParams,
1677 MOS_GPU_CONTEXT eMosGpuContext,
1678 MOS_STATUS eLastStatus)
1679 {
1680 PVPHAL_STATUS_ENTRY pStatusEntry;
1681 bool bEmptyTable;
1682 MOS_STATUS eStatus;
1683 uint32_t dwLastTag;
1684 PVPHAL_STATUS_TABLE pStatusTable;
1685 uint32_t dwStatusFeedBackID;
1686
1687 VPHAL_RENDER_CHK_NULL(pStatusTableUpdateParams);
1688 eStatus = MOS_STATUS_SUCCESS;
1689
1690 if (!pStatusTableUpdateParams->bReportStatus ||
1691 !pStatusTableUpdateParams->bSurfIsRenderTarget)
1692 {
1693 goto finish;
1694 }
1695
1696 VPHAL_RENDER_CHK_NULL(pStatusTableUpdateParams->pStatusTable);
1697 VPHAL_RENDER_CHK_NULL(pOsInterface);
1698
1699 pStatusTable = pStatusTableUpdateParams->pStatusTable;
1700 dwStatusFeedBackID = pStatusTableUpdateParams->StatusFeedBackID;
1701
1702 VPHAL_RENDER_ASSERT(pStatusTable->uiHead < VPHAL_STATUS_TABLE_MAX_SIZE);
1703 VPHAL_RENDER_ASSERT(pStatusTable->uiCurrent < VPHAL_STATUS_TABLE_MAX_SIZE);
1704
1705 bEmptyTable = (pStatusTable->uiCurrent == pStatusTable->uiHead);
1706 if (!bEmptyTable)
1707 {
1708 uint32_t uiLast = (pStatusTable->uiCurrent - 1) & (VPHAL_STATUS_TABLE_MAX_SIZE - 1);
1709 bool bSameFrameIdWithLastRender = (pStatusTable->aTableEntries[uiLast].StatusFeedBackID == dwStatusFeedBackID);
1710 if (bSameFrameIdWithLastRender)
1711 {
1712 pStatusTable->uiCurrent = uiLast;
1713 }
1714 }
1715 pStatusEntry = &pStatusTable->aTableEntries[pStatusTable->uiCurrent];
1716 pStatusEntry->StatusFeedBackID = dwStatusFeedBackID;
1717 pStatusEntry->GpuContextOrdinal = eMosGpuContext;
1718 dwLastTag = pOsInterface->pfnGetGpuStatusTag(pOsInterface, eMosGpuContext) - 1;
1719 pStatusEntry->dwTag = dwLastTag;
1720 pStatusEntry->dwStatus = (eLastStatus == MOS_STATUS_SUCCESS)? VPREP_NOTREADY : VPREP_ERROR;
1721 pStatusTable->uiCurrent = (pStatusTable->uiCurrent + 1) & (VPHAL_STATUS_TABLE_MAX_SIZE - 1);
1722
1723 if (pStatusTable->uiCurrent == pStatusTable->uiHead)
1724 {
1725 pStatusTable->uiHead = (pStatusTable->uiHead + 1) & (VPHAL_STATUS_TABLE_MAX_SIZE - 1);
1726 }
1727
1728 // CM may use a different streamIndex, record it here
1729 if (pStatusTableUpdateParams->bUpdateStreamIndex)
1730 {
1731 pStatusEntry->isStreamIndexSet = true;
1732 pStatusEntry->streamIndex = (uint16_t)pOsInterface->streamIndex;
1733 }
1734 else
1735 {
1736 pStatusEntry->isStreamIndexSet = false;
1737 }
1738
1739 finish:
1740 return eStatus;
1741 }
1742