1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility.XSPerfAccumulate 23import xiangshan._ 24import xiangshan.backend.fu.fpu._ 25 26trait HasFuLatency { 27 val latencyVal: Option[Int] 28 val extraLatencyVal: Option[Int] 29 val uncertainLatencyVal: Option[Int] 30 val uncertainEnable: Option[Int] 31} 32 33case class CertainLatency(value: Int, extraValue: Int = 0) extends HasFuLatency { 34 override val latencyVal: Option[Int] = Some(value + extraValue) 35 override val extraLatencyVal: Option[Int] = Some(extraValue) 36 override val uncertainLatencyVal: Option[Int] = None 37 override val uncertainEnable: Option[Int] = None 38} 39 40case class UncertainLatency(value: Option[Int]) extends HasFuLatency { 41 override val latencyVal: Option[Int] = None 42 override val extraLatencyVal: Option[Int] = None 43 override val uncertainLatencyVal: Option[Int] = value 44 override val uncertainEnable: Option[Int] = Some(0) // for gate uncertain fu 45} 46 47object UncertainLatency { 48 def apply(): UncertainLatency = UncertainLatency(None) 49 def apply(value: Int): UncertainLatency = UncertainLatency(Some(value)) 50} 51 52class FuOutput(val len: Int)(implicit p: Parameters) extends XSBundle { 53 val data = UInt(len.W) 54 val uop = new MicroOp 55} 56 57class FunctionUnitInput(val len: Int)(implicit p: Parameters) extends XSBundle { 58 val src = Vec(3, UInt(len.W)) 59 val uop = new MicroOp 60} 61 62class FunctionUnitIO(val len: Int)(implicit p: Parameters) extends XSBundle { 63 val in = Flipped(DecoupledIO(new FunctionUnitInput(len))) 64 65 val out = DecoupledIO(new FuOutput(len)) 66 67 val redirectIn = Flipped(ValidIO(new Redirect)) 68} 69 70abstract class FunctionUnit(len: Int = 64)(implicit p: Parameters) extends XSModule { 71 72 val io = IO(new FunctionUnitIO(len)) 73 74 XSPerfAccumulate("in_valid", io.in.valid) 75 XSPerfAccumulate("in_fire", io.in.fire) 76 XSPerfAccumulate("out_valid", io.out.valid) 77 XSPerfAccumulate("out_fire", io.out.fire) 78 79} 80