1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Support for Intel Camera Imaging ISP subsystem.
4  * Copyright (c) 2015, Intel Corporation.
5  */
6 
7 #include "system_local.h"
8 
9 /* ISP */
10 const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
11 	0x0000000000020000ULL
12 };
13 
14 const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
15 	0x0000000000200000ULL
16 };
17 
18 const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
19 	0x0000000000100000ULL
20 };
21 
22 /* SP */
23 const hrt_address SP_CTRL_BASE[N_SP_ID] = {
24 	0x0000000000010000ULL
25 };
26 
27 const hrt_address SP_DMEM_BASE[N_SP_ID] = {
28 	0x0000000000300000ULL
29 };
30 
31 /* MMU */
32 /*
33  * MMU0_ID: The data MMU
34  * MMU1_ID: The icache MMU
35  */
36 const hrt_address MMU_BASE[N_MMU_ID] = {
37 	0x0000000000070000ULL,
38 	0x00000000000A0000ULL
39 };
40 
41 /* DMA */
42 const hrt_address DMA_BASE[N_DMA_ID] = {
43 	0x0000000000040000ULL
44 };
45 
46 const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID] = {
47 	0x00000000000CA000ULL
48 };
49 
50 /* IRQ */
51 const hrt_address IRQ_BASE[N_IRQ_ID] = {
52 	0x0000000000000500ULL,
53 	0x0000000000030A00ULL,
54 	0x000000000008C000ULL,
55 	0x0000000000090200ULL
56 };
57 
58 /*
59 	0x0000000000000500ULL};
60  */
61 
62 /* GDC */
63 const hrt_address GDC_BASE[N_GDC_ID] = {
64 	0x0000000000050000ULL,
65 	0x0000000000060000ULL
66 };
67 
68 /* FIFO_MONITOR (not a subset of GP_DEVICE) */
69 const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
70 	0x0000000000000000ULL
71 };
72 
73 /*
74 const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
75 	0x0000000000000000ULL};
76 
77 const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
78 	0x0000000000090000ULL};
79 */
80 
81 /* GP_DEVICE (single base for all separate GP_REG instances) */
82 const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
83 	0x0000000000000000ULL
84 };
85 
86 /*GP TIMER , all timer registers are inter-twined,
87  * so, having multiple base addresses for
88  * different timers does not help*/
89 const hrt_address GP_TIMER_BASE =
90     (hrt_address)0x0000000000000600ULL;
91 
92 /* GPIO */
93 const hrt_address GPIO_BASE[N_GPIO_ID] = {
94 	0x0000000000000400ULL
95 };
96 
97 /* TIMED_CTRL */
98 const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
99 	0x0000000000000100ULL
100 };
101 
102 /* INPUT_FORMATTER */
103 const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
104 	0x0000000000030000ULL,
105 	0x0000000000030200ULL,
106 	0x0000000000030400ULL,
107 	0x0000000000030600ULL
108 }; /* memcpy() */
109 
110 /* INPUT_SYSTEM */
111 const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
112 	0x0000000000080000ULL
113 };
114 
115 /*	0x0000000000081000ULL, */ /* capture A */
116 /*	0x0000000000082000ULL, */ /* capture B */
117 /*	0x0000000000083000ULL, */ /* capture C */
118 /*	0x0000000000084000ULL, */ /* Acquisition */
119 /*	0x0000000000085000ULL, */ /* DMA */
120 /*	0x0000000000089000ULL, */ /* ctrl */
121 /*	0x000000000008A000ULL, */ /* GP regs */
122 /*	0x000000000008B000ULL, */ /* FIFO */
123 /*	0x000000000008C000ULL, */ /* IRQ */
124 
125 /* RX, the MIPI lane control regs start at offset 0 */
126 const hrt_address RX_BASE[N_RX_ID] = {
127 	0x0000000000080100ULL
128 };
129 
130 /* IBUF_CTRL, part of the Input System 2401 */
131 const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID] = {
132 	0x00000000000C1800ULL,	/* ibuf controller A */
133 	0x00000000000C3800ULL,	/* ibuf controller B */
134 	0x00000000000C5800ULL	/* ibuf controller C */
135 };
136 
137 /* ISYS IRQ Controllers, part of the Input System 2401 */
138 const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID] = {
139 	0x00000000000C1400ULL,	/* port a */
140 	0x00000000000C3400ULL,	/* port b */
141 	0x00000000000C5400ULL	/* port c */
142 };
143 
144 /* CSI FE, part of the Input System 2401 */
145 const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = {
146 	0x00000000000C0400ULL,	/* csi fe controller A */
147 	0x00000000000C2400ULL,	/* csi fe controller B */
148 	0x00000000000C4400ULL	/* csi fe controller C */
149 };
150 
151 /* CSI BE, part of the Input System 2401 */
152 const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = {
153 	0x00000000000C0800ULL,	/* csi be controller A */
154 	0x00000000000C2800ULL,	/* csi be controller B */
155 	0x00000000000C4800ULL	/* csi be controller C */
156 };
157 
158 /* PIXEL Generator, part of the Input System 2401 */
159 const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = {
160 	0x00000000000C1000ULL,	/* pixel gen controller A */
161 	0x00000000000C3000ULL,	/* pixel gen controller B */
162 	0x00000000000C5000ULL	/* pixel gen controller C */
163 };
164 
165 /* Stream2MMIO, part of the Input System 2401 */
166 const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = {
167 	0x00000000000C0C00ULL,	/* stream2mmio controller A */
168 	0x00000000000C2C00ULL,	/* stream2mmio controller B */
169 	0x00000000000C4C00ULL	/* stream2mmio controller C */
170 };
171