1## SPDX-License-Identifier: GPL-2.0-only 2 3mainmenu "coreboot configuration" 4 5menu "General setup" 6 7config LOCALVERSION 8 string "Local version string" 9 help 10 Append an extra string to the end of the coreboot version. 11 12 This can be useful if, for instance, you want to append the 13 respective board's hostname or some other identifying string to 14 the coreboot version number, so that you can easily distinguish 15 boot logs of different boards from each other. 16 17config CONFIGURABLE_CBFS_PREFIX 18 bool 19 help 20 Select this to prompt to use to configure the prefix for cbfs files. 21 22choice 23 prompt "CBFS prefix to use" 24 depends on CONFIGURABLE_CBFS_PREFIX 25 default CBFS_PREFIX_FALLBACK 26 27config CBFS_PREFIX_FALLBACK 28 bool "fallback" 29 30config CBFS_PREFIX_NORMAL 31 bool "normal" 32 33config CBFS_PREFIX_DIY 34 bool "Define your own cbfs prefix" 35 36endchoice 37 38config CBFS_PREFIX 39 string "CBFS prefix to use" if CBFS_PREFIX_DIY 40 default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK 41 default "normal" if CBFS_PREFIX_NORMAL 42 help 43 Select the prefix to all files put into the image. It's "fallback" 44 by default, "normal" is a common alternative. 45 46config DEFAULT_COMPILER_LLVM_CLANG 47 bool 48 help 49 Allows to override the default compiler. This can for instance be 50 set in site-local/Kconfig. 51 52choice 53 prompt "Compiler to use" 54 default COMPILER_LLVM_CLANG if DEFAULT_COMPILER_LLVM_CLANG 55 default COMPILER_GCC 56 help 57 This option allows you to select the compiler used for building 58 coreboot. 59 You must build the coreboot crosscompiler for the board that you 60 have selected. 61 62 To build all the GCC crosscompilers (takes a LONG time), run: 63 make crossgcc 64 65 For help on individual architectures, run the command: 66 make help_toolchain 67 68config COMPILER_GCC 69 bool "GCC" 70 help 71 Use the GNU Compiler Collection (GCC) to build coreboot. 72 73 For details see http://gcc.gnu.org. 74 75config COMPILER_LLVM_CLANG 76 bool "LLVM/clang" 77 depends on ALLOW_EXPERIMENTAL_CLANG || ARCH_SUPPORTS_CLANG 78 help 79 Use LLVM/clang to build coreboot. To use this, you must build the 80 coreboot version of the clang compiler. Run the command 81 make clang 82 Note that Clang is not currently working on all architectures. 83 84 For details see http://clang.llvm.org. 85 86endchoice 87 88config ARCH_SUPPORTS_CLANG 89 bool 90 help 91 Opt-in flag for architectures that generally work well with CLANG. 92 By default the option would be hidden. 93 94config ALLOW_EXPERIMENTAL_CLANG 95 bool "Allow experimental LLVM/Clang" 96 depends on !ARCH_SUPPORTS_CLANG 97 help 98 On some architectures CLANG does not work that well. 99 Use this only to try to get CLANG working. 100 101config ANY_TOOLCHAIN 102 bool "Allow building with any toolchain" 103 default n 104 help 105 Many toolchains break when building coreboot since it uses quite 106 unusual linker features. Unless developers explicitly request it, 107 we'll have to assume that they use their distro compiler by mistake. 108 Make sure that using patched compilers is a conscious decision. 109 110config CCACHE 111 bool "Use ccache to speed up (re)compilation" 112 help 113 Enables the use of ccache for faster builds. 114 115 Requires the ccache utility in your system $PATH. 116 117 For details see https://ccache.samba.org. 118 119config IWYU 120 bool "Test platform with include-what-you-use" 121 help 122 This runs each source file through the include-what-you-use tool 123 to check the header includes. 124 125config FMD_GENPARSER 126 bool "Generate flashmap descriptor parser using flex and bison" 127 default n 128 help 129 Enable this option if you are working on the flashmap descriptor 130 parser and made changes to fmd_scanner.l or fmd_parser.y. 131 132 Otherwise, say N to use the provided pregenerated scanner/parser. 133 134config UTIL_GENPARSER 135 bool "Generate parsers for bincfg, sconfig and kconfig locally" 136 default n 137 help 138 Enable this option if you are working on the sconfig device tree 139 parser or bincfg and made changes to the .l or .y files. 140 141 Otherwise, say N to use the provided pregenerated scanner/parser. 142 143choice 144 prompt "Option backend to use" 145 default USE_MAINBOARD_SPECIFIC_OPTION_BACKEND if HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND 146 default USE_OPTION_TABLE if NVRAMCUI_SECONDARY_PAYLOAD 147 default USE_UEFI_VARIABLE_STORE if DRIVERS_EFI_VARIABLE_STORE && \ 148 PAYLOAD_EDK2 && SMMSTORE_V2 149 150config OPTION_BACKEND_NONE 151 bool "None" 152 153config USE_OPTION_TABLE 154 bool "Use CMOS for configuration values" 155 depends on HAVE_OPTION_TABLE 156 help 157 Enable this option if coreboot shall read options from the "CMOS" 158 NVRAM instead of using hard-coded values. 159 160config USE_UEFI_VARIABLE_STORE 161 bool "Use UEFI variable-store in SPI flash as option backend" 162 depends on DRIVERS_EFI_VARIABLE_STORE 163 depends on SMMSTORE_V2 164 help 165 Enable this option if coreboot shall read/write options from the 166 SMMSTORE region within the SPI flash. The region must be formatted 167 by the payload first before it can be used. 168 169config USE_MAINBOARD_SPECIFIC_OPTION_BACKEND 170 bool "Use mainboard-specific option backend" 171 depends on HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND 172 help 173 Use a mainboard-specific mechanism to access runtime-configurable 174 options. 175 176endchoice 177 178config STATIC_OPTION_TABLE 179 bool "Load default configuration values into CMOS on each boot" 180 depends on USE_OPTION_TABLE 181 help 182 Enable this option to reset "CMOS" NVRAM values to default on 183 every boot. Use this if you want the NVRAM configuration to 184 never be modified from its default values. 185 186config MB_COMPRESS_RAMSTAGE_LZ4 187 bool 188 help 189 Select this in a mainboard to use LZ4 compression by default 190 191choice 192 prompt "Ramstage compression" 193 depends on HAVE_RAMSTAGE && !UNCOMPRESSED_RAMSTAGE 194 default COMPRESS_RAMSTAGE_LZ4 if MB_COMPRESS_RAMSTAGE_LZ4 195 default COMPRESS_RAMSTAGE_LZMA 196 197config COMPRESS_RAMSTAGE_LZMA 198 bool "Compress ramstage with LZMA" 199 help 200 Compress ramstage with LZMA to save memory in the flash image. 201 202config COMPRESS_RAMSTAGE_LZ4 203 bool "Compress ramstage with LZ4" 204 help 205 LZ4 doesn't give as good compression as LZMA, but decompresses much 206 faster. For large binaries such as ramstage, it's typically best to 207 use LZMA, but there can be cases where the faster decompression of 208 LZ4 can lead to a faster boot time. Testing on each individual board 209 is typically going to be needed due to the large number of factors 210 that can influence the decision. Binary size, CPU speed, ROM read 211 speed, cache, and other factors all play a part. 212 213 If you're not sure, stick with LZMA. 214 215endchoice 216 217config COMPRESS_PRERAM_STAGES 218 bool "Compress romstage and verstage with LZ4" 219 depends on (HAVE_ROMSTAGE || HAVE_VERSTAGE) && NO_XIP_EARLY_STAGES 220 # Default value set at the end of the file 221 help 222 Compress romstage and (if it exists) verstage with LZ4 to save flash 223 space and speed up boot, since the time for reading the image from SPI 224 (and in the vboot case verifying it) is usually much greater than the 225 time spent decompressing. Doesn't work for XIP stages for obvious 226 reasons. 227 228config COMPRESS_BOOTBLOCK 229 bool 230 depends on HAVE_BOOTBLOCK 231 help 232 This option can be used to compress the bootblock with LZ4 and attach 233 a small self-decompression stub to its front. This can drastically 234 reduce boot time on platforms where the bootblock is loaded over a 235 very slow connection and bootblock size trumps all other factors for 236 speed. Since using this option usually requires changes to the 237 SoC memlayout and possibly extra support code, it should not be 238 user-selectable. (There's no real point in offering this to the user 239 anyway... if it works and saves boot time, you would always want it.) 240 241config SEPARATE_ROMSTAGE 242 bool "Build a separate romstage" 243 help 244 Build a separate romstage that is loaded by bootblock. With this 245 option disabled the romstage sources are linked inside the bootblock 246 as a single stage. 247 248config INCLUDE_CONFIG_FILE 249 bool "Include the coreboot .config file into the ROM image" 250 # Default value set at the end of the file 251 help 252 Include the .config file that was used to compile coreboot 253 in the (CBFS) ROM image. This is useful if you want to know which 254 options were used to build a specific coreboot.rom image. 255 256 Saying Y here will increase the image size by 2-3KB. 257 258 You can then use cbfstool to extract the config from a final image: 259 260 cbfstool coreboot.rom extract -n config -f <output file path> 261 262 Alternatively, you can also use cbfstool to print the image 263 contents (including the raw 'config' item we're looking for). 264 265 Example: 266 267 $ cbfstool coreboot.rom print 268 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304, 269 offset 0x0 270 Alignment: 64 bytes 271 272 Name Offset Type Size 273 cmos_layout.bin 0x0 CMOS layout 1159 274 fallback/romstage 0x4c0 stage 339756 275 fallback/ramstage 0x53440 stage 186664 276 fallback/payload 0x80dc0 payload 51526 277 config 0x8d740 raw 3324 278 (empty) 0x8e480 null 3610440 279 280config COLLECT_TIMESTAMPS 281 bool "Create a table of timestamps collected during boot" 282 default y if ARCH_X86 283 help 284 Make coreboot create a table of timer-ID/timer-value pairs to 285 allow measuring time spent at different phases of the boot process. 286 287config TIMESTAMPS_ON_CONSOLE 288 bool "Print the timestamp values on the console" 289 default n 290 depends on COLLECT_TIMESTAMPS 291 help 292 Print the timestamps to the debug console if enabled at level info. 293 294config USE_BLOBS 295 bool "Allow use of binary-only repository" 296 default y 297 help 298 This draws in the blobs repository, which contains binary files that 299 might be required for some chipsets or boards. 300 This flag ensures that a "Free" option remains available for users. 301 302config USE_AMD_BLOBS 303 bool "Allow AMD blobs repository (with license agreement)" 304 depends on USE_BLOBS 305 help 306 This draws in the amd_blobs repository, which contains binary files 307 distributed by AMD, including VBIOS, PSP bootloaders, SMU firmwares, 308 etc. Selecting this item to download or clone the repo implies your 309 agreement to the AMD license agreement. A copy of the license text 310 may be reviewed by reading Documentation/soc/amd/amdblobs_license.md, 311 and your copy of the license is present in the repo once downloaded. 312 313 Note that for some products, omitting PSP, SMU images, or other items 314 may result in a nonbooting coreboot.rom. 315 316config USE_QC_BLOBS 317 bool "Allow QC blobs repository (selecting this agrees to the license!)" 318 depends on USE_BLOBS 319 help 320 This draws in the qc_blobs repository, which contains binary files 321 distributed by Qualcomm that are required to build firmware for 322 certain Qualcomm SoCs (including QcLib, QC-SEC, qtiseclib and QUP 323 firmware). If you say Y here you are implicitly agreeing to the 324 Qualcomm license agreement which can be found at: 325 https://review.coreboot.org/cgit/qc_blobs.git/tree/LICENSE 326 327 ***************************************************** 328 PLEASE MAKE SURE YOU READ AND AGREE TO ALL TERMS IN 329 ABOVE LICENSE AGREEMENT BEFORE SELECTING THIS OPTION! 330 ***************************************************** 331 332 Not selecting this option means certain Qualcomm SoCs and related 333 mainboards cannot be built and will be hidden from the "Mainboards" 334 section. 335 336config COVERAGE 337 bool "Code coverage support" 338 depends on COMPILER_GCC 339 help 340 Add code coverage support for coreboot. This will store code 341 coverage information in CBMEM for extraction from user space. 342 If unsure, say N. 343 344config UBSAN 345 bool "Undefined behavior sanitizer support" 346 default n 347 help 348 Instrument the code with checks for undefined behavior. If unsure, 349 say N because it adds a small performance penalty and may abort 350 on code that happens to work in spite of the UB. 351 352config HAVE_ASAN_IN_ROMSTAGE 353 bool 354 default n 355 356config ASAN_IN_ROMSTAGE 357 bool 358 default n 359 help 360 Enable address sanitizer in romstage for platform. 361 362config HAVE_ASAN_IN_RAMSTAGE 363 bool 364 default n 365 366config ASAN_IN_RAMSTAGE 367 bool 368 default n 369 help 370 Enable address sanitizer in ramstage for platform. 371 372config ASAN 373 bool "Address sanitizer support" 374 default n 375 select ASAN_IN_ROMSTAGE if HAVE_ASAN_IN_ROMSTAGE 376 select ASAN_IN_RAMSTAGE if HAVE_ASAN_IN_RAMSTAGE 377 depends on COMPILER_GCC 378 help 379 Enable address sanitizer - runtime memory debugger, 380 designed to find out-of-bounds accesses and use-after-scope bugs. 381 382 This feature consumes up to 1/8 of available memory and brings about 383 ~1.5x performance slowdown. 384 385 If unsure, say N. 386 387if ASAN 388 comment "Before using this feature, make sure that " 389 comment "asan_shadow_offset_callback patch is applied to GCC." 390endif 391 392choice 393 prompt "Stage Cache for ACPI S3 resume" 394 default NO_STAGE_CACHE if !HAVE_ACPI_RESUME || MAINBOARD_DISABLE_STAGE_CACHE 395 default TSEG_STAGE_CACHE if SMM_TSEG 396 397config NO_STAGE_CACHE 398 bool "Disabled" 399 help 400 Do not save any component in stage cache for resume path. On resume, 401 all components would be read back from CBFS again. 402 403config TSEG_STAGE_CACHE 404 bool "TSEG" 405 depends on SMM_TSEG 406 help 407 The option enables stage cache support for platform. Platform 408 can stash copies of postcar, ramstage and raw runtime data 409 inside SMM TSEG, to be restored on S3 resume path. 410 411config CBMEM_STAGE_CACHE 412 bool "CBMEM" 413 depends on !SMM_TSEG 414 help 415 The option enables stage cache support for platform. Platform 416 can stash copies of postcar, ramstage and raw runtime data 417 inside CBMEM. 418 419 While the approach is faster than reloading stages from boot media 420 it is also a possible attack scenario via which OS can possibly 421 circumvent SMM locks and SPI write protections. 422 423 If unsure, select 'N' 424 425endchoice 426 427config MAINBOARD_DISABLE_STAGE_CACHE 428 bool 429 help 430 Selected by mainboards which wish to disable the stage cache. 431 E.g. mainboards which don't use S3 resume in the field may wish to 432 disable it to save boot time at the cost of increasing S3 resume time. 433 434config UPDATE_IMAGE 435 bool "Update existing coreboot.rom image" 436 help 437 If this option is enabled, no new coreboot.rom file 438 is created. Instead it is expected that there already 439 is a suitable file for further processing. 440 The bootblock will not be modified. 441 442 If unsure, select 'N' 443 444config BOOTSPLASH_IMAGE 445 bool "Add a bootsplash image" 446 help 447 Select this option if you have a bootsplash image that you would 448 like to add to your ROM. 449 450 This will only add the image to the ROM. To actually run it check 451 options under 'Display' section. 452 453config BOOTSPLASH_FILE 454 string "Bootsplash path and filename" 455 depends on BOOTSPLASH_IMAGE 456 # Default value set at the end of the file 457 help 458 The path and filename of the file to use as graphical bootsplash 459 screen. The file format has to be JPEG with YCC 4:2:0 color sampling 460 unless converted with "Pre-process bootsplash file with ImageMagick". 461 462 The image can only be displayed by coreboot if it's smaller or has 463 the same size as the framebuffer resolution. Width and height have 464 to be a multiple of 16 pixels. 465 466 Setting these constraints allows a leaner implementation in coreboot. 467 The minimum necessary ImageMagick command line seems to be: 468 $ convert input.img -colorspace YCC -sampling-factor 4:2:0 bootsplash.jpg 469 470config BOOTSPLASH_CONVERT 471 bool "Pre-process bootsplash file with ImageMagick" 472 depends on BOOTSPLASH_IMAGE 473 help 474 Use ImageMagick (`convert` program) to convert a bootsplash image 475 to the supported JPEG format. 476 477config BOOTSPLASH_CONVERT_QUALITY 478 int "Bootsplash JPEG target quality (%)" 479 depends on BOOTSPLASH_CONVERT 480 range 1 100 481 # Default value set at the end of the file 482 483config BOOTSPLASH_CONVERT_RESIZE 484 bool "Resize bootsplash image" 485 depends on BOOTSPLASH_CONVERT 486 help 487 Resize the image to the given resolution. Aspect ratio will be kept, 488 adding black bars as necessary. 489 490config BOOTSPLASH_CONVERT_RESOLUTION 491 string "Bootsplash image target size" 492 depends on BOOTSPLASH_CONVERT_RESIZE 493 # Default value set at the end of the file 494 help 495 Target image resolution given as <width>x<height>, e.g. 1024x768. 496 Values not divisible by 16 will be rounded down. 497 498 When using coreboot to display the bootsplash image (CONFIG_BOOTSPLASH), 499 set this lower or equal to the minimum resolution you expect. 500 501config BOOTSPLASH_CONVERT_COLORSWAP 502 bool "Swap red and blue color channels" 503 depends on BOOTSPLASH_CONVERT 504 help 505 The JPEG decoder currently ignores the framebuffer color order. 506 If your colors seem all wrong, try this option. 507 508config FW_CONFIG 509 bool 510 help 511 Enable support for probing devices with fw_config. This is a simple 512 bitmask broken into fields and options for probing. 513 Select this option in the Mainboard Kconfig. 514 515config FW_CONFIG_SOURCE_CHROMEEC_CBI 516 bool 517 depends on FW_CONFIG && EC_GOOGLE_CHROMEEC 518 help 519 This option tells coreboot to read the firmware configuration value 520 from the Google Chrome Embedded Controller CBI interface. This source 521 is not tried if FW_CONFIG_SOURCE_CBFS is enabled and the value was 522 found in CBFS. 523 Select this option in the Mainboard Kconfig. 524 525config FW_CONFIG_SOURCE_CBFS 526 bool "Obtain Firmware Configuration value from CBFS" 527 depends on FW_CONFIG 528 help 529 With this option enabled coreboot will look for the 32bit firmware 530 configuration value in CBFS at the selected prefix with the file name 531 "fw_config". This option gets run if no value is found with CBI, so acts 532 as a FW_CONFIG_SOURCE_CHROMEEC_CBI fallback option. 533 534config FW_CONFIG_SOURCE_VPD 535 bool "Obtain Firmware Configuration value from VPD" 536 depends on FW_CONFIG && VPD 537 help 538 With this option enabled coreboot will look for the 32bit firmware 539 configuration value in VPD key name "fw_config". This option runs if no 540 FW_CONFIG value is set by either CBI or CBFS. 541 542config HAVE_RAMPAYLOAD 543 bool 544 545config RAMPAYLOAD 546 bool "Enable coreboot flow without executing ramstage" 547 default y if ARCH_X86 548 depends on HAVE_RAMPAYLOAD 549 help 550 If this option is enabled, coreboot flow will skip ramstage 551 loading and execution of ramstage to load payload. 552 553 Instead it is expected to load payload from postcar stage itself. 554 555 In this flow coreboot will perform basic x86 initialization 556 (DRAM resource allocation), MTRR programming, 557 Skip PCI enumeration logic and only allocate BAR for fixed devices 558 (bootable devices, TPM over GSPI). 559 560config HAVE_CONFIGURABLE_RAMSTAGE 561 bool 562 563config CONFIGURABLE_RAMSTAGE 564 bool "Enable a configurable ramstage." 565 default y if ARCH_X86 566 depends on HAVE_CONFIGURABLE_RAMSTAGE 567 help 568 A configurable ramstage allows you to select which parts of the ramstage 569 to run. Currently, we can only select a minimal PCI scanning step. 570 The minimal PCI scanning will only check those parts that are enabled 571 in the devicetree.cb. By convention none of those devices should be bridges. 572 573config MINIMAL_PCI_SCANNING 574 bool "Enable minimal PCI scanning" 575 depends on CONFIGURABLE_RAMSTAGE && PCI 576 help 577 If this option is enabled, coreboot will scan only PCI devices 578 marked as mandatory in devicetree.cb 579 580menu "Software Bill Of Materials (SBOM)" 581 582source "src/sbom/Kconfig" 583 584endmenu 585endmenu 586 587menu "Mainboard" 588 589source "src/mainboard/Kconfig" 590 591config DEVICETREE 592 string 593 default "devicetree.cb" 594 help 595 This symbol allows mainboards to select a different file under their 596 mainboard directory for the devicetree.cb file. This allows the board 597 variants that need different devicetrees to be in the same directory. 598 599 Examples: "devicetree.variant.cb" 600 "variant/devicetree.cb" 601 602config OVERRIDE_DEVICETREE 603 string 604 default "" 605 help 606 This symbol allows variants to provide an override devicetree file to 607 override the registers and/or add new devices on top of the ones 608 provided by baseboard devicetree using CONFIG_DEVICETREE. 609 610 Examples: "devicetree.variant-override.cb" 611 "variant/devicetree-override.cb" 612 613config FMDFILE 614 string "fmap description file in fmd format" 615 default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS 616 default "" 617 help 618 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE, 619 but in some cases more complex setups are required. 620 When an fmd is specified, it overrides the default format. 621 622config CBFS_SIZE 623 hex "Size of CBFS filesystem in ROM" 624 depends on FMDFILE = "" 625 # Default value set at the end of the file 626 help 627 This is the part of the ROM actually managed by CBFS, located at the 628 end of the ROM (passed through cbfstool -o) on x86 and at the start 629 of the ROM (passed through cbfstool -s) everywhere else. It defaults 630 to span the whole ROM on all but Intel systems that use an Intel Firmware 631 Descriptor. It can be overridden to make coreboot live alongside other 632 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE 633 binaries. This symbol should only be used to generate a default FMAP and 634 is unused when a non-default fmd file is provided via CONFIG_FMDFILE. 635 636endmenu 637 638# load site-local kconfig to allow user specific defaults and overrides 639source "site-local/Kconfig" 640 641config SYSTEM_TYPE_LAPTOP 642 default n 643 bool 644 645config SYSTEM_TYPE_TABLET 646 default n 647 bool 648 649config SYSTEM_TYPE_DETACHABLE 650 default n 651 bool 652 653config SYSTEM_TYPE_CONVERTIBLE 654 default n 655 bool 656 657config CBFS_AUTOGEN_ATTRIBUTES 658 default n 659 bool 660 help 661 If this option is selected, every file in cbfs which has a constraint 662 regarding position or alignment will get an additional file attribute 663 which describes this constraint. 664 665menu "Chipset" 666 667comment "SoC" 668source "src/soc/*/*/Kconfig" 669source "src/soc/*/*/Kconfig.common" 670comment "CPU" 671source "src/cpu/Kconfig" 672comment "Northbridge" 673source "src/northbridge/*/*/Kconfig" 674source "src/northbridge/*/*/Kconfig.common" 675comment "Southbridge" 676source "src/southbridge/*/*/Kconfig" 677source "src/southbridge/*/*/Kconfig.common" 678comment "Super I/O" 679source "src/superio/*/*/Kconfig" 680comment "Embedded Controllers" 681source "src/ec/acpi/Kconfig" 682source "src/ec/*/*/Kconfig" 683 684source "src/southbridge/intel/common/firmware/Kconfig" 685source "src/vendorcode/*/Kconfig" 686 687source "src/arch/*/Kconfig" 688 689config CHIPSET_DEVICETREE 690 string 691 default "" 692 help 693 This symbol allows a chipset to provide a set of default settings in 694 a devicetree which are common to all mainboards. This may include 695 devices (including alias names), chip drivers, register settings, 696 and others. This path is relative to the src/ directory. 697 698 Example: "chipset.cb" 699 700endmenu 701 702source "src/device/Kconfig" 703 704menu "Generic Drivers" 705source "src/drivers/*/Kconfig" 706source "src/drivers/*/*/Kconfig" 707source "src/drivers/*/*/*/Kconfig" 708source "src/commonlib/storage/Kconfig" 709endmenu 710 711menu "Security" 712 713source "src/security/Kconfig" 714source "src/vendorcode/eltan/security/Kconfig" 715 716endmenu 717 718source "src/acpi/Kconfig" 719 720# This option is for the current boards/chipsets where SPI flash 721# is not the boot device. Currently nearly all boards/chipsets assume 722# SPI flash is the boot device. 723config BOOT_DEVICE_NOT_SPI_FLASH 724 bool 725 default n 726 727config BOOT_DEVICE_SPI_FLASH 728 bool 729 default y if !BOOT_DEVICE_NOT_SPI_FLASH 730 default n 731 732config BOOT_DEVICE_MEMORY_MAPPED 733 bool 734 default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH 735 default n 736 help 737 Inform system if SPI is memory-mapped or not. 738 739config BOOT_DEVICE_SUPPORTS_WRITES 740 bool 741 default n 742 help 743 Indicate that the platform has writable boot device 744 support. 745 746config RTC 747 bool 748 default n 749 750config HEAP_SIZE 751 hex 752 default 0x100000 753 754config STACK_SIZE 755 hex 756 default 0x2000 if ARCH_X86 757 default 0x0 758 759config MAX_CPUS 760 int 761 default 1 762 763source "src/console/Kconfig" 764 765config ACPI_S1_NOT_SUPPORTED 766 bool 767 default n 768 help 769 Set this to 'y' on platforms that do not support ACPI S1 state. 770 771config HAVE_ACPI_RESUME 772 bool 773 default n 774 775config DISABLE_ACPI_HIBERNATE 776 bool 777 default n 778 help 779 Removes S4 from the available sleepstates 780 781config RESUME_PATH_SAME_AS_BOOT 782 bool 783 default y if ARCH_X86 784 depends on HAVE_ACPI_RESUME 785 help 786 This option indicates that when a system resumes it takes the 787 same path as a regular boot. e.g. an x86 system runs from the 788 reset vector at 0xfffffff0 on both resume and warm/cold boot. 789 790config NO_MONOTONIC_TIMER 791 def_bool n 792 793config HAVE_MONOTONIC_TIMER 794 bool 795 depends on !NO_MONOTONIC_TIMER 796 default y 797 help 798 The board/chipset provides a monotonic timer. 799 800config GENERIC_UDELAY 801 bool 802 depends on HAVE_MONOTONIC_TIMER 803 default y if !ARCH_X86 804 help 805 The board/chipset uses a generic udelay function utilizing the 806 monotonic timer. 807 808config TIMER_QUEUE 809 def_bool n 810 depends on HAVE_MONOTONIC_TIMER 811 help 812 Provide a timer queue for performing time-based callbacks. 813 814config COOP_MULTITASKING 815 def_bool n 816 select TIMER_QUEUE 817 depends on ARCH_X86 818 help 819 Cooperative multitasking allows callbacks to be multiplexed on the 820 main thread. With this enabled it allows for multiple execution paths 821 to take place when they have udelay() calls within their code. 822 823config NUM_THREADS 824 int 825 default 4 826 depends on COOP_MULTITASKING 827 help 828 How many execution threads to cooperatively multitask with. 829 830config HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND 831 bool 832 help 833 Selected by mainboards which implement a mainboard-specific mechanism 834 to access the values for runtime-configurable options. For example, a 835 custom BMC interface or an EEPROM with an externally-imposed layout. 836 837config HAVE_OPTION_TABLE 838 bool 839 default n 840 help 841 This variable specifies whether a given board has a cmos.layout 842 file containing NVRAM/CMOS bit definitions. 843 It defaults to 'n' but can be selected in mainboard/*/Kconfig. 844 845config CMOS_LAYOUT_FILE 846 string 847 default "src/mainboard/\$(MAINBOARDDIR)/cmos.layout" 848 depends on HAVE_OPTION_TABLE 849 850config PCI_IO_CFG_EXT 851 bool 852 default n 853 854config IOAPIC 855 bool 856 default y if SMP 857 default n 858 859config USE_WATCHDOG_ON_BOOT 860 bool 861 default n 862 863config GFXUMA 864 bool 865 default n 866 help 867 Enable Unified Memory Architecture for graphics. 868 869config HAVE_MP_TABLE 870 bool 871 help 872 This variable specifies whether a given board has MP table support. 873 It is usually set in mainboard/*/Kconfig. 874 Whether or not the MP table is actually generated by coreboot 875 is configurable by the user via GENERATE_MP_TABLE. 876 877config HAVE_PIRQ_TABLE 878 bool 879 help 880 This variable specifies whether a given board has PIRQ table support. 881 It is usually set in mainboard/*/Kconfig. 882 Whether or not the PIRQ table is actually generated by coreboot 883 is configurable by the user via GENERATE_PIRQ_TABLE. 884 885config ACPI_NHLT 886 bool 887 default n 888 help 889 Build support for NHLT (non HD Audio) ACPI table generation. 890 891#These Options are here to avoid "undefined" warnings. 892#The actual selection and help texts are in the following menu. 893 894menu "System tables" 895 896config GENERATE_MP_TABLE 897 prompt "Generate an MP table" if HAVE_MP_TABLE 898 bool 899 depends on !ECAM_MMCONF_SUPPORT || ECAM_MMCONF_BUS_NUMBER <= 256 900 default HAVE_MP_TABLE 901 help 902 Generate an MP table (conforming to the Intel MultiProcessor 903 specification 1.4) for this board. 904 905 If unsure, say Y. 906 907config GENERATE_PIRQ_TABLE 908 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE 909 bool 910 default HAVE_PIRQ_TABLE 911 help 912 Generate a PIRQ table for this board. 913 914 If unsure, say Y. 915 916config GENERATE_SMBIOS_TABLES 917 depends on ARCH_X86 || ARCH_ARM64 918 bool "Generate SMBIOS tables" 919 default n if ARCH_ARM64 920 default y 921 help 922 Generate SMBIOS tables for this board. 923 924 If unsure, say Y. 925 926config SMBIOS_TYPE41_PROVIDED_BY_DEVTREE 927 bool 928 depends on ARCH_X86 929 help 930 If enabled, only generate SMBIOS Type 41 entries for PCI devices in 931 the devicetree for which Type 41 information is provided, e.g. with 932 the `smbios_dev_info` devicetree syntax. This is useful to manually 933 assign specific instance IDs to onboard devices irrespective of the 934 device traversal order. It is assumed that instance IDs for devices 935 of the same class are unique. 936 When disabled, coreboot autogenerates SMBIOS Type 41 entries for all 937 appropriate PCI devices in the devicetree. Instance IDs are assigned 938 successive numbers from a monotonically increasing counter, with one 939 counter for each device class. 940 941config SMBIOS_PROVIDED_BY_MOBO 942 bool 943 default n 944 945if GENERATE_SMBIOS_TABLES 946 947config BIOS_VENDOR 948 prompt "SMBIOS BIOS Vendor name" 949 string 950 default "coreboot" 951 help 952 The BIOS Vendor name to store in the SMBIOS Type0 table. 953 954config MAINBOARD_SERIAL_NUMBER 955 prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO 956 string 957 default "123456789" 958 help 959 The Serial Number to store in SMBIOS structures. 960 961config MAINBOARD_VERSION 962 prompt "SMBIOS Version Number" if !SMBIOS_PROVIDED_BY_MOBO 963 string 964 default "1.0" 965 help 966 The Version Number to store in SMBIOS structures. 967 968config MAINBOARD_SMBIOS_MANUFACTURER 969 prompt "SMBIOS Manufacturer" if !SMBIOS_PROVIDED_BY_MOBO 970 string 971 default MAINBOARD_VENDOR 972 help 973 Override the default Manufacturer stored in SMBIOS structures. 974 975config MAINBOARD_SMBIOS_PRODUCT_NAME 976 prompt "SMBIOS Product name" if !SMBIOS_PROVIDED_BY_MOBO 977 string 978 default MAINBOARD_PART_NUMBER 979 help 980 Override the default Product name stored in SMBIOS structures. 981 982config VPD_SMBIOS_VERSION 983 bool "Populates SMBIOS type 0 version from the VPD_RO variable 'firmware_version'" 984 default n 985 depends on VPD 986 help 987 Selecting this option will read firmware_version from 988 VPD_RO and override SMBIOS type 0 version. One special 989 scenario of using this feature is to assign a BIOS version 990 to a coreboot image without the need to rebuild from source. 991 992endif 993 994endmenu 995 996source "payloads/Kconfig" 997 998menu "Debugging" 999 1000comment "CPU Debug Settings" 1001source "src/cpu/*/Kconfig.debug_cpu" 1002 1003comment "Vendorcode Debug Settings" 1004 source "src/vendorcode/*/*/Kconfig.debug" 1005 1006comment "BLOB Debug Settings" 1007source "src/drivers/intel/fsp*/Kconfig.debug_blob" 1008 1009comment "General Debug Settings" 1010 1011# TODO: Better help text and detailed instructions. 1012config GDB_STUB 1013 bool "GDB debugging support" 1014 default n 1015# FIXME Not implemented in long mode 1016 depends on DRIVERS_UART && !USE_X86_64_SUPPORT 1017 help 1018 If enabled, you will be able to set breakpoints for gdb debugging. 1019 See src/arch/x86/c_start.S for details. 1020 1021config GDB_WAIT 1022 bool "Wait for a GDB connection in the ramstage" 1023 default n 1024 depends on GDB_STUB 1025 help 1026 If enabled, coreboot will wait for a GDB connection in the ramstage. 1027 1028 1029config FATAL_ASSERTS 1030 bool "Halt when hitting a BUG() or assertion error" 1031 default n 1032 help 1033 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT(). 1034 1035config HAVE_DEBUG_GPIO 1036 bool 1037 1038config DEBUG_GPIO 1039 bool "Output verbose GPIO debug messages" 1040 depends on HAVE_DEBUG_GPIO 1041 1042config DEBUG_CBFS 1043 bool "Output verbose CBFS debug messages" 1044 default n 1045 help 1046 This option enables additional CBFS related debug messages. 1047 1048config HAVE_DEBUG_RAM_SETUP 1049 def_bool n 1050 1051config DEBUG_RAM_SETUP 1052 bool "Output verbose RAM init debug messages" 1053 default n 1054 depends on HAVE_DEBUG_RAM_SETUP 1055 help 1056 This option enables additional RAM init related debug messages. 1057 It is recommended to enable this when debugging issues on your 1058 board which might be RAM init related. 1059 1060 Note: This option will increase the size of the coreboot image. 1061 1062 If unsure, say N. 1063 1064config DEBUG_PIRQ 1065 bool "Check PIRQ table consistency" 1066 default n 1067 depends on GENERATE_PIRQ_TABLE 1068 help 1069 If unsure, say N. 1070 1071config HAVE_DEBUG_SMBUS 1072 def_bool n 1073 1074config DEBUG_SMBUS 1075 bool "Output verbose SMBus debug messages" 1076 default n 1077 depends on HAVE_DEBUG_SMBUS 1078 help 1079 This option enables additional SMBus (and SPD) debug messages. 1080 1081 Note: This option will increase the size of the coreboot image. 1082 1083 If unsure, say N. 1084 1085config DEBUG_SMI 1086 bool "Output verbose SMI debug messages" 1087 default n 1088 depends on HAVE_SMI_HANDLER 1089 select SPI_FLASH_SMM if EM100PRO_SPI_CONSOLE || CONSOLE_SPI_FLASH 1090 help 1091 This option enables additional SMI related debug messages. 1092 1093 Note: This option will increase the size of the coreboot image. 1094 1095 If unsure, say N. 1096 1097config DEBUG_PERIODIC_SMI 1098 bool "Trigger SMI periodically" 1099 depends on DEBUG_SMI 1100 1101# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional 1102# printk(BIOS_DEBUG, ...) calls. 1103config DEBUG_MALLOC 1104 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL 1105 bool 1106 default n 1107 help 1108 This option enables additional malloc related debug messages. 1109 1110 Note: This option will increase the size of the coreboot image. 1111 1112 If unsure, say N. 1113 1114# Only visible if DEBUG_SPEW (8) is set. 1115config DEBUG_RESOURCES 1116 bool "Output verbose PCI MEM and IO resource debug messages" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL 1117 default n 1118 help 1119 This option enables additional PCI memory and IO debug messages. 1120 Note: This option will increase the size of the coreboot image. 1121 If unsure, say N. 1122 1123config DEBUG_CONSOLE_INIT 1124 bool "Debug console initialisation code" 1125 default n 1126 help 1127 With this option printk()'s are attempted before console hardware 1128 initialisation has been completed. Your mileage may vary. 1129 1130 Typically you will need to modify source in console_hw_init() such 1131 that a working console appears before the one you want to debug. 1132 1133 If unsure, say N. 1134 1135# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional 1136# printk(BIOS_DEBUG, ...) calls. 1137config REALMODE_DEBUG 1138 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL 1139 bool 1140 default n 1141 depends on PCI_OPTION_ROM_RUN_REALMODE 1142 help 1143 This option enables additional x86emu related debug messages. 1144 1145 Note: This option will increase the time to emulate a ROM. 1146 1147 If unsure, say N. 1148 1149config X86EMU_DEBUG 1150 bool "Output verbose x86emu debug messages" 1151 default n 1152 depends on PCI_OPTION_ROM_RUN_YABEL 1153 help 1154 This option enables additional x86emu related debug messages. 1155 1156 Note: This option will increase the size of the coreboot image. 1157 1158 If unsure, say N. 1159 1160if X86EMU_DEBUG 1161 1162config X86EMU_DEBUG_JMP 1163 bool "Trace JMP/RETF" 1164 default n 1165 help 1166 Print information about JMP and RETF opcodes from x86emu. 1167 1168 Note: This option will increase the size of the coreboot image. 1169 1170 If unsure, say N. 1171 1172config X86EMU_DEBUG_TRACE 1173 bool "Trace all opcodes" 1174 default n 1175 help 1176 Print _all_ opcodes that are executed by x86emu. 1177 1178 WARNING: This will produce a LOT of output and take a long time. 1179 1180 Note: This option will increase the size of the coreboot image. 1181 1182 If unsure, say N. 1183 1184config X86EMU_DEBUG_PNP 1185 bool "Log Plug&Play accesses" 1186 default n 1187 help 1188 Print Plug And Play accesses made by option ROMs. 1189 1190 Note: This option will increase the size of the coreboot image. 1191 1192 If unsure, say N. 1193 1194config X86EMU_DEBUG_DISK 1195 bool "Log Disk I/O" 1196 default n 1197 help 1198 Print Disk I/O related messages. 1199 1200 Note: This option will increase the size of the coreboot image. 1201 1202 If unsure, say N. 1203 1204config X86EMU_DEBUG_PMM 1205 bool "Log PMM" 1206 default n 1207 help 1208 Print messages related to POST Memory Manager (PMM). 1209 1210 Note: This option will increase the size of the coreboot image. 1211 1212 If unsure, say N. 1213 1214 1215config X86EMU_DEBUG_VBE 1216 bool "Debug VESA BIOS Extensions" 1217 default n 1218 help 1219 Print messages related to VESA BIOS Extension (VBE) functions. 1220 1221 Note: This option will increase the size of the coreboot image. 1222 1223 If unsure, say N. 1224 1225config X86EMU_DEBUG_INT10 1226 bool "Redirect INT10 output to console" 1227 default n 1228 help 1229 Let INT10 (i.e. character output) calls print messages to debug output. 1230 1231 Note: This option will increase the size of the coreboot image. 1232 1233 If unsure, say N. 1234 1235config X86EMU_DEBUG_INTERRUPTS 1236 bool "Log intXX calls" 1237 default n 1238 help 1239 Print messages related to interrupt handling. 1240 1241 Note: This option will increase the size of the coreboot image. 1242 1243 If unsure, say N. 1244 1245config X86EMU_DEBUG_CHECK_VMEM_ACCESS 1246 bool "Log special memory accesses" 1247 default n 1248 help 1249 Print messages related to accesses to certain areas of the virtual 1250 memory (e.g. BDA (BIOS Data Area) or interrupt vectors) 1251 1252 Note: This option will increase the size of the coreboot image. 1253 1254 If unsure, say N. 1255 1256config X86EMU_DEBUG_MEM 1257 bool "Log all memory accesses" 1258 default n 1259 help 1260 Print memory accesses made by option ROM. 1261 Note: This also includes accesses to fetch instructions. 1262 1263 Note: This option will increase the size of the coreboot image. 1264 1265 If unsure, say N. 1266 1267config X86EMU_DEBUG_IO 1268 bool "Log IO accesses" 1269 default n 1270 help 1271 Print I/O accesses made by option ROM. 1272 1273 Note: This option will increase the size of the coreboot image. 1274 1275 If unsure, say N. 1276 1277config X86EMU_DEBUG_TIMINGS 1278 bool "Output timing information" 1279 default n 1280 depends on HAVE_MONOTONIC_TIMER 1281 help 1282 Print timing information needed by i915tool. 1283 1284 If unsure, say N. 1285 1286endif 1287 1288config DEBUG_SPI_FLASH 1289 bool "Output verbose SPI flash debug messages" 1290 default n 1291 depends on SPI_FLASH 1292 help 1293 This option enables additional SPI flash related debug messages. 1294 1295config DEBUG_IPMI 1296 bool "Output verbose IPMI debug messages" 1297 default n 1298 depends on IPMI_KCS 1299 help 1300 This option enables additional IPMI related debug messages. 1301 1302if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8 1303# Only visible with the right southbridge and loglevel. 1304config DEBUG_INTEL_ME 1305 bool "Verbose logging for Intel Management Engine" 1306 default n 1307 help 1308 Enable verbose logging for Intel Management Engine driver that 1309 is present on Intel 6-series chipsets. 1310endif 1311 1312config DEBUG_FUNC 1313 bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL 1314 default n 1315 help 1316 This option enables additional function entry and exit debug messages 1317 for select functions. 1318 Note: This option will increase the size of the coreboot image. 1319 If unsure, say N. 1320 1321config DEBUG_COVERAGE 1322 bool "Debug code coverage" 1323 default n 1324 depends on COVERAGE 1325 help 1326 If enabled, the code coverage hooks in coreboot will output some 1327 information about the coverage data that is dumped. 1328 1329config DEBUG_BOOT_STATE 1330 bool "Debug boot state machine" 1331 default n 1332 help 1333 Control debugging of the boot state machine. When selected displays 1334 the state boundaries in ramstage. 1335 1336config DEBUG_ADA_CODE 1337 bool "Compile debug code in Ada sources" 1338 default n 1339 help 1340 Add the compiler switch `-gnata` to compile code guarded by 1341 `pragma Debug`. 1342 1343config HAVE_EM100_SUPPORT 1344 bool 1345 help 1346 This is enabled by platforms which can support using the EM100. 1347 1348config EM100 1349 bool "Configure image for EM100 usage" 1350 depends on HAVE_EM100_SUPPORT 1351 help 1352 The Dediprog EM100 SPI emulator allows fast loading of new SPI images 1353 over USB. However it only supports a maximum SPI clock of 20MHz and 1354 single data output. Enable this option to use a 20MHz SPI clock and 1355 disable "Dual Output Fast Read" Support. 1356 1357 On AMD platforms this changes the SPI speed at run-time if the 1358 mainboard code supports this. On supported Intel platforms this works 1359 by changing the settings in the descriptor.bin file. 1360 1361config DEBUG_ACPICA_COMPATIBLE 1362 bool "Print out ACPI tables in ACPICA compatible format" 1363 depends on HAVE_ACPI_TABLES 1364 help 1365 Select this to print out ACPI tables in an ACPICA compatible 1366 format. Set the console loglevel to verbosity 'SPEW'. 1367 To analyze ACPI tables capture the coreboot log between 1368 "Printing ACPI in ACPICA compatible table" and "Done printing 1369 ACPI in ACPICA compatible table". 1370 Remove the prefix "[SPEW ] " and then issue 'acpixtract -a dump' 1371 to extract all the tables. Then use 'iasl -d' on the .dat files 1372 to decompile the tables. 1373 1374endmenu 1375 1376############################################################################### 1377# Set variables with no prompt - these can be set anywhere, and putting at 1378# the end of this file gives the most flexibility. 1379 1380source "src/lib/Kconfig" 1381 1382config WARNINGS_ARE_ERRORS 1383 bool 1384 default y 1385 1386# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, 1387# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are 1388# mutually exclusive. One of these options must be selected in the 1389# mainboard Kconfig if the chipset supports enabling and disabling of 1390# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set 1391# in mainboard/Kconfig to know if the button should be enabled or not. 1392 1393config POWER_BUTTON_DEFAULT_ENABLE 1394 def_bool n 1395 help 1396 Select when the board has a power button which can optionally be 1397 disabled by the user. 1398 1399config POWER_BUTTON_DEFAULT_DISABLE 1400 def_bool n 1401 help 1402 Select when the board has a power button which can optionally be 1403 enabled by the user, e.g. when the board ships with a jumper over 1404 the power switch contacts. 1405 1406config POWER_BUTTON_FORCE_ENABLE 1407 def_bool n 1408 help 1409 Select when the board requires that the power button is always 1410 enabled. 1411 1412config POWER_BUTTON_FORCE_DISABLE 1413 def_bool n 1414 help 1415 Select when the board requires that the power button is always 1416 disabled, e.g. when it has been hardwired to ground. 1417 1418config POWER_BUTTON_IS_OPTIONAL 1419 bool 1420 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE 1421 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE) 1422 help 1423 Internal option that controls ENABLE_POWER_BUTTON visibility. 1424 1425config REG_SCRIPT 1426 bool 1427 default n 1428 help 1429 Internal option that controls whether we compile in register scripts. 1430 1431config MAX_REBOOT_CNT 1432 int 1433 default 3 1434 help 1435 Internal option that sets the maximum number of bootblock executions allowed 1436 with the normal image enabled before assuming the normal image is defective 1437 and switching to the fallback image. 1438 1439config UNCOMPRESSED_RAMSTAGE 1440 bool 1441 1442config NO_XIP_EARLY_STAGES 1443 bool 1444 default n if ARCH_X86 1445 default y 1446 help 1447 Identify if early stages are eXecute-In-Place(XIP). 1448 1449config EARLY_CBMEM_LIST 1450 bool 1451 default n 1452 help 1453 Enable display of CBMEM during romstage and postcar. 1454 1455config RELOCATABLE_MODULES 1456 bool 1457 help 1458 If RELOCATABLE_MODULES is selected then support is enabled for 1459 building relocatable modules in the RAM stage. Those modules can be 1460 loaded anywhere and all the relocations are handled automatically. 1461 1462config GENERIC_GPIO_LIB 1463 bool 1464 help 1465 If enabled, compile the generic GPIO library. A "generic" GPIO 1466 implies configurability usually found on SoCs, particularly the 1467 ability to control internal pull resistors. 1468 1469config BOOTBLOCK_CUSTOM 1470 # To be selected by arch, SoC or mainboard if it does not want use the normal 1471 # src/lib/bootblock.c#main() C entry point. 1472 bool 1473 1474config BOOTBLOCK_IN_CBFS 1475 bool 1476 default y if ARCH_X86 1477 help 1478 Select this on platforms that have a top aligned bootblock inside cbfs. 1479 1480config MEMLAYOUT_LD_FILE 1481 string 1482 default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/memlayout.ld" 1483 help 1484 This variable allows SoC/mainboard to supply in a custom linker file 1485 if required. This determines the linker file used for all the stages 1486 (bootblock, romstage, verstage, ramstage, postcar) in 1487 src/arch/${ARCH}/Makefile.mk. 1488 1489############################################################################### 1490# Set default values for symbols created before mainboards. This allows the 1491# option to be displayed in the general menu, but the default to be loaded in 1492# the mainboard if desired. 1493config COMPRESS_PRERAM_STAGES 1494 depends on (HAVE_ROMSTAGE || HAVE_VERSTAGE) && NO_XIP_EARLY_STAGES 1495 default y 1496 1497config INCLUDE_CONFIG_FILE 1498 default y 1499 1500config BOOTSPLASH_FILE 1501 depends on BOOTSPLASH_IMAGE 1502 default "bootsplash.jpg" 1503 1504config BOOTSPLASH_CONVERT_QUALITY 1505 depends on BOOTSPLASH_CONVERT 1506 default 80 1507 1508config BOOTSPLASH_CONVERT_RESOLUTION 1509 depends on BOOTSPLASH_CONVERT_RESIZE 1510 default "1024x768" 1511 1512config CBFS_SIZE 1513 default ROM_SIZE 1514 1515config HAVE_BOOTBLOCK 1516 bool 1517 default y 1518 1519config HAVE_VERSTAGE 1520 bool 1521 depends on VBOOT_SEPARATE_VERSTAGE 1522 default y 1523 1524config HAVE_ROMSTAGE 1525 bool 1526 depends on SEPARATE_ROMSTAGE 1527 default y 1528 1529config HAVE_RAMSTAGE 1530 bool 1531 default n if RAMPAYLOAD 1532 default y 1533 1534config SEPARATE_ROMSTAGE 1535 default y 1536
